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Hi all,
I am designing a PCB using an XC2S100 FPGA. Does anyone know where I can
find design considerations for this PCB, such powering, bypass capasitors,
etc. Is there something special I must pay attention to?
Thanks you in advance,
Stamatis
Article: 52651Hello, I am a new user of Spartan IIE FPGA, using ISE Web edition and the modelsim simulator (xilinx edition). I implemented a FIFO in a Spartan device, using a RAMB4_S8_S8 component (I use the VHDL examples of application note XAPP175), and I want to look at the evolution of the RAM block contents during the simulation. This is something I was able to do with ALTERA FPGA using the MAX+ or QUARTUS tools, and I can't get to work with the XILINX tools. Under Modelsim I have only access to the IO ports of the RAM block, and the init values. Is there a way to see these internal values ? The simulator must have knowledge of the internal RAM block contents (I hope :), but how can I display the associated waveforms ? thank you for any help. Pascal CADIC AVILINKSArticle: 52652
Hi folks,
I just want to check that what I have derived from previous newsgroup
postings/the Xilinx support site for my multi-cycle constraints is correct
and ask a couple of questions re the reports that ISE 5.1.02i is spitting
out.
My design has a master clock (CLK) of 150MHz and some parts are clock
enabled (CLKEN) at 75MHz - CLKEN is derived from the main CLK signal using a
counter within my design (CLK comes in on a pad).
The parts that are clock enabled will not run at 150MHz due to carry-ripples
in some of the adders etc. so I needed to find a way to tell the tools that
these parts of the circuit need only run at 75MHz (i.e. these parts actually
have 2 master CLK cycles before they need to be registered again).
So, I came up with some UCF constraints (given at the end) for this
situation and ran place and route to get the timing analysis.
The static timing analysis report says this:
=====================================
Timing constraint: TS_CLK = PERIOD
TIMEGRP "CLK" 6.660 nS HIGH 50.000000 % ;
2050 items analyzed, 0 timing errors detected.
Minimum period is 6.463ns.
-------------------------------------------------------
====================================
Timing constraint: TS_CLKEN = MAXDELAY
FROM TIMEGRP "CLKEN" TO TIMEGRP
"CLKEN" TS_CLK * 2.000 ;
55390 items analyzed, 0 timing errors detected.
Maximum delay is 11.156ns.
------------------------------------------------------
All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK | 11.156| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 57440 paths, 0 nets, and 6107 connections (99.9% coverage)
Design statistics:
Minimum period: 11.156ns (Maximum frequency: 89.638MHz)
Maximum path delay from/to any node: 11.156ns
So, no timing errors - fair enough.
However, the tools report the maximum frequency as being about 89MHz with
this number being derived from the "Maximum delay" of the TS_CLKEN timing
constraint.
Given that both the timing constraints TS_CLK and TS_CLKEN were met with 0
errors, I would have expected the tools to report the maximum frequency as
150MHz and give some sort of qualifying statement with respect to the logic
that will only meet timing when clock enabled at 75MHz...
Anyway, here are the questions:
(1)
Do my UCF constraints look ok for my purposes?
(2)
The Xilinx constraints editor found a whole load of clken signal instances
and I figured I would need to group them all - is this correct?
(3)
If my constraints are correct, does the fact that timing analysis reports 0
errors and a maximum clock freq of less than 150MHz mean that I will be ok
to clock this design at 150MHz and it will work ok (i..e the 75MHz enabled
logic will work ok along with the 150MHz logic) or am I missing something?
(4)
Why is the CLK signal being reported in the "Src Rise" to "Dest Rise" box
above as being 11.156 ns when it should be 6.463 ns as reported above that?
(5)
If there are no timing violations, surely my maximum frequency is 150MHz?
(6)
In the .PCF file, it seems like all of the signals in the design are grouped
under both the TIMEGRP "CLKEN" group and the TIMEGRP "CLK" group. Is this
what you would expect?
(7)
If I am up a gum tree, please point me in the right direction.... :-)
Thanks very much for your time,
Ken
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 6.66 ns HIGH 50 %;
NET "clken" TNM_NET = "CLKEN";
NET "clken_1" TNM_NET = "CLKEN";
NET "clken_2" TNM_NET = "CLKEN";
NET "clken_3" TNM_NET = "CLKEN";
NET "clken_4" TNM_NET = "CLKEN";
NET "clken_5" TNM_NET = "CLKEN";
NET "clken_6" TNM_NET = "CLKEN";
NET "clken_7" TNM_NET = "CLKEN";
NET "clken_8" TNM_NET = "CLKEN";
NET "clken_9" TNM_NET = "CLKEN";
NET "clken_10" TNM_NET = "CLKEN";
NET "clken_11" TNM_NET = "CLKEN";
NET "clken_12" TNM_NET = "CLKEN";
NET "clken_13" TNM_NET = "CLKEN";
NET "clken_14" TNM_NET = "CLKEN";
NET "clken_15" TNM_NET = "CLKEN";
NET "clken_16" TNM_NET = "CLKEN";
NET "clken_17" TNM_NET = "CLKEN";
NET "clken_18" TNM_NET = "CLKEN";
NET "clken_19" TNM_NET = "CLKEN";
NET "clken_20" TNM_NET = "CLKEN";
NET "clken_21" TNM_NET = "CLKEN";
NET "clken_22" TNM_NET = "CLKEN";
TIMESPEC "TS_CLKEN" = FROM "CLKEN" TO "CLKEN" "TS_CLK" * 2;
--
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Article: 52653There are some good info in the datasheets of both implementations. http://www.xilinx.com/ipcenter/catalog/logicore/docs/mac_fir.pdf http://www.xilinx.com/ipcenter/catalog/logicore/docs/da_fir.pdf HTH, Jim "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message news:t4ar0nx1CHA.2460@exchnews1.main.ntu.edu.sg... Hi all, Could anyone tell me the differences between Distributed Arithmetic FIR Filter and and MAC Filter ? Both are obtained from Xilinx Coregen. What is the pros/cons ? Thx. BuzzArticle: 52654
Hi John, The 5.2i version of Xilinx's XPower tool supports that device. More information on XPower is available here : http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=xpower. Brendan John wrote: > Brendan Cullen <bcullen@xilinx.com> wrote in message news:<3DE265EC.F7FE6A23@xilinx.com>... > > Hi John, > > > > > I'm about to use a Xilinx CoolRunner CPLD (running at ~30uA) and am > > > wondering what the best way is to measure the power consumption. I'm > > > looking for something relatively simple, which doesn't need to be > > > extremely accurate. Can I just measure the current draw across all the > > > VCC inputs and multiply those by VCC? What is the easiest circuit to > > > do this, since the currents will be so low - a BJT current amplifier? > > > Thanks! > > > > In particular, which CPLD device ? > > > > Brendan > > The XCR3256XL-TQ144. > > -JohnArticle: 52655
I was hoping that someone would have any VHDL code I could use for the Montgomery Serial n-bit multiplier. ThanksArticle: 52656
Philip Freidin wrote: > Try looking at http://www.fpga-faq.com/FPGA_Boards.htm > > In particular, look at WildCard from Annapolis Micro Systems > http://www.annapmicro.com/products.html > > Philip > > Philip, Frederic, thanks for the link. It is very close to my requirements. Unfortunately, 26 I/O lines is far off the mark. I would need something in the vicinity of 60-70. Do you know of any interface chips for Cardbus? The usual suspects (National/Zilog/etc) have all discontinued what they had.All I can find are ASICS for Ethernet and the like. Is this a global conspiracy against Cardbus developers? ;^) Regards, IwoArticle: 52657
Hi Does anybody know of any books or papers that discuss synthesis and execution efficiency as a function of HDL code layout? The reason I am asking this is that there must be ways of improving LE allocation by setting your code out in different manners. Normally there are several ways to write a piece of code to perform a specific operation. Which ways are better than others? I think all HDL programmers should be interested in this type of topic. Any thoughts or pointers?? RyanArticle: 52658
"geeko" <jibin@ushustech.com> wrote in message news:<b2spc6$1fgeh2$1@ID-159027.news.dfncis.de>... > Hi Jan > I am not so much worried about AHB interface any way it is a standard.I am > confused with the design of the core.The core will finally > become the part of an SoC which has ARM processor core .I want to get some > guidlines to the core design so as to make the core programmable by the ARM > processor.Any refrerence design or documents about a core design for an Soc Hmm, what kind of a core are you designing ? Perhaps you should take a look at www.opencores.org, there you will find many, many different IP cores. Perhaps doing some research on your own will answer your question. Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV ----- > "Jan De Ceuster" <Jan.DeCeuster@elis.rug.ac.be> wrote in message > news:3E50DFB4.BBFFE817@elis.rug.ac.be... > > > Hi all > > > I have a problem with the design of an SoC peripheral cell to be used in > an > > > SoC with AHB interface .I am new to this area.Any resource or advices > > > regarding the design of an SoC peripheral > > > > > > Thanks in Advance > > > Regards Geeko > > > > Geeko, what is exactly your problem? You're a bit vague here. > > For the AHB interface itself you should look into the AMBAv2.0 spec > > which is downloadable at the ARM website. Nothing is going to help you > > more than that spec because ARM did a good job in creating this > > document. > > > > JanArticle: 52659
monarchy_99@rediffmail.com (Ken Frawley) wrote in message news:<57b62fba.0302171027.4ee8828c@posting.google.com>... > Hi, > > I've been using Fpga Compiler2 version 3.6.0 for a long time now. I > got to try out their newest version 3.7.2 and found its much better > than all of their earlier versions so far. > > For one, it was very very fast compared to 3.6.0. And also seems to > support a lot more HDL constructs. I'd like to try a few more things > through it before going for an upgrade. > > Let me know if anybody's used it and if an upgrade is justified. > > Ken Hi Ken, Upgrade decision depends on several factors. I too have used Fpga Complier 3.7.2 version. My DSP application targetted to Virtex2 used to crash with 371. With the latest one, it not only goes through fine, I can target to speed 6 which was not available earlier. If all your target technology is centered around Xilinx, probably you could upgrade. If your requirement is centred around Actel APA/RT74SX devices, then this latest version does not have that support. I 'm looking out for some other for this support. RhodneyArticle: 52660
hi, Leonardo is giving different Flop count, if I target same design(arround 10K gate) to ASIC technology and FPGA technology. Please let me what could be the possible reasons! Thanks, Valli.Article: 52661
At xilinx.com, do a search in "Everything" (not just the "AnswerDatabase") for "PCB" and you'll find such entries as Xilinx Design Hints: Printed Circuit Board Design Considerations (XCell Journal 28 article, Q2 98) http://www.xilinx.com/xcell/xl28/xl28_22.pdf and Xilinx Home : Products and Solutions : System Resources : Signal Integrity : PCB Checklist http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?iLanguageID=1&iCountryID= 1&title=si_pcbcheck Although the following .pdf is for the Virtex-II devices, you can probably find a lot of applicable information in the Virtex-II Platform FPGA User Guide http://www.xilinx.com/publications/products/v2/ug_pdf/ug002.pdf "Stamatis Sotiropoulos" <ssothro@hotmail.com> wrote in message news:b2tdtg$1g98$1@ulysses.noc.ntua.gr... > Hi all, > I am designing a PCB using an XC2S100 FPGA. Does anyone know where I can > find design considerations for this PCB, such powering, bypass capasitors, > etc. Is there something special I must pay attention to? > > Thanks you in advance, > Stamatis > > >Article: 52662
> I've used 3.6 for ca. 1 year and then switched to 3.7 but I had so > many fatal errors (even on the same source which worked fine with > 3.6!) that I gave up FC2. 3.7 was several times faster than 3.6 > though. This was under Solaris 7. This is the exact reason I hadn't upgraded to 3.7 But version 3.7.2 seems to have solved these problems. -Ken Petter Gustad <newsmailcomp4@gustad.com> wrote in message news:<m3znoux9zq.fsf@scimul.dolphinics.no>... > hereisjunk@yahoo.com (Nicholas Girde) writes: > > > Yes, I've tried it out and I'd say that 3.7.2 is certainly the most > > stable FC2 version so far. Retiming seems to have been finally fixed. > > Its also very fast without compromising on the QOR. So an upgrade is > > definetely worth it. > > I've used 3.6 for ca. 1 year and then switched to 3.7 but I had so > many fatal errors (even on the same source which worked fine with > 3.6!) that I gave up FC2. 3.7 was several times faster than 3.6 > though. This was under Solaris 7. > > Does anybody know anything about DC FPGA? I'm a long time DC user and > would like a synthesis tool which has the DC front-end scripting > capabilities but with an efficient FPGA synthesis engine. > > PetterArticle: 52664
Could anyone tell me what is the multiplier algorthm used by the hardware multiplier blocks in Xilinx Virtex-II P FPGAs? Is it Booth, Wallace tree, what?Article: 52665
> I'd need to have a TCP/IP stack I'm not really sure if you need a full blown TCP/IP stack. Look at those thumbnail "webservers" based on PIC12. I'm sure one can implement a minimalistic subset of TCP/IP that is able to download the bitstream via HTTP from certain webservers in the LAN. A PIC12 is very cheap and tiny, certainly cheaper than the ethernet interface itself.Article: 52666
In article <af3f5bb5.0302180957.6724f8a4@posting.google.com>, jetmarc <jetmarc@hotmail.com> wrote: >> I'd need to have a TCP/IP stack > >I'm not really sure if you need a full blown TCP/IP stack. Look at those >thumbnail "webservers" based on PIC12. I'm sure one can implement a >minimalistic subset of TCP/IP that is able to download the bitstream >via HTTP from certain webservers in the LAN. A PIC12 is very cheap and >tiny, certainly cheaper than the ethernet interface itself. Also, TCP may be hairy and complicated, but the MINIMUM isn't that nasty. If you keep window size at 0, ack packets one at a time, you get cruddy throughput, but you get all the reliability and compatability you need. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 52667
Hello again! Sorry for incovenience, this is a repost with some precisions... I changed for a more explicit title as there was no reaction to my previous post titled "JTAG and SVF" a few days ago (I admit the title was a bit cryptic). Maybe I am a bit too impatient, yet I am sure many people would be interested by this issue as there is very little information about it on the net, and yet it is a very important matter for FPGA designs - debugging as well as configuring. Almost every FPGA has a JTAG interface, so it seems natural to use it instead of creating an UART, putting a MAX232 and talking through a PC serial link, or using similar solutions that require extra hardware. I would like to use USER1/USER2 JTAG mechanism to communicate with my FPGA project once configured, for debugging or data loading. Or is there a better way to take advantage of the JTAG interface? As it is a Xilinx Spartan II, I understand that I can use the BSCAN_SPARTAN2 component , refer to Xilinx appnotes 058/138/139. Then I should create an SVF file (cf appnote 503) and play it with Xilinx' playxsvf.exe. The mystery becomes even darker for the RDBK component that allows to view the state of a configured device... any practical information would be most welcome! I have dug a lot on this newsgroup and on the Internet, and I found a lot of interesting information, but... no concrete examples showing an SVF file using USER1 instruction and a simple FPGA design instantiating BSCAN_SPARTAN2, and how to get the data back and forth. I am sure I am not the first newbie to ask the question. Could anyone please give me suggestions and/or examples of communication with a configured FPGA through a JTAG interface? Thank you in advance for your help. -- Frederic Bastenaire (fba@free.fr)Article: 52668
On Tue, 18 Feb 2003 14:59:58 +0000, Iwo Mergler <Iwo.mergler@soton.sc.philips.com> wrote: >Philip Freidin wrote: >> Try looking at http://www.fpga-faq.com/FPGA_Boards.htm >> >> In particular, look at WildCard from Annapolis Micro Systems >> http://www.annapmicro.com/products.html >> >> Philip >> >> > >Philip, Frederic, > >thanks for the link. It is very close to my requirements. >Unfortunately, 26 I/O lines is far off the mark. I would >need something in the vicinity of 60-70. This is the only general FPGA PCMCIA card I know of. >Do you know of any interface chips for Cardbus? The usual >suspects (National/Zilog/etc) have all discontinued what >they had.All I can find are ASICS for Ethernet and the like. Nope >Is this a global conspiracy against Cardbus developers? ;^) Maybe. Check with the Trilateral Commission. :-) >Regards, > >Iwo Philip Freidin FliptronicsArticle: 52669
The algorithm is the popular "Modified Booth". Peter Alfke, Xilinx Applications ================================ RM wrote: > Could anyone tell me what is the multiplier > algorthm used by the hardware multiplier blocks > in Xilinx Virtex-II P FPGAs? Is it Booth, Wallace > tree, what?Article: 52670
The USER1 and USER2 Jtag commands have nothing with the rdbk symbol or function. The Jtag interface is always present in a Xilinx Virtex device. One of the commands is the USER commands. These will allow you to read and write to an internal register that you hook up to the BSCAN symbol. You can use the player but it is simple to use the Jtag interface if you read up on it a little. It is a 16 tap state machine with TMS and TCK controling which state you are in. TDI and TDO are the data in and out. TI has a nice little demo and simulator for Jtag. I think it is at... http://www-s.ti.com/sc/psheets/satb002a/satb002a.zip Steve "Frederic Bastenaire" <fba@free.fr> wrote in message news:3e527722$0$7890$626a54ce@news.free.fr... > Hello again! > > Sorry for incovenience, this is a repost with some precisions... I changed > > for a more explicit title as there was no reaction to > > my previous post titled "JTAG and SVF" a few days ago (I admit the title was > > a bit cryptic). > > Maybe I am a bit too impatient, yet I am sure many people would be > > interested by this issue > > as there is very little information about it on the net, and yet it is a > > very important matter > > for FPGA designs - debugging as well as configuring. > > Almost every FPGA has a JTAG interface, so it seems natural to use it > > instead of creating an UART, > > putting a MAX232 and talking through a PC serial link, or using similar > > solutions that require extra hardware. > > I would like to use USER1/USER2 JTAG mechanism to communicate with my FPGA > > project once configured, for debugging or data loading. Or is there a better > > way to take advantage > > of the JTAG interface? > > As it is a Xilinx Spartan II, I understand that I can use the BSCAN_SPARTAN2 > > component , refer to Xilinx appnotes 058/138/139. > > Then I should create an SVF file (cf appnote 503) and play it with Xilinx' > > playxsvf.exe. > > The mystery becomes even darker for the RDBK component that allows to view > > the > > state of a configured device... any practical information would be most > > welcome! > > I have dug a lot on this newsgroup and on the Internet, and I found a lot of > > interesting information, but... no concrete examples showing > > an SVF file using USER1 instruction and a simple FPGA design instantiating > > BSCAN_SPARTAN2, and how to get the data back and forth. > > I am sure I am not the first newbie to ask the question. > > Could anyone please give me suggestions and/or examples of communication > > with a configured FPGA through a JTAG interface? > > Thank you in advance for your help. > > -- > > Frederic Bastenaire (fba@free.fr) > > >Article: 52672
Hello,
Im compiling a Verilog Code (XST Verilog) for a Xilinx FPGA (Virtex-E 600)
but the process fails, I dont know why.
this is what I get:
Analyzing top module <main>.
WARNING : (VLG__6004). "main.v", line 21: Name conflict (<I> and <i>,
renaming I as i_rnm0).
WARNING : (VLG__4010). "main.v", line 165: The signals <count, clk_index,
PId, IQoutd, PQd, Itemp, IQtemp, addr, i_rnm0, Iin, Q, Qin, eId, eQd, PId2,
PQd2, shift> are missing in the sensitivity list of always block.
Module <main> is correct for synthesis.
Synthesizing Unit <main>.
Extracting 3-bit up counter for signal <count>.
Extracting T flip-flop for signal <IQclk>.
Extracting 10-bit up counter for signal <addr>.
Extracting T flip-flop for signal <clk_index>.
Extracting 12-bit register for signal <Itemp>.
Extracting 12-bit register for signal <Qtemp>.
Extracting 12-bit register for signal <i_rnm0>.
Extracting 12-bit register for signal <Q>.
WARNING : (ADVISOR__0001). Extracting 12-bit latch for signal <IQDAC>.
.......
.......
WARNING : (ADVISOR__0001). Extracting 1-bit latch for signal <eQ<0>>.
Extracting 32-bit 2-to-1 multiplexer for internal node.
Done: failed with exit code: 0002.
Any help will be very appreciated.Thanks
Laura
Article: 52673> Do you know of any interface chips for Cardbus? The usual > suspects (National/Zilog/etc) have all discontinued what > they had.All I can find are ASICS for Ethernet and the like. AFAIK CardBus is very similar to PCI so you should be able to modify a PCI-Core to build a CardBus Card. The 16-Bit PCCard interface is extremly simple and should fit into a smaller CPLD. You could use this if you want to reconfigure your FPGA dynamically. Kolja SulimmaArticle: 52674
> Hi all, > I am designing a PCB using an XC2S100 FPGA. Does anyone know where I can > find design considerations for this PCB, such powering, bypass capasitors, > etc. Is there something special I must pay attention to? What kind of package do you use? If you do a two layer board you must be very careful with your power routing. Usually you have three power supply rails and only one layer to connect them to the FPGA. With four layers live is simple. The amount of bypass capacitors necessary varies with the amount of simultenous switching going on and the slew rates selected for the outputs. Usually you do not need one capacitors per power/ground pair. But there are people who suggest that you should, and if your application is more demanding with respect to transient power, you should folow theire advice. Surely every power and ground pin should have a very short connection to a capacitor and the capacitor should have a small SMD outline and a low ESR dielectricum. I remember seeing Xilinx application notes on PCB design. At least for the ball grid packages there are detailed guidelines. Kolja Sulimma
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