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> Hi all > I have a problem with the design of an SoC peripheral cell to be used in an > SoC with AHB interface .I am new to this area.Any resource or advices > regarding the design of an SoC peripheral > > Thanks in Advance > Regards Geeko Geeko, what is exactly your problem? You're a bit vague here. For the AHB interface itself you should look into the AMBAv2.0 spec which is downloadable at the ARM website. Nothing is going to help you more than that spec because ARM did a good job in creating this document. JanArticle: 52626
Hello,
We are trying to generate a sine wave using the dsp iir filter
method but not able to get a sine wave. The vhdl code simulates a
correct sine wave output but the synthesized code does not give any
output on the fpga (xilinx virtex 2, xv2000).
The process is given below for reference
------------ begin vhdl code --------------------
process(rstl,clk_osc) --rstl is derived from the system reset., clk
--> clock
begin
if(rstl ='0') then --initializations.
y(2)<=-800;
y(3)<=0;
temp<=0;
elsif( clk_osc'event and clk_osc ='1') then
y(3)<=y(2);
y(2)<=output;
output<=2*8127*y(2)/8192-y(3);
tempor<= not conv_std_logic_vector(output,14) ; --ieee.arith**
DAC1_D<= not tempor(13) & tempor(12 downto 0);
end if;
end process;
---------------- end code-------------------
Any help will be appreciated.
Thanks,
Regards,
Akshay Mishra
Article: 52627Hi, I'm looking for a PCMCIA card with programable logic inside. Something with a Spartan or large CPLD. I have spent a large amount of time now, trying to find a commercial product - with no success. I almost resigned to the fact that I'll have to design my own. Do you know of someone selling this kind of devices? It would save a lot of time+money if I could buy it off-the-shelf... Thanks in advance, IwoArticle: 52628
Assaf Sarfati wrote: > "Kris Vorwerk" <no@one.here.org> wrote in message news:<itT3a.236$sv3.87671@news20.bellglobal.com>... > > Hi there, > > > > I have a general question about programming FPGAs. > > > > I'm in the very early planning phase of a design. The system that I've been > > planning would basically connect a few small PCBs together through an > > Ethernet interface (on each PCB). Each PCB would also have an FPGA on it. > > Some of my early prototype designs have used CPLDs (which retain their > > configuration after power loss), and to program them, I manually connected > > my boards to a JTAG interface. (They were prototypes :) > > > > Now, with the amount and size of my logic, FPGAs are starting to make more > > sense, so I'm thinking of replacing the CPLDs with FPGAs. I really like the > > idea of having my boards automatically download bitfiles from a central > > server (over the ethernet connection) at device power-on. This would make > > bug fixes and feature enhancements a breeze. > > > > Has anyone here tried to setup their boards to automatically program over a > > network, and can you share any experiences? Any specific FPGAs, CPLDs, > > controllers, app notes, etc. that greatly simplified your life when you > > tried this? > > > > [I realize that there are a few immediate problems with my idea (e.g., I'd > > need to have a TCP/IP stack, etc), so I was thinking that I could use a ROM > > to "bootstrap" my FPGA, install an initial TCP/IP stack, have the FPGA seek > > the bitfile over the network, download the bitfile, and have external logic > > reprogram the device. This seems a little excessive, and was thinking that > > there must be a cleaner/faster/better/cheaper way ...] > > > > Regards, > > -kris > > If your board has an independent CPU, you can use it to program the > FPGA from a bitfile in boot ROM; of course, your CPU should be able to > run, at least a little, without the FPGA (DON'T put your ROM CS logic > in the FPGA - been there, done that, had to kick myself in the butt). > After everything had been configured, the CPU can check the server for > a newer version of the FPGA bitfile and save it in its ROM (flash, of > course) for the next time. It can also reload the FPGA immediately if > required (fix for a big bug). > > If your board doesn't have an independent CPU (for example, your CPU > is inside the FPGA), you must use an automatic loader. The simplest > loader is a serial-ROM chip designed specifically for your FPGA (each > RAM-based FPGA has one; sadly, they are specific to each manufacturer, > sometimes to one FPGA family). This is the easiest solution, but they > are very expensive chips (flash-based are hideously expensive; OTP are > merely expensive, and must be socketed). If you are converting from > CPLDs, you probably won't like using a 20$ ROM (IIRC, those were the > prices for a flash-based ROM) for a 3$ FPGA. > Partially true... The flash parts _are_ very expensive. For a spartan2e (XC2s50e-7tq144c) the FPGA is about $15. The spartan flash part is about $22. The atmel serial EEPROM is about the same price. The OTP EPROM from Xilinx is about $3. (All prices are for US dollars in small quantities. These prices are based on my memory so...) What I do is use the Atmel part for development and the OTP EPROM for production. These are both available in 8 pin dip packages. The dip packages are pin-for-pin compatible. (Drop in replacements.) If I recall correctly, the spartan part is also available in a 8 pin SOIC. I don't thing the EEPROM is available in an SOIC. As stated, the PROMs are largely device specific. Theron > > Another solution is to use a standard parallel flash-ROM and a small > CPLD to load the bitfile to the chip; both Altera and Xilix have app > notes about how to do it. It requires more design effort and board > space, but will probably be cheaper on the long run.Article: 52629
Akshay, Has your part really finished loading (Is done high?) From my experience, if the simulation is correct and the part has completed loading the output is almost certainly correct. I assume that you must have some sort of D/A converter. Are you sure that the problem is not with the D/A converter or other external circuitry? Theron Akshay wrote: > Hello, > We are trying to generate a sine wave using the dsp iir filter > method but not able to get a sine wave. The vhdl code simulates a > correct sine wave output but the synthesized code does not give any > output on the fpga (xilinx virtex 2, xv2000). > > The process is given below for reference > > ------------ begin vhdl code -------------------- > > process(rstl,clk_osc) --rstl is derived from the system reset., clk > --> clock > begin > if(rstl ='0') then --initializations. > y(2)<=-800; > y(3)<=0; > temp<=0; > > elsif( clk_osc'event and clk_osc ='1') then > > y(3)<=y(2); > y(2)<=output; > output<=2*8127*y(2)/8192-y(3); > tempor<= not conv_std_logic_vector(output,14) ; --ieee.arith** > > DAC1_D<= not tempor(13) & tempor(12 downto 0); > > end if; > end process; > ---------------- end code------------------- > > Any help will be appreciated. > > Thanks, > Regards, > Akshay MishraArticle: 52630
Thanks for the link but I'm still having some problems. Specifically I have two questions: (1) Can I use a Fibonacci architecture to yield an equivalent output/register state to my Galois architecture? (2) If I translate the polynomial (as per the link posted previously) what translation must I apply to the initial state of the register? A lot of the information I can find seems to avoid these questions. Thanks, Chris.Article: 52631
Dear Akshay, I would be very concerned about precision. > output<=2*8127*y(2)/8192-y(3); I think you are trying to say output <= [ 1.98413 * y(2) ] - y(3) but I would be most surprised if that is what your code will actually get synthesized to represent. It is almost as if you are writing VHDL as if it is some sort of software language with arrays and floating point precision. I'm afraid it isn't, so you should work out the precision required to represent your coefficients and the then the precision required to maintain correct stability around the feedback loop. I have just implemented a DTMF tone generator using PicoBlaze and a similar algorithm, but I needed to do a mathematical modeling and simulations first. Ken ChapmanArticle: 52632
Martin Sauer wrote: > Hello, > > I want to compile the VHDL model of a IDT fifo memory (I found it on > www.eda.org/fmf), but the Xilinx WebPack 5.1 produces only the following > messages: > > ERROR:HDLParsers:3014 - > L:/Sonstiges/Entwicklung/FPGA/FreeModelFoundry/Fifo/WebPack/idt/../../VHDL-Code/library_fmf/gen_utils.vhd > Line 22. Library unit vital_primitives is not available in library ieee. > > Is there a possibility to compile such vhdl module? Not sure what you are trying to do. Are you trying to synthesize the IDT fifo into a Xilinx architecture? The model you obtained from fmf is not intended to be synthesizable. You should look on the Xilinx website for info on synthesizable fifo models. Also, a FIFO is an easy thing to do yourself from scratch. Otherwise, for simulation with the FMF FIFO model, you need to get and compile (also available on the FMF website) the files conversions_b.vhd, conversions_p.vhd, and gen_utils.vhd. -- My real email is akamail.com@dclark (or something like that).Article: 52633
Hi, I've been using Fpga Compiler2 version 3.6.0 for a long time now. I got to try out their newest version 3.7.2 and found its much better than all of their earlier versions so far. For one, it was very very fast compared to 3.6.0. And also seems to support a lot more HDL constructs. I'd like to try a few more things through it before going for an upgrade. Let me know if anybody's used it and if an upgrade is justified. KenArticle: 52634
Hi, take a look at the Wildcard (XCX300 based) for $999 on http://www.annapmicro.com/products.html Yours, FB > I'm looking for a PCMCIA card with programable logic > inside. Something with a Spartan or large CPLD. > I have spent a large amount of time now, trying to > find a commercial product - with no success. I almost > resigned to the fact that I'll have to design my own. >Article: 52635
When you synthesize your design, if you are instantiating a Xilinx-specific component (like IBUF or sram), then your synthesis engine (ie: Synplify or Synopsys or whatever) will replace these components with a "black box" implementation, so that the PAR knows to use the componets you've instantiated, ie: by using the RAM block for contiguous sram versus using registers in the CLBs Essentially, the wanrings are not a problem and shouldn't adversly affect your design.Article: 52636
Hi! > If your board has an independent CPU, you can use it to program the FPGA > from a bitfile in boot ROM; of course, your CPU should be able to run, > at least a little, without the FPGA (DON'T put your ROM CS logic in the > FPGA - been there, done that, had to kick myself in the butt). After > everything had been configured, the CPU can check the server for a newer > version of the FPGA bitfile and save it in its ROM (flash, of course) > for the next time. It can also reload the FPGA immediately if required > (fix for a big bug). Yesterday I found the DC80C400 at the Maxim web site. http://www.maxim-ic.com/quick_view2.cfm?qv_pk=3609 This is a heavily enhanced 8051 derivate. It has a built in Ethernet MAC, 64k Boot ROM, ... You only need the PHY, magnetigs and a connector (probably in a single case, like from Halo Electronics (FastJack)). The Boot ROM has a built in TCP/IP stack. The chip can be switched on without any external EPROMs (it only needs 64k external SRAM). It then initializes itself, takes the MAC-Address from a little EEPROM (DS2502-E48, don't wonder that you can't find it on Maxims web site, it's very new) and does a DHCP query on the Ethernet. Then it downloads its firmware from the TFTP server announce in the DHCP setup packet. After finishing that the firmware is executed. Since all the procedures to do these jobs are in the Boot ROM, your application can use these too. You can then again contact the TFTP server within you firmware. Download the FPGA config and configure the FPGA. Bye HansiArticle: 52637
Hi all, Does anybody know how to monitor FPGA die temperature? I am interested in Xilinx Virtex2, spent last 2 hours searching and found nothing... Thanks, jakabArticle: 52638
Try looking at http://www.fpga-faq.com/FPGA_Boards.htm
In particular, look at WildCard from Annapolis Micro Systems
http://www.annapmicro.com/products.html
Philip
On Mon, 17 Feb 2003 13:43:30 +0000, Iwo Mergler <Iwo.mergler@soton.sc.philips.com> wrote:
>Hi,
>
>I'm looking for a PCMCIA card with programable logic
>inside. Something with a Spartan or large CPLD.
>I have spent a large amount of time now, trying to
>find a commercial product - with no success. I almost
>resigned to the fact that I'll have to design my own.
>
>Do you know of someone selling this kind of devices?
>It would save a lot of time+money if I could buy
>it off-the-shelf...
>
>Thanks in advance,
>
>Iwo
===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM
Article: 52639Hi, You might want to consider writing a conventional test-bench to generate the stimulus for your device-under-test. Its only a little extra work but well worth while if you want to modify or expand the test cases performed. In this case, shifting the clock by a fixed delay is quite easy to do. cheers, Chris "Stefano M" <stefano.mora@antispam.libero.it> wrote in message news:<b2qja6$3tq$1@fata.cs.interbusiness.it>... > Hello, > i'm drawing some waveforms to test my implementation. > I need to draw within Xilinx HDL Bench an input signal that > start AFTER a little time respect rising edge of the > clock and not BEFORE rising edge. > How can i set the program to do that ? > > Thanks a lotArticle: 52640
Search Google Groups for "xilinx temperature-sensing diode" (do not include quotes) will give you the answer. HTH, Jim "jakab tanko" <jtanko@ics-ltd.com> wrote in message news:b2rjnu$3t9$1@news.storm.ca... > Hi all, > > Does anybody know how to monitor FPGA die temperature? > I am interested in Xilinx Virtex2, spent last 2 hours searching > and found nothing... > Thanks, > jakab > >Article: 52641
Hi, Try the post P&R simulation with and without the timing info back-annotated (this is in the SDF file). Simulating without timing info is just to confirm that no steps in the tool-flow have corrupted the netlist. When simulating with the timing info back annotated, you need to watch for the setup and hold requirements on the input FF's vs the clock, as there is delay associated with the routing of the clock net from the pin to the FF Clk input. (Global clock routing keeps the skew to all FF Clk inputs low, but there is still a fixed amount of delay due to the BUFG etc). You can try manually adding delay to the clock in the test-bench or instantiate a DCM to phase-shift the clock so the input FF's timing requirements are met again. Chris rathanon99@yahoo.com (ron) wrote in message news:<c661162.0302162134.4582fbb5@posting.google.com>... > I am using XILINX ISE in implementing my VHDL design in FPGA and I > simulate my design in Modelsim. The problem is the post map simulation > is correct but the post PAR simulation is wrong. I really have no idea > on how to remedy this problem. Please help. Thank you!Article: 52642
On Sun, 16 Feb 2003 22:13:41 -0800, Assaf Sarfati wrote: > "Kris Vorwerk" <no@one.here.org> wrote in message > news:<itT3a.236$sv3.87671@news20.bellglobal.com>... >> Hi there, >> >> I have a general question about programming FPGAs. >> >> I'm in the very early planning phase of a design. The system that I've >> been planning would basically connect a few small PCBs together through >> an Ethernet interface (on each PCB). Each PCB would also have an FPGA >> on it. Some of my early prototype designs have used CPLDs (which retain >> their configuration after power loss), and to program them, I manually >> connected my boards to a JTAG interface. (They were prototypes :) >> >> Now, with the amount and size of my logic, FPGAs are starting to make >> more sense, so I'm thinking of replacing the CPLDs with FPGAs. I >> really like the idea of having my boards automatically download >> bitfiles from a central server (over the ethernet connection) at device >> power-on. This would make bug fixes and feature enhancements a breeze. >> >> Has anyone here tried to setup their boards to automatically program >> over a network, and can you share any experiences? Any specific FPGAs, >> CPLDs, controllers, app notes, etc. that greatly simplified your life >> when you tried this? >> >> [I realize that there are a few immediate problems with my idea (e.g., >> I'd need to have a TCP/IP stack, etc), so I was thinking that I could >> use a ROM to "bootstrap" my FPGA, install an initial TCP/IP stack, have >> the FPGA seek the bitfile over the network, download the bitfile, and >> have external logic reprogram the device. This seems a little >> excessive, and was thinking that there must be a >> cleaner/faster/better/cheaper way ...] >> >> Regards, >> -kris > > If your board has an independent CPU, you can use it to program the FPGA > from a bitfile in boot ROM; of course, your CPU should be able to run, > at least a little, without the FPGA (DON'T put your ROM CS logic in the > FPGA - been there, done that, had to kick myself in the butt). After > everything had been configured, the CPU can check the server for a newer > version of the FPGA bitfile and save it in its ROM (flash, of course) > for the next time. It can also reload the FPGA immediately if required > (fix for a big bug). > > If your board doesn't have an independent CPU (for example, your CPU is > inside the FPGA), you must use an automatic loader. The simplest loader > is a serial-ROM chip designed specifically for your FPGA (each RAM-based > FPGA has one; sadly, they are specific to each manufacturer, sometimes > to one FPGA family). This is the easiest solution, but they are very > expensive chips (flash-based are hideously expensive; OTP are merely > expensive, and must be socketed). If you are converting from CPLDs, you > probably won't like using a 20$ ROM (IIRC, those were the prices for a > flash-based ROM) for a 3$ FPGA. > > Another solution is to use a standard parallel flash-ROM and a small > CPLD to load the bitfile to the chip; both Altera and Xilix have app > notes about how to do it. It requires more design effort and board > space, but will probably be cheaper on the long run. Actually a $1.35 SST 45LF010 serial flash chip (1 M bit) and a $.80 8 pin PIC will support up to 200K Spartan II/IIe parts (and maybe 300K not sure what the 300K configuration size is) I can make the PIC code available if anyone wants it (it supprts serial download to the flash) Peter WallaceArticle: 52643
Yes, I've tried it out and I'd say that 3.7.2 is certainly the most stable FC2 version so far. Retiming seems to have been finally fixed. Its also very fast without compromising on the QOR. So an upgrade is definetely worth it. -Nick monarchy_99@rediffmail.com (Ken Frawley) wrote in message news:<57b62fba.0302171027.4ee8828c@posting.google.com>... > Hi, > > I've been using Fpga Compiler2 version 3.6.0 for a long time now. I > got to try out their newest version 3.7.2 and found its much better > than all of their earlier versions so far. > > For one, it was very very fast compared to 3.6.0. And also seems to > support a lot more HDL constructs. I'd like to try a few more things > through it before going for an upgrade. > > Let me know if anybody's used it and if an upgrade is justified. > > KenArticle: 52644
On 17 Feb 2003 07:11:21 -0800, chris.p.ward@ntlworld.com (Chris Ward) wrote: >Thanks for the link but I'm still having some problems. > >Specifically I have two questions: > >(1) Can I use a Fibonacci architecture to yield an equivalent >output/register state to my Galois architecture? Yes. The state of the registers will be related by a linear function (where a "linear function" is a sea of XOR gates). For a polynomial of width N bits, you will need roughly N N/2 input XOR gates (IIRC). You can work out how many LUT4s (or whatever gates you are using) that is. >(2) If I translate the polynomial (as per the link posted previously) >what translation must I apply to the initial state of the register? See above. Working out the exact function is left as an exercise for the reader (which is another way of saying I don't know right now). But if it's a small polynomial (say, 16 bits or less) then it's easy enough to use a brute force method in software to create a big lookup table to do the translation. But since both the Fibbonacci and Galois versions produce the same sequence, you could encode the difference as an integer that represents the number of times you would need to iterate the Fibbonacci FSM to get it to the same point in the sequence as the Galois one, given the same starting state. This would take more time, but less hardware than the previous method. >A lot of the information I can find seems to avoid these questions. Probably because it's not something that's done that often. Why are you interested in the exact start value? We use LFSRs for a lot of things (BERT, etc.) but we usually don't care about the start value. Regards, Allan.Article: 52645
Hi all, Could anyone tell me the differences between Distributed Arithmetic FIR = Filter and and MAC Filter ? Both are obtained from Xilinx Coregen. What is the pros/cons ? Thx. BuzzArticle: 52646
In comp.lang.vhdl geeko <jibin@ushustech.com> wrote: All bus-protocols are easily described as state machines. If your peripheral is a simple slave, your only concern is pretty much whether you want to insert wait-states or not. I'd prefer the register-file approach, in which your peripheral is just a location in the memory space. You work with predefined delays (ie. how long it takes to read or write a certain location) which leads to fixed wait-states and eases the design (If I remember correctly AHB master can not insert wait states, so you don't have to worry about that). I know this sounded like a bunch of mambo jambo, but start simple and design a unit with only one n-bit register, make it read-only and work from there up. And keep it synchronous... regards, juza : I have a problem with the design of an SoC peripheral cell to be used in an : SoC with AHB interface .I am new to this area.Any resource or advices : regarding the design of an SoC peripheral : Thanks in Advance : Regards Geeko -- JuzaArticle: 52647
Hi Jan I am not so much worried about AHB interface any way it is a standard.I am confused with the design of the core.The core will finally become the part of an SoC which has ARM processor core .I want to get some guidlines to the core design so as to make the core programmable by the ARM processor.Any refrerence design or documents about a core design for an Soc "Jan De Ceuster" <Jan.DeCeuster@elis.rug.ac.be> wrote in message news:3E50DFB4.BBFFE817@elis.rug.ac.be... > > Hi all > > I have a problem with the design of an SoC peripheral cell to be used in an > > SoC with AHB interface .I am new to this area.Any resource or advices > > regarding the design of an SoC peripheral > > > > Thanks in Advance > > Regards Geeko > > Geeko, what is exactly your problem? You're a bit vague here. > For the AHB interface itself you should look into the AMBAv2.0 spec > which is downloadable at the ARM website. Nothing is going to help you > more than that spec because ARM did a good job in creating this > document. > > JanArticle: 52648
hereisjunk@yahoo.com (Nicholas Girde) writes: > Yes, I've tried it out and I'd say that 3.7.2 is certainly the most > stable FC2 version so far. Retiming seems to have been finally fixed. > Its also very fast without compromising on the QOR. So an upgrade is > definetely worth it. I've used 3.6 for ca. 1 year and then switched to 3.7 but I had so many fatal errors (even on the same source which worked fine with 3.6!) that I gave up FC2. 3.7 was several times faster than 3.6 though. This was under Solaris 7. Does anybody know anything about DC FPGA? I'm a long time DC user and would like a synthesis tool which has the DC front-end scripting capabilities but with an efficient FPGA synthesis engine. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 52649
Allan,
The application is for a CRC calculation engine.
I have an existing Galois design which I would like to implement using
a Fibonacci architecture. (If you're interested, I'm doing this
because I am experimenting with moving the design into a DSP which
provides for Fibonacci LFSRs within its instruction set.)
Specifically, I need to determine:
(1) the poly
(2) the start state for the Fibonacci design
(3) the linear function to transfrom the final state to that
of the Galois (to yield the CRC).
However, I am beginning think that I may not be able to do this for
two reasons:
(I) In the non-autonomous LFSRs, mapping the input bit
'connection' of one architecture to the other requires a
non-singular 'connection' (I think)
(II) the need to apply a linear function to translate the final
state could require a fairly large LUT.
Chris.
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