Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Martin Schoeberl wrote: > > > What we want to do is to use a nand-flash device to configure the fpga to > > further reduce cost plus the nand flash can also be used as a mass storage > > device. The idea is to use a 16 bit flash , 8 bits containing the > > configuration code, 6 bits to do error correction (nand flash is not > > garanteed error free). The error correction and the nandflash interface > > could be handled by a cpld. > > An interesting idea. I thought about the same for an Altera FPGA (Cyclone) > board. The problem is similar for X and A. But in a nand-flash you have > complete bad blocks. This makes logic in the CPLD pretty complex. > I decided to go the 'convential' way with a very small CPLD (MAX7064) and a > 4Mbit flash for configuration and some application data and an optional > nand-flash. Both flash are programmed via the FPGA. The additional flash is > cheaper than a more complex CPLD. > You can find schmatic and VHDL details at: > http://www.jopdesign.com/index.html Have you looked at Atmel DATAFLASH, or SSTs SerialFlash devices ? These don't have the defects, and come large enough to configure most FPGAs, but in small packages. With a CPLD, you can also add run-length compression - so the price compare becomes : 'slightly better Serial FLASH', and smaller code area, against using ~50% of NAND, and the fixups - which only work on hard-defects. I have seen Cygnals tiny uC used for more complex compression for Serial FLASH loaders (Serial Bridge ?) - they are in the same price region as CPLD, but smaller so better suit serial-serial. -jg -jgArticle: 52951
Taka wrote: > Hi, > > How I can program an Altera EPC1 with a ByteBlaster cable? > I want to do an adapter to program it, but I can´t find any document > with the eprom program method. > I have not an external programmer. Can anybody help me? Download AN-116 and have a look at the pages. One or the other setup suits an EPC1 and your FPGA. Select JTAG chain mode and have the few pins connected to ByteblaserMV. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 52952
fba@free.fr (Frederic Bastenaire) writes: > On Xilinx site, they seem to have release version 5.2 of their outstanding > ISE tools, for the CD version. > Yet the ISE Webpack is still in v5.1 SP3. > Does anyone know whether it will be available for download in v5.2? I don't have any inside information, but generally Webpack gets updated a while after the full release.Article: 52953
Has anyone ran place and routes for a FPGA design under linux and then under windows on teh same machine? I was wondering just what kind of performance gain there is under one OS vs the other. Thanks in advance. JerryArticle: 52954
"Jim Granville" <jim.granville@designtools.co.nz> schrieb im Newsbeitrag news:3E5D0D31.6236@designtools.co.nz... > Martin Schoeberl wrote: > > > > > What we want to do is to use a nand-flash device to configure the fpga to > > > further reduce cost plus the nand flash can also be used as a mass storage > > > device. The idea is to use a 16 bit flash , 8 bits containing the > > > configuration code, 6 bits to do error correction (nand flash is not > > > garanteed error free). The error correction and the nandflash interface > > > could be handled by a cpld. > > > > An interesting idea. I thought about the same for an Altera FPGA (Cyclone) > > board. The problem is similar for X and A. But in a nand-flash you have > > complete bad blocks. This makes logic in the CPLD pretty complex. > > I decided to go the 'convential' way with a very small CPLD (MAX7064) and a > > 4Mbit flash for configuration and some application data and an optional > > nand-flash. Both flash are programmed via the FPGA. The additional flash is > > cheaper than a more complex CPLD. > > You can find schmatic and VHDL details at: > > http://www.jopdesign.com/index.html > > Have you looked at Atmel DATAFLASH, or SSTs SerialFlash devices ? > These don't have the defects, and come large enough to configure most > FPGAs, > but in small packages. I´ve seen zero defect nand flash from AMD. But only 8MB. So no real mass storage device. For configuration only (and some application data) I can use 'traditional' flash. > With a CPLD, you can also add run-length compression - so the price > compare becomes : 'slightly better Serial FLASH', and smaller code area, > against using ~50% of NAND, and the fixups - which only work on > hard-defects. The configuration data for new devices (like Cyclone) can be compressed. You get no benefit from inventing your own compression and it makes the CPLD more complex. MartinArticle: 52956
Hi guys, I am a graduate student at Texas A&M University, we are trying to use microblaze core for a project. And that is where the problems started. We installed xilinx mdk2.2. It crashed on the tutorials, so now we have no idea how to get it to work. We think it's the perl scripts that is doing this. We fidled around with cygwin environments to no avail - we are constantly getting different error messages. We even applied patch with equally erroneous results, Xilinx Software IDE will crash everytime the it starts (the problem occurs imediately after you created or load a project) There is nothing we can do with the MDK without causing one error or another, and we are just trying to compile a "hello world" program. In cygwin, this is the newest error message on the list: "C:\MicroBlaze\bin\gnu\cpp0.exe: *** Couldn't reserve space for cygwin heap (0x2420000) in child, cygheap, Win32 error 487" Do any of you wise sages out there have had any previous experiences with and solutions to these problems? Whom we should contact? What patch to apply...? Please help! Thanks. -Junyi Ling jling@cs.tamu.eduArticle: 52957
Gaga wrote: > > In cygwin, this is the newest error message on the list: > "C:\MicroBlaze\bin\gnu\cpp0.exe: *** Couldn't reserve space for cygwin heap > (0x2420000) in child, cygheap, Win32 error 487" Let me guess, you're running WinXP? The version of Cygwin that Xilinx used for MDK was released before Cygwin ran under WinXP. So, strictly speaking, it's a legacy Cygwin problem (fixed in newer versions of Cygwin). > Do any of you wise sages out there have had any previous experiences with > and solutions to these problems? Whom we should contact? What patch to > apply...? Please help! Thanks. You have several choices: (1) Lobby Xilinx for an upgrade to EDK, install it and patch up to SP3, then it will run under WinXp. Note however that the EDK requires ISE 5.1, which you may not have. (2) Hack it. Grab the latest version of Cygwin from www.cygwin.com, install into c:/cygwin or wherever, then use a binary editor to modify all of Xilinx's tools replacing references of "xygwin1.dll" to "cygwin1.dll". Finally, put the MDK tool directories (but not the /xygwin dir) into the Cygwin path, and off you go (doing all your work under Cygwin, not Xygwin). Ugly, but it works. I've actually got a combination of both - I'm using EDK with SP3, and have hacked it to work under regular Cygwin instead of the Xygwin shell. Makes life a lot easier. Rgds, JohnArticle: 52958
How is the FPGA 2003 conference? sincerely ------------- Kuan Zhou ECSE department On Wed, 26 Feb 2003, Nicholas C. Weaver wrote: > In article <b3iing$pht$1@news.uni-kl.de>, > Peter Tawdross <tawdross@rhrk.uni-kl.de> wrote: > >I need all the hardware details > > Its built of Kegs, Plastic Cups, Togas, and Cheerleader uniforms (on > guys). > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu > >Article: 52959
I have seen a lot of press on picoChip. They certainly seem to have some impressive claims (30 GigaMACs, easier to program, as fast as FPGA but with the programming model of DSP etc) but is it real ? How usable is it ? Is it realistic to get this performance ? Do 30giga-MACs mean anything ? Do these picoArray devices actually exist, or is it hype ? What are the strings ? Is this the fasdtest DSP ? (How does it compare to a new C6416 or TigerSHARC) ? Is it really as fasdt as an FPGA ?Article: 52960
Hi all, I have just bought an FPGA development board and it must be attached to = the PC's PCI slot. As it is attached inside the PC, so it's hard to tap = the jumper or FPGA pin and moreover it is not flexible. I am willing to = extend this PCI slot to outside of the PC, using cables and so on. Anybody has done this before ? any advice ? is it safe ? or .. is there any company who made this, so i can just buy :) Thanks. Basuki KerenArticle: 52961
you are crazy! :)
but i think u can try it .. use a cables , like an ATAPI ( IDE ) cable .
When the cable is about 50cm long ,the delay is no more than 1ns . on the
66Mhz PCI bus .
it's not matter.
--
sincerely yours
wufengzhi
------------------------------------------
email:wufz@magima.com.cn
------------------------------------------
"Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message
news:NixKKci3CHA.2508@exchnews1.main.ntu.edu.sg...
Hi all,
I have just bought an FPGA development board and it must be attached to the
PC's PCI slot. As it is attached inside the PC, so it's hard to tap the
jumper or FPGA pin and moreover it is not flexible. I am willing to extend
this PCI slot to outside of the PC, using cables and so on.
Anybody has done this before ? any advice ? is it safe ?
or .. is there any company who made this, so i can just buy :)
Thanks.
Basuki Keren
Article: 52962Martin Schoeberl wrote: > "Jo Kenens" <(no_spam)Jo(no_spam).ken(no_spam)ens@acunia.com> schrieb im > Newsbeitrag news:Xns932E9544CAADnospamJonospamkennos@195.129.110.155... > > On 26 feb 2003, you wrote in comp.arch.fpga: > > > > >> What we want to do is to use a nand-flash device to configure the > > >> fpga to further reduce cost plus the nand flash can also be used as a > > >> mass storage device. The idea is to use a 16 bit flash , 8 bits > > >> containing the configuration code, 6 bits to do error correction > > >> (nand flash is not garanteed error free). The error correction and > > >> the nandflash interface could be handled by a cpld. > > > > > > An interesting idea. I thought about the same for an Altera FPGA > > > (Cyclone) board. The problem is similar for X and A. But in a > > > nand-flash you have complete bad blocks. This makes logic in the CPLD > > > pretty complex. I decided to go the 'convential' way with a very small > > > CPLD (MAX7064) and a 4Mbit flash for configuration and some > > > application data and an optional nand-flash. Both flash are programmed > > > via the FPGA. The additional flash is cheaper than a more complex > > > CPLD. You can find schmatic and VHDL details at: > > > http://www.jopdesign.com/index.html > > > > > > Martin Schoeberl > > > > > > > > > > > > > > > > The idea was to move the complexity to the nand-flash programming > > software. What you then could do is use the last bytes (nand page = (256 > > + 8) x 16 bits) to build some kind of linked list. These last bytes would > > contain the address of the next 'valid' block. Then the cpld statemachine > > only has to update his address pointer after each block read. > > > > Jo Kenens > > So you assume that the first page is a good block (chances are high). Your > idea is good, perhaps we can work on it together. What complexity of PLD do > you expect? I expect you will need a 128 LC part. So it will get e a little > bit more expensive: MAX7064 bout $6, AMD Flash $4 but a MAX7128 is about $13 > (all prices on single pieces, but ok for comparison). But you can save a > little bit of board space. > > Martin It is like on HDs. The first blocks must be error free for the root block. The idea to do your own ECC is great to resolve the problem to do the ECC over the whole block. I have worked on this either and came up to the result that a XC9536XL is about $1 in the cheapest version. If the macro cells are not enough you can add a e.g. 74HC40103 for the counter and a 74HC374 for the next address register unless a XC9572XL is cheaper. If you get to the $2 range a small micro controller might do a cheaper job. ThomasArticle: 52963
Oh no, the stubs on a PCI bus must not be longer than 2 inch. You might have success if you make sure that it is in the last slot. Thus just increasing the length of the bus. AFAIK there are cards available that add a sub bus to the PCI bus. This should be the more reliable solution. Thomas fizz wrote: > you are crazy! :) > > but i think u can try it .. use a cables , like an ATAPI ( IDE ) cable . > When the cable is about 50cm long ,the delay is no more than 1ns . on the > 66Mhz PCI bus . > it's not matter. > > -- > sincerely yours > wufengzhi > ------------------------------------------ > email:wufz@magima.com.cn > ------------------------------------------ > > "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message > news:NixKKci3CHA.2508@exchnews1.main.ntu.edu.sg... > Hi all, > > I have just bought an FPGA development board and it must be attached to the > PC's PCI slot. As it is attached inside the PC, so it's hard to tap the > jumper or FPGA pin and moreover it is not flexible. I am willing to extend > this PCI slot to outside of the PC, using cables and so on. > > Anybody has done this before ? any advice ? is it safe ? > > or .. is there any company who made this, so i can just buy :) > > Thanks. > > Basuki KerenArticle: 52964
>I have just bought an FPGA development board and it must be attached to = >the PC's PCI slot. As it is attached inside the PC, so it's hard to tap = >the jumper or FPGA pin and moreover it is not flexible. I am willing to = >extend this PCI slot to outside of the PC, using cables and so on. I've never seen it done with cables. It is reasonably common to use an extender card to raise the card you want to work on up above the other PCI cards. That probably breaks the official specs/rules, but it normally works. Google should find several of them. The other thing you can do is take your PC apart and put the motherboard on your bench top so the case doesn't get in your way. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 52965
The documentation speaks of a low power mode (as opposed to a high speed mode) for these CPLDs, I can using webpac I can set the slew rate but can not find how to put the macrocells into low power mode? Anyone have any clues? Thanks RalphArticle: 52966
Hello Sir/Friends. I am designing a PCI target. I am presently reading specification and i didnot understand certain things which i have listed it. what is this UDF (user defined features)? what is cache wrap mode addressing? can anyone give me example what is single and multiple function PCI? please give me example? what is use cardbus line register in configuration header?Is this used only for PCMCIA cards How can you find if the burst transfer has crossed cacheline boundaries Any tips for the design of target PCI design I will be greatful to you if you can answer my question Thanking in advance praveenArticle: 52967
Ralph Mason <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote: : The documentation speaks of a low power mode (as opposed to a high speed : mode) for these CPLDs, I can using webpac I can set the slew rate but can : not find how to put the macrocells into low power mode? : Anyone have any clues? Implement design -> Properities -> Basic -> Macrocell Power Setting (Low seems to be default). Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52968
Hello, This is a newbie question. Apologies if it is already discussed. I can't seem to find it. I am a student and developing a PCB with virtex (2.5V) device. The device is to be programmed with XC1800 series serial EEPROM. The serial EEPROM is to be programmed through the JTAG interface. My question is what are the values to which VCC and VCCO should be tied in order for a proper operation? From data sheets, I understand, Virtex VCC=2.5 and VCC0=3.3V for bank 2 and 3 so that it can operate with the 3.3V serial EEPROM. And for XC1800, VCC=3.3V and VCCO=2.5V so that it can operate with virtex (am I right?). And I tie VREF of JTAG connector to 3.3V so that its output is 3.3V compatible with serial EEPROM. Now my question is, since VCCO is 2.5V for a serial EEPROM, the output of serial EEPROM is 2.5V compatible and will this be o.k with the JTAG circuitry in the parallel cable? And if I later use a virtex-E device, then this voltage will be 1.8V. Will the JTAG circuitry make the necessary adjustment to be compatible with 1.8V? Is it possible to get internal details (say at transistor diagram level) of this voltage conversion circuits? If I use a serial EEPROM to program the device, then what would I do with other modes of configuration pins? Say selectMAP or JTAG? Can I leave them unconnected? Is it safe? Thankyou for your time, JenifferArticle: 52969
praveen wrote: > Hello Sir/Friends. > > I am designing a PCI target. I am presently reading specification and > i didnot understand certain things which i have listed it. > what is this UDF (user defined features)? > > what is cache wrap mode addressing? can anyone give me example > Intel has a so called interleave burst. It wraps: 0-1-2-3, 1-0-3-2, 2-3-0-1 or 3-2-1-0 While linear burst is: 0-1-2-3, 1-2-3-0, 2-3-0-1 or 3-0-1-2 This mode must be the same between the controller and the RAM because only the first address will be supplied. > > what is single and multiple function PCI? please give me example? > You might have an IO section and a memory section. Graphic cards often use this. > > what is use cardbus line register in configuration header?Is this used > only for PCMCIA cards > Do not know. But sure will read the answer of somebody who knows this. > > How can you find if the burst transfer has crossed cacheline > boundaries > You need to have an address counter. You need this anyway cause the target can stop the burst at any time. If your address counter wraps at the appropiate bit position you are in the next line. > > Any tips for the design of target PCI design > Xilinx had allways useful aplication notes. You might also check at http://www.opencores.org > > I will be greatful to you if you can answer my question > Thanking in advance > praveenArticle: 52970
"Jim" <jim@nospam.com> wrote in message news:b3iqbn$49m$1@newsg1.svr.pol.co.uk... > Anyone know how/where to get hold of a Xilinx Coolrunner-II dev kit ($49) in > the UK please? The Xilinx web store is out of stock. The offical > distrbitutor for the UK (Insight Memec) only seems to sell it in the U.S. > > Many thanks. Its made by digilent www.digilentinc.com They sell the board but not the design kit. http://www.digilentinc.com/XC2/index.html Also have a nice spartan2e board Insight memec has worldwide offices. They are one of the local distributors here in Australia. Tried emailing xilinx sales ? AlexArticle: 52971
Yes, these devices have weak pull-ups on their IO, its been a while but I believe you can turn these pull-ups off once programmed, --- jakab Markus Meng <meng.engineering@bluewin.ch> wrote in message news:3e5b9ae9$1_4@corp.newsgroups.com... > Is this normal, that a blank CPLD is driving high the IO-Pin? > > markus > > -- > Mit freundlichen Grüssen > Markus Meng > > P.S. Achtung wir haben eine neue FAX-Nummer > ******************************************************************** > ** Meng Engineering Telefon 056 222 44 10 ** > ** Markus Meng Natel 079 230 93 86 ** > ** Bruggerstr. 21 Telefax 056 222 44 34 <-- NEU !! ** > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > ** Web www.meng-engineering.ch ** > ******************************************************************** > ** You cannot create experience. You must undergo it. Albert Camus** > > > > > > > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 52972
"Alex Gibson" <alxx@ihug.com.au> wrote in message news:b3l2f6$3os$1@lust.ihug.co.nz... > > "Jim" <jim@nospam.com> wrote in message > news:b3iqbn$49m$1@newsg1.svr.pol.co.uk... > > Anyone know how/where to get hold of a Xilinx Coolrunner-II dev kit ($49) > in > > the UK please? The Xilinx web store is out of stock. The offical > > distrbitutor for the UK (Insight Memec) only seems to sell it in the U.S. > > > > Many thanks. > > Its made by digilent www.digilentinc.com > They sell the board but not the design kit. > > http://www.digilentinc.com/XC2/index.html > Also have a nice spartan2e board > > Insight memec has worldwide offices. > They are one of the local distributors here in Australia. > > Tried emailing xilinx sales ? > > Alex > Many thanks for the info Alex - Digilent have some nice boards and good prices. JimArticle: 52973
Anyway, my PC has PCI to PCMCIA card. is there any PCMCIA to PCI ? = Especially for laptop users ? :) cheers, Basuki -----Original Message----- From: Thomas Rudloff [mailto:thomas_rudloff@gmx.net] Posted At: Thursday, February 27, 2003 4:31 PM Posted To: fpga Conversation: Extend PCI slot to outside PC Subject: Re: Extend PCI slot to outside PC Oh no, the stubs on a PCI bus must not be longer than 2 inch. You might have success if you make sure that it is in the last slot. = Thus just increasing the length of the bus. AFAIK there are cards available that add a sub bus to the PCI bus. This should be the more reliable solution. Thomas fizz wrote: > you are crazy! :) > > but i think u can try it .. use a cables , like an ATAPI ( IDE ) = cable . > When the cable is about 50cm long ,the delay is no more than 1ns . on = the > 66Mhz PCI bus . > it's not matter. > > -- > sincerely yours > wufengzhi > ------------------------------------------ > email:wufz@magima.com.cn > ------------------------------------------ > > "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message > news:NixKKci3CHA.2508@exchnews1.main.ntu.edu.sg... > Hi all, > > I have just bought an FPGA development board and it must be attached = to the > PC's PCI slot. As it is attached inside the PC, so it's hard to tap = the > jumper or FPGA pin and moreover it is not flexible. I am willing to = extend > this PCI slot to outside of the PC, using cables and so on. > > Anybody has done this before ? any advice ? is it safe ? > > or .. is there any company who made this, so i can just buy :) > > Thanks. > > Basuki KerenArticle: 52974
Hello Tim Thanks - exactly what I was looking for. Kresten "Tim Pagden" <tim@isoptic.com> skrev i en meddelelse news:3e58f570.166477471@usenet.f9.net.uk... > Hello, Kresten, > > Contact the guys at www.timingtool.com - I shall continue to persuade them that > this is a worthwhile avenue to explore; added weight to a request for VHDL > generation from timing diagrams is more than welcome! > > Producing state machine-based VHDL appropriate for synthesis from timing diagram > input is not an easy task, but the method has merit and is automatable. I have > used this approach for both testbench generation and RTL design for a few years. > > My own automation approach is based upon powerpoint (for timing diagram > definition) & VBA (for code generation) but requires more user intervention than > I'd like. If a >>high-level<< timing definition & code-generation tool (ie, > based upon TDML and VHDL) was commercially available, I'd buy it! > > Tim. > > On Sat, 22 Feb 2003 08:57:24 +0100, "Kresten Nørgaard" > <kresten_noergaard@ddf.dk> wrote: > > >Does anyone know of a FPGA design tool, that takes timing diagrams as an > >input, and produces VHDL (or something else) as an output? > > > >Kresten > > > > >
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z