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Another important difference: BlockRAM is not only much bigger, but also inherently two-ported, with two totally independent access mechanisms, even different aspect ratios (width x depth ). Distributed RAM can be given two ports, one write and one read, but loses 50% of its efficiency since it takes two LUTs for a 16-bit dual-port RAM. Peter Alfke, Xilinx Applications John_H wrote: > The two main differentiators I see (beyond the obvious width/depth issues): > > Distributed RAM is slower than BlockRAM in write speeds (limited by the > clock pulse width in the CLB SelectRAM) but the read is faster (limited by > Tbcko and routing in the BlockRAM). The routing on BlobkRAMs for Enable and > Write Enable signals can be a speed breaker, but the design-around for a > trash address location (thanks to Ray Andraka for pointing out the method) > can keep the speeds high. > > Distributed RAMs have combinatorial read while the BlockRAM reads are > registered. > > "longjin" <lchin1@excite.com> wrote in message > news:21cf9f42.0212022209.45362d05@posting.google.com... > > Does any know the difference between block and distributed RAM in terms > > of application and functionality. The question seems trivial but please > > enlighten just to verify my doubt. Thanks. > > > > There is no where to find the difference.Article: 50151
Workshop on Cryptographic Hardware and Embedded Systems 2003
(CHES 2003)
www.chesworkshop.org
Cologne, Germany
September 8 - 10, 2003
First Call for Papers
General Information
The focus of this workshop is on all aspects of cryptographic hardware
and security in embedded systems. The workshop will be a forum of new
results from the research community as well as from the industry. Of
special interest are contributions that describe new methods for
efficient hardware implementations and high-speed software for
embedded systems, e.g., smart cards, microprocessors, DSPs, etc. We
hope that the workshop will help to fill the gap between the
cryptography research community and the application areas of
cryptography. Consequently, we encourage submissions from academia,
industry, and other organizations. All submitted papers will be
reviewed.
This will be the fifth CHES workshop. CHES '99 and CHES 2000 were held
at WPI. CHES 2001 was held in Paris, and CHES 2002 in the San Francisco
Bay Area. The number of participants has grown to more than 200, with
attendees coming from industry, academia, and government organizations.
The topics of CHES 2002 include but are not limited to:
* Computer architectures for public-key and secret-key cryptosystems
* Efficient algorithms for embedded processors
* Reconfigurable computing in cryptography
* Cryptographic processors and co-processors
* Cryptography in wireless applications (mobile phone, LANs, etc.)
* Security in pay-TV systems
* Smart card attacks and architectures
* Tamper resistance on the chip and board level
* True and pseudo random number generators
* Special-purpose hardware for cryptanalysis
* Embedded security
* Device identification
Instructions for Authors
Authors are invited to submit original papers. The preferred submission form
is by electronic mail to submission@chesworkshop.org. The submissions
must be anonymous, with no author names, affiliations, acknowledgments, or
obvious references. Papers should be formatted according to the Springer
Lecture Notes in Computer Science instructions for authors at
"http://www.springer.de/comp/lncs/instruct/typeinst.pdf". They must not
exceed 12 pages (excluding the title page, bibliography and appendices)
nor 15 pages overall. Please submit the paper in Postscript or PDF, together
with an extra file containing the email and physical address of the authors,
and an indication of the corresponding author. We recommend that you
generate the PS or PDF file using LaTeX, however, MS Word is also
acceptable. All submissions will be refereed. Only original research
contributions will be considered. Submissions must not substantially duplicate
work that any of the authors have published elsewhere or have submitted in
parallel to any other conferences or workshops that have proceedings.
Important Dates
Submission Deadline: March 14th, 2003.
Acceptance Notification: May 14th, 2003.
Final Version due: June 13th, 2003.
Workshop: September 8th - 10th, 2003.
Mailing List
If you want to receive emails with subsequent Call for Papers and
registration information, please send a brief mail to
mailinglist@chesworkshop.org.
Program Committee
Ross Anderson, University of Cambridge, UK
Beni Arazi, Louisiana State University, USA
Jean-Sebastien Coron, Gemplus, France
Craig Gentry, DoCoMo Communications Laboratories, USA
Jim Goodman, Engim Canada Inc., Canada
Louis Goubin, SchlumbergerSema, France
Anwar Hasan, University of Waterloo, Canada
Kouichi Itoh, Fujtsu Laboratories Ltd, Japan
Marc Joye, Gemplus, France
Seungjoo Kim, Korea Information Security Agency, Korea
François Koeune, Universite catholique de Louvain, Belgium
Peter Kornerup, University of Southern Denmark, Odense, Denmark
Pil Joong Lee, Pohang University of Science and Technology, Korea
Katsuyuki Okeya, Hitachi, Japan
Bart Preneel, Katholieke Universiteit Leuven, Belgium
Vincent Rijmen, Cryptomathic, Belgium & Graz University of Technology, Austria
Kouichi Sakurai, Kyushu University, Japan
Erkay Savas, Sabanci University, Turkey
Werner Schindler, Bundesamt fur Sicherheit in der Informationstechnik, Germany
Jean-Pierre Seifert, Infineon technologies AG, Germany
Berk Sunar, Worcester Polytechnic Institute, USA
Tsuyoshi Takagi, Technische Universitat Darmstadt, Germany
Elena Trichina, University of Kuopio, Finland
Ingrid Verbauwhede, University of California, Los Angeles, USA
Sung-Ming Yen, National Central University, Taiwan
Organizational Committee
All correspondence and/or questions should be directed to any of
the Organizational Committee Members:
Colin Walter
(Program Chair)
Comodo Research Labs
10 Hey Street
Bradford BD7 1DQ, UK
Phone: +44 (0)1274 730505
Fax: +44 (0)1274 730909
Email: colin.walter@comodo.net
Cetin Kaya Koc
(Submission Management and Publication)
ECE Department
Oregon State University
Corvallis, Oregon 97331, USA
Phone: +1 541 737 4853
Fax: +1 541 737 8377
Email: Koc@ece.orst.edu
Christof Paar
(Local Organization and Publicity )
Electrical Eng. & Information Sciences Dept.
Ruhr-Universitaet Bochum
44780 Bochum, Germany
Phone: +49 234 32 23988
Fax: +49 234 32 14389
Email: cpaar@crypto.rub.de
Workshop Proceedings
The proceedings will be published in Springer-Verlag's Lecture Notes
in Computer Science (LNCS) series IN TIME FOR DISTRIBUTION AT THE
WORKSHOP. Notice that in order to be included in the proceedings,
the authors of an accepted paper must guarantee to present their
contribution at the workshop.
Article: 50152
Hello all
I'm having a hard time trying to get a correct RPM working with Xilinx ISE
5.1sp2 tools.
The following ASCII shows the design hierarchy.
I ---+--- H -------------------------+
J ---+ |
|
A ---+--- E ---+--- G ---+--- K ---+--- L
B ---| | |
C ---| | |
D ---+ | |
| |
A ---+--- F ---+ |
B ---| |
D ---+ |
|
A ------------------------+
At the bottom level, four different entities A, B, C, and D are used, based
on LUTs, DFEs, SRLs and so on. One of the simplest (D) uses a single LUT and
a single DFE.
If I synthesize up to entity K, everything is fine. The RPM (more than 2000
slices) appears
well organized in Floorplaner.
However, if I synthesize entity L, map produces a lot of warnings about
component D, like this one:
"INFO:Map:91 - dsr_f6muxor symbol "u0/u0/u8/u4/f" has an RLOC attribute
and will
be ignored since it is on a hierarchical block not directly recognized by
map. This may be caused by an error in the Xilinx library expansion for
the
symbol or by a third-party vendor incorrectly expanding the symbol."
The result, as shown by Floorplanner, is that K is only partially RPMed with
elements
of D spread around.
I can not imagine why all D components (dsr_f6muxor is the actual entity
name) are
not recognized by map(that is, D's belonging to E and F),
as it is correctly processed when the top-level entity is K.
And the problem affects D only, not A, B or C (all at the same level than
D).
Have any of you experienced a similar problem? Any clues?
I've searched Xilinx answer database but found nothing.
Regards
Francisco Rodriguez
====================================================
Francisco Rodriguez Ballester (prodrig@disca.upv.es)
Dept. DISCA, EUI - Univ. Politecnica de Valencia
c/Camino de Vera s/n, E-46022, VALENCIA (SPAIN)
tlf: +(34) 96 387 75 77 - fax: +(34) 96 387 75 79
====================================================
Article: 50153ISE Classic which was released recently supports most XC4000 family devices, including Spartan and Spartan-XL. It's free, but doesn't come with a synthesis tool. If you want a complete free package (A synthesis tool + a backend tool + a "crippled" HDL simulator) you will need to use ISE WebPACK, but ISE WebPACK doesn't support XC4000 family (It supports Spartan-II which is Virtex-based.). Kevin Brace (If you want to respond to what I wrote, I prefer if you will do so within the newsgroup.) "E. Napoli" wrote: > > I need a software such as Xilinx foundation that supports > xc4000xl fpga. > This should be free, even in a limited version. In this way I can distribute > the > software to my students and let them exercise at home. > The support for xc400xl is important since I own demo board including > xc4005xl fpga and spartan fpga. > > Can you suggest a software? Also a collection of packages (one > for synthesys, one for simulation, etc.) could work. > > Thank you for any suggestion. > > E. NapoliArticle: 50154
On Tue, 03 Dec 2002 15:13:13 -0600, Kevin Brace wrote:
>ISE Classic which was released recently supports most XC4000 family
>devices, including Spartan and Spartan-XL.
>It's free, but doesn't come with a synthesis tool.
Cool. Icarus Verilog will "synthesize",
for suitably loose definitions of the word.
I have used it successfully with an XCS10
and Xilinx Alliance.
- Larry
Article: 50155Hi, Look at Xilinx application note 151.It may be useful. Also check Parbit tool in google.The author of that tool may help you. If you know how to do it,please let me know.My boss asked me to do the same thing. sincerely ------------- On Sat, 30 Nov 2002, Philip Freidin wrote: > On 18 Nov 2002 03:26:49 -0800, mohamed.shiha@link.net (Mohamed Shiha) wrote: > > >On 18 Nov 2002 03:26:49 -0800, in comp.arch.fpga you wrote: > >Dear all, > > > >I would like to understand XC5204 bitstream format and be able to > >design a program that takes bitstream (*.bit) file as input and gives > >*.ncd file (place and route result file) or structural VHDL code file > >as output ... > > There are no tools to do this. While not impossible, it would be > extremely hard to do. i.e. multiple man-years effort. > > >I know that it has been made succesfuly by NeoCAd before and some fans > >are working around with Virtex family .... > > Even Neocad did not achieve this. They reverse engineered the forward > path (equiv to ncd-to-bits.) > > >Actually, I found a lot of useful information in the XC5200 datasheet > >from Xilinx .. but something that I don't understand is the following > >... > > > >"Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for > >the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 > >fill > >bits + 24 extended write bits > >= (34 x number of Rows) + 100" > > > >is the part that I don't understand ... > > I can see more than 4 splitter bits ... Actually, I see 8 bits and > >divided on two bytes .. something like that FC 7F so, C& are the > >splitter .. they are exactly at the mid of the frame .... sometimes , > >I see something like 04 also divided on two bytes ... But I never > >found the splitting bits constant ... their values depend onm the > >frame position and contents .... > > Some fields are encoded some aren't. 28+28+4+8+4+4+24 = 100 > > >Another remark ... How does Xilinx calculate the checksum bits ... I > >figured out that the checksum of two identical frames is not the same > >... Also, if i have changed something in the ncd file , the checksum > >values of so many frames are changed ... sometimes, i see the checksum > >changes before the frame of the data changes .. !!!!! > > The checksum is actually a running CRC, (not reset after each frame), > so a change early in the bitstream affects all subsequent CRC fields. > Look at patent 5,598,424 for more details than you could possibly want. > at http://patft.uspto.gov/netahtml/srchnum.htm > > >The last comic is , what are the 28 bits for the top and the 28 bits > >for the bottom .. ??? what does it mean ... ???? > > These are the I/O rows. 34 bits for CLB rows, 28 for I/O rows > > >Could anyone help with these things .. ??? > > > >With regards > >Mohamed Shiha > > I know you don't want to hear this, but, I recommend you spend your > time on something more useful than trying to reverse engineer the > bit stream of a discontinued FPGA product family. > > Philip Freidin > > > > Philip Freidin > Fliptronics > >Article: 50156
One simple question occurs to me. Are you connected to a powered PC parallel port with your system unpowered? -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "Jon Elson" <elson@pico-systems.com> wrote in message news:3DEBAB19.8050008@pico-systems.com... > Hello, all, > > I have developed some products using Xilinx FPGAs and CPLDs. I have had > some problems with certain customers blowing out these devices, and > suspected > they may be using really bad ESD procedures, and just kind of ignored > the problem. > > Then, I was testing a board on the bench with an XCS30-3TQ144C Spartan 5V > FPGA. I powered it up, tested it, all looked good. I turned it off, > turned it back > on, and it wouldn't configure. A quick check indicated the power supply > was overloaded. > I took out the regulator chip and hooked it to a bench supply, and found > it would draw > about 1.8 A at only 3 V. My bench supply was at current limit. I > removed several > other parts, and determined the Spartan was drawing all the current. > Now, from reading > other info on ESD, this may have been a latent fault that chose that > moment to develop. > > My experience is that I can count on one hand all the other chips I've > blown out. But, now, I > seem to be getting a very large pile of Xilinx parts that have died. > > Anyway, this device is mostly opto-isolated, but has a connector to a > PC's parallel > port. I think that is the path that needs to be protected. Does anyone > have any > suggestions on what I should put into the next revision? Has anyone > fought this > sort of problem before? I plan on putting one of those diode clamp > packs in to > clamp all lines between gnd and +5 V, and see if that prevents any more > of these > problems. Has anyone tried this approach, or are TVS devices a better plan? > > Thanks in advance for all comments! > > Jon >Article: 50157
Jim Granville wrote: >You could check the pin characteristics, on the dead pile, to >see if any show leakage/damage signs. > > Yes, on a few of them I actually found a pin that was anomalous. I really didn't try to diagnose past the chip package very hard. >Sounds like the PC Parallel port is directly connected to the FPGA ? > > Yes, that's right. >Diode clamps would seem best, or even a 1284 buffer device, eg >fairchild. >Series R also helps reduce the currents. > >Damage modes could be ESD, which should be pin-specific, or triggered >latch-up, which does not need ESD voltages to occur. >Latch up needs just enough injection current from < 0V, or > 5V, to >get the lateral thyristor above the trigger threshold, and then it >crowbars >the Vcc until power is removed. > > I suspect there have been a few latch-ups. I had some experience with 95144s a few years ago, and while I had them "de-program" themselves on occasion, and start drawing a lot of current and getting hot, they generally could be erased and reprogrammed, and work fine. >You can test latch-up currents yourself - when we tried this on CPLDs, >we found +ve latch up needed high voltages (10-14V) to get enough >injection, >and at that level it's a debate on current/voltage trigger. >-ve latchup has a steeper diode, and less minus voltage injection >was needed but it was still in the hundreds of mA. > We also tested the thyristor holding current, thinking that a >smart powersupply could self cure this problem - but found they >are actually quite good thyristors, with 5-10mA region holding currents! > > Maybe the series resistor is a good idea, but on bidir and output pins, I can't put a lot of R in there. 1284 buffer chips would save money on blown expensive FPGAs, but shouldn't be able to withstand much more than the FPGA, unless Xilinx's protection networks are known to be weak. Would a bipolar chip's protection network be better (with real diodes) than a pure-CMOS FET network that has resistive clamping? I've been working with a custom CMOS chip on another project, and was surprised to see I could drive the input pins 2.2 V beyond the supply rails. It has a pair of FETs in the pad protection. This 2.2 V peak was seen as the ringing on about 4" of circuit board trace, with an XC9572 driving it. Anyway, I'm sure I'll be putting a diode to each rail protector on it for sure. Thanks for your comments! JonArticle: 50159
Hi All, Thanks a lot for your kind enlightenment.Article: 50160
Hi, muthu,
I have provided the source code named "register or latch (source code)".
Thank you!
regards,
siriuswmx
_nano@yahoo.co.in (Muthu) wrote in message news:<28c66cd3.0212030549.5de1edbe@posting.google.com>...
> wangmanxi@yahoo.com (siriuswmx) wrote in message news:<4528663b.0212021655.4951876@posting.google.com>...
> > hi. everybody,
> > I wrote a program in VHDL to realize the following function : if
> > en=1 ,x is latched into reg_x, y is latched into reg_y after "not" has
> > been excuted in alu.
> > if en=0 , x adds y in alu.
> > I used xilinx2.1 to simulate it but failed , and i found that x was
> > latched into reg_x just when en=0, but y into reg_y when en=1.
> > Someone have told me that there must be something wrong with the
> > difference with register and latch , but he knows little about it.
> > Can you help me ?
> > Thank you!
>
> could you u provide the piece of code to check?
>
> Rgds,
> Muthu
Article: 50161
Thank you ,Markus Sponsel,
> Don't use a synthesis tool for simulation, use a simulator instead
> (e.g. ModelsimXE, it's part of the free webpack).
>
Yes, i used ActiveHDl to simulate it yesterday, and I got the right results.
you are right, tools can cause trouble sometimes.
Best regards,
siriuswmx
Article: 50162
Larry Doolittle wrote:
>
>
> Cool. Icarus Verilog will "synthesize",
> for suitably loose definitions of the word.
> I have used it successfully with an XCS10
> and Xilinx Alliance.
>
> - Larry
I thought Icarus Verilog was only a simulator.
How good is the synthesis tool, and what devices are supported?
Kevin Brace (If you want to respond to what I wrote, I prefer if you
will do so within the newsgroup.)
Article: 50163Library IEEE; use IEEE.std_logic_1164.all; use work.alu_package.all; entity x_y is port(x,y:in std_logic_Vector(7 downto 0); z:out std_logic_vector(7 downto 0); en:in std_logic); end x_y; end x_y; architecture alg of x_y is signal a_in,b_in,c_out,reg_x,reg_y:std_logic_vector(7 downto 0); signal ci_in:std_logic_vector(1 downto 0); begin z<=c_out; u1:alu8 port map(a_in,b_in,c_out,ci_in); step1:process(en,x,c_out) begin if en='1' then reg_x<=x; reg_y<=c_out; end if; end process; step2:process(en,y) begin if en='1' then a_in<=y; ci_in<="01"; b_in<="00000000"; else b_in<=reg_x; b_in<=reg_x; a_in<=reg_y; ci_in<="10"; end if; end process; end alg;Article: 50164
Step 1 = a level sensitive storage element = latch Step 2 = 2:1 Multiplexer siriuswmx wrote: > My program : > > Library IEEE; > use IEEE.std_logic_1164.all; > use work.alu_package.all; > entity x_y is > port(x,y:in std_logic_Vector(7 downto 0); > z:out std_logic_vector(7 downto 0); > en:in std_logic); > end x_y; > > > end x_y; > architecture alg of x_y is > signal a_in,b_in,c_out,reg_x,reg_y:std_logic_vector(7 downto 0); > signal ci_in:std_logic_vector(1 downto 0); > begin > z<=c_out; > u1:alu8 port map(a_in,b_in,c_out,ci_in); > step1:process(en,x,c_out) > begin > if en='1' then > reg_x<=x; > reg_y<=c_out; > end if; > end process; > > step2:process(en,y) > begin > if en='1' then > a_in<=y; > ci_in<="01"; > b_in<="00000000"; > else > b_in<=reg_x; > > > b_in<=reg_x; > a_in<=reg_y; > ci_in<="10"; > end if; > end process; > end alg; > > Thanks ! :) -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 50165
There are so many aspects to serial interfaces that you need to be more specific about your application requirements and what you mean when you say 'serial bus'. For example... Serial - a single 'signal' with clocking information embedded in the data requiring clock and data recovery in the receiver, or, seperate clock and data 'signals' - control infromation embedded in the data stream, or seperate control 'signals' - half-duplex or full-duplex Bus - multiple devices connected to a single 'signal' (or set of 'signals'), or a point-to-point connection between two devices (switched point-to-point connections for multiple devices?) IO signaling technology - single ended signaling (i.e. TTL or CMOS levels), or differential signaling (PECL, LVDS, etc.) Protocol - home grown wire protocol vs. industry standard, or commercially available protocol What capabilities do you need? - data throughput? - latency? - address/data transfers (random or sequential), or streaming data pipe? - write only, write/read, read only? - sideband signaling (errors, interrupts, etc.) - distance requirements - common power system between connected nodes or seperately powered chassis requiring dc-isolation ... and many more... Identify as many requirements as you can and people might be able to offer you more guidence. TC ++++ "Mark Lew" <markylew@earthlink.net> wrote in message news:ee7aba6.-1@WebX.sUN8CHnE... I am looking for suggestions on a low speed serial bus (~30 Mbs) while minimizing IO. I will probably be interfacing between an FPGA and a couple of CPLDs. Any help would be much appreciated. MarkArticle: 50166
Jon Elson wrote: > <snip> > > Maybe the series resistor is a good idea, but on bidir and output pins, > I can't put a lot of > R in there. 1284 buffer chips would save money on blown expensive > FPGAs, but shouldn't > be able to withstand much more than the FPGA, unless Xilinx's protection > networks are > known to be weak. Fairchilds 74LVXZ161284 quotes 4KV ESD, which will be above any FPGA pin, but they do not spec a latchup value, so you may have to test for that for both devices. Even if the latch up trigger inject-level is the same, the 1284 buffer can have a separate much lower limited supply, as it does NOT have to support the FPGA startup, or run currents. Thus in cases where latchup does occur, it would be non-fatal. - jgArticle: 50167
This is a multi-part message in MIME format.
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Thanks a lot!
--
sincerely yours
wufengzhi
------------------------------------------
email:wufz@magima.com.cn
------------------------------------------
Article: 50168Rick Filipkiewicz <rick@algor.co.uk> wrote: > A note on #2 above: What you need to look for is `MEDDELAY' in the constraints guide. I've just tried that, but I get the same effect as with NODELAY. The constraints guide says that MEDDELAY is for Spartan IIE only. > Also - If you've not yet committed your choice of device you might consider using a Virtex-2 since > their DLLs (called DCMs = DigitalClockManagers for V-2) have the ability to phase shift the output > clock at a resolution of TClk/256. That's exactly what we've done. Their controlled-impedance io's come in handy for us as well :-) Thank you for your reply, AndyArticle: 50169
okay are you targetting a xilinx spartan device for this purpose? the following discussion is valid only in that case. what you can do is forcibly constrain the buffers that you want leonardo to "infer" through a constraints file instead of letting it infer some wrong buffers. that is a foolproof way of ensuring that it does not do any supposedly smart assumptions of buffers for you. Sometimes leospec indavertently assigns BUFG to that net which goes to your DLL and then xilinx PAR cribs that i/p should always go to an IBUFG. if you are facing this problem in assigning IBUFG at i/p of a CLKDLL,you can manually instantiate an IBUFG component and give it a location constraing GCLKBUF <num> and if you want give a GCLKPAD constraint to the pin/net that is driving the input of this GCLKBUF. so at the end of the day when it comes to ports, always prefer manual buffer isnertion. regards, Nachiket Kapre Design Engineer. Paxonet Communications. quadarel@yahoo.it (Rosaria) wrote in message news:<80f08e5a.0212030319.4faf2c62@posting.google.com>... > Hello, > does anyone knows if is it possible configure leonardo in order to NOT > instance clock pad and clock buffer? > I have checked the box exclude gates yet. > > Thank you > > RosariaArticle: 50170
I wholeheartedly agree with Mikhail on the suggestion of using an XC18v series of ISP PROMs which allow you infinite in-system reprogrammability thru a simple JTAG "Parallel Cable 3" interface (and a daisy chain). 18v can save you a lot of headache and the return on the initial up-front high cost of the 18v compared to a 17v cannot be measured in terms of money alone. Okay, and about Atmel, you are absolutely right regarding the compatibility of that part with the Xilinx part. We did consider Atmel substitue parts in our deisgn but eventually , paradoxically due to unaviability of Atmel parts we went in with a Xilinx 18v series. regards, Nachiket Kapre Design Engineer. Paxonet Communications. "MM" <misoma@NOrogersSPPAMM.com> wrote in message news:<TY5H9.1467$yq.39508@news>... > You are not clear on what stage you are at in your project and I don't know > what the availability situation is, neither do I know anything about the > Atmel parts, but you may want to consider using reprogrammable parts such as > XC18Vxxx instead of the one time programmable XC17xxx's. Also, depending on > where you are in your development you might want to consider using a > different method of loading your FPGA., e.g. from a parallel PROM. There are > multiple appnotes on the Xilinx website in regards to this issue. > > /Mikhail > > > > "Cristian" <cbustos@yx.cl> wrote in message > news:69583e13.0212030616.af701d0@posting.google.com... > > Hi, > > > > I'm currently developing a project with a xc2s300 Xilinx FPGA. Now I > > need to purchase the corresponding PROM. It's supposed to be the > > xc17S300a. This IC is hard to find in the market. Then I heart about > > an Atmel replacement. The AT17LV002. Is this true? Is this a valid > > replacement, are there any differences? Looking at the pines and the > > signals over time there are some differences but quite small, though. > > But even for this PROM, were can I purchase it? > > > > Finally, are there more/better replacement then these? Were can I find > > them. Perhaps it's possible to get a sample. > > > > Can anybody help me? > > > > Thanks in advanceArticle: 50171
Okay, I recollect doing my programming on XP and ISE Webpack. iMPACT does work okay with ISE. I thought reinstalling ISE would have been a better option that reinstalling the OS. And if u r gettnig bscan errors check the cable that you are using. And what do u mean that impact works on win2k?...are you suggesting that you have tried configuring it thru win2k and the configuration worked ok?..or that just impact executed? regards, Nachiket. "Kim Noer" <kn@nospam.dk> wrote in message news:<asi5t0$rba8u$1@ID-151686.news.dfncis.de>... > Hi there.. > > I'm experiencing quite a few problems with Windows XP and Impact. I did a > total reinstall of my OS, and then it seemed to be working (using a JTAG > cable for downloading firmware to a XC9500). But yesterday it suddenly > refused to work, some failures regarding boundering scan or something like > that. Since then I haven't been able to get it to work again. Any ideas on > how to correct this particular problem? > > PS. Impact works in Windows 2000. So it seems to be a problem specific to > Windows XP.Article: 50172
okay, i dont think you may need to use a FIFO for transporting control signals unless your application specifically requires it. You can do with simple synchronisers. You can refer to Synopsys documentation concernign multi-clock domains written by Clifford Cummings that can help you in your design. It is a veritable bible of such designs. regards, Nachiket Kapre Design Engineer Paxonet Communications. "louis" <n2684172@ms17.hinet.net> wrote in message news:<ash6nd$bgk@netnews.hinet.net>... > That's why I asked this question. > Since I am not familiar with the characteristic of DLL, > I'd like to know what kind of mechanism I have to design to > overcome the clock difference of DLL... > Should it be asynchronous FIFO, or double buffer or > different clock edge sampling, or something... > > Of course, I knew the asynchronous FIFO is safest, but the > size is also largest. > > > "Nachiket Kapre" <nachikap@yahoo.com> > > why dont you try synchroniser across the two domains since that will > > make your deisgn safer and independent of jitter which as ray > > mentioned is suscptibel to rpocess vaiations and other physical > > factors like temeperature.. > > > > Nachiket Kapre > > Design Engineer > > Paxonet Communications > > > > > > "louis" <n2684172@ms17.hinet.net> wrote in message > news:<arcgqh$3og@netnews.hinet.net>... > > > There's a external clock input (20MHz) on my system, and I multiply > > > it to 2X (40MHz) by DLL as the working clock. > > > However, I have to exchange data in several > > > modules between these two clock domains. I don't know if it safe to sample data > > > on both positive edges of these two clocks? > > > Will the clock jitter cause the metastability? Or I have to generate data > > > on positive edge and retrieve data on negative edge instead? > > > The target chip is SpartanIIE. Any comment and suggestion will be very > > > appreciated. > > > > > > louisArticle: 50173
Hi,
When I did this, I used vga.pdf from the page below on XESS's
website. Hardware is basically a few resistors. Piece of cake! The
worst part was entering the character generator ROM for the format I
wanted. I used 7*5 sized chars (stolen from and old Epsom LCD
controller manual) in a 9*6 space. This let me do crude graphics by
defining 64 chars to represent the combinations of six 3*3 blocks
being on and off in the 9*6 space, just like teletext. To do 'proper'
graphics you'd need loads of memory, so your plan of driving an old
VGA controller would work fine.
HTH, Symsx.
http://www.xess.com/ho03000.html#Tutorials
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3DECC967.C375C09C@yahoo.com>...
> Thomas Buerner wrote:
> >
> > Hi
> >
> > is it possible to use an old isa vga card connected to an FPGA
> > for video output? what must be sent over the bus to get it working?
> >
> > or is there another - easier - way to get a monitor connected to
> > my FPGA.
> > all hints welcome
> >
> > Thomas
>
> Yes, you can interface to a ISA video card if you have a means of
> programming the registers and drawing your images in memory. I assume
> you are connected to a MCU or similar.
>
> Another way is to build the controller into your FPGA. If you only need
> text display then you can use a very simple controller indeed and can
> likely use the on chip memory. There are several types here.
>
> http://www.opencores.com/projects/
>
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
Article: 50174Hello Everyone, anyone knows how to send refresh cycle to the SDRAM if the Full-Page mode is used and if the time needed to transfere all the data in the page is 3 times bigger than the time needed to send one refresh cycle. I think that i need to use burst terminate command, but how can i continue transfering the data from the cutting point after terminating it to send the refresh? Thanks
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