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you can use the built-in multipliers in a Virtex chip. it's generally adviced not to use loops if you want to synthesize a module. Since A is a fixed number, you had better manually scrap them with adders and this is much more efficient. -- Xu Qijun ---------------------------------------------------- Oki Techno Centre (Singapore) Pte Ltd 20 Science Park Road #02-06/10, Teletech Park, Singapore Science Park II, 117674 Singapore. Tel: +65-6779-1621 Fax: +65-6779-2382 DID: +65-6770-7081 E-mail: qijun677@oki.com URL: www.okitechno.com ---------------------------------------------------- Friends may come and go, but enemies accumulate. "Peng Cong" <pc_dragon@sohu.com> wrote in message news:ap2hok$jlp$1@debian.bentium.com... > Please help > > I write a simple verilog programe to calculate a 4 * 4 matrix > multiplication. C = A * B, A is pre-defined. > I write a task calc_line to calculate one line, like follows: > > module matrix_multi > ... > for(j = 0; j < 16; j = i + 4) > calc_line(in[j], in[j + 1], in[j + 2], in[j + 3], out[j], out[j + > 1], out[j + 2], out[j + 3]); > ... > > task calc_line; > input a, b, c, d; > output dout0, dout1, dout2, dout3; > .... > //multiply here > .... > endtask > > endmodule > > After the synthesis/implementation, it seems that 4 physic calc_line > "blocks"(maybe not accurate, I don't know the term) > are prodused to run, it use too much resource, I only need one block and > re-use it in the loop. > > Hopes you can understand what I say, I don't know how to describe it in > special terms. > > How can I do it? > > I use Active HDL 5.1 , Xilinx ISE 4.1, FPGA is Xilinx VIRTEX2 > > Thanks for any advance > >Article: 48626
Don't forget to check ebay, a great place to get parts for a hobby type project where you know you won't need more than a couple and you want to save some bux. Regards minosss@yahoo.com (Javier Garcia) wrote in message news:<a92a77a9.0210211239.77b73234@posting.google.com>... > Someone know where to buy fpga (Xilinx,Altera) in quantities of 1 to 5 > Thanks in advanceArticle: 48627
I downloaded it just the other day - no problem. RobArticle: 48628
On Tue, 22 Oct 2002 00:41:31 GMT, Ken McElvain <ken@synplicity.com> wrote: > > >Allan Herriman wrote: > >> On Sat, 19 Oct 2002 16:15:01 GMT, Ken McElvain <ken@synplicity.com> >> wrote: >> >> >>>Thanks! Actually there are several of the hotline folks that read the >>>newsgroup, but we limit the number of posters. >>> >> >> Ah, good. I'd like to know what you are doing about the SRL16 >> inference rule change between 7.0 and 7.1. We have a number of >> designs here that break in 7.1 and 7.2 because Synplify Pro is >> inappropriately changing FF into SRL16E. >> >> Problem 1 (fixed in 7.2 beta) Some FF with 350MHz clock get converted >> to SRL16E. SRL16E don't work at 350MHz (in Virtex2). >> >> Problem 2 (still outstanding) Some FF with async reset get converted >> to SRL16E. SRL16E don't have an async reset input, so this is a >> functional change. >> (It's that old problem of Synplify trying to be too clever about the >> meaning of GSR when the startup block is present. If an FPGA has an >> external reset input (connected to the startup block) then it is *not* >> correct to assume that GSR is only active during configuration.) > > >Sorry, this was a bug in the 7.2 beta1 . I understand that it has >already been fixed in the current 7.2 beta2. We usually go through >2 rounds of beta before production release. Different bug. This one is present in 7.1.0, 7.1.1, 7.2.0 beta 1 and 7.2.0 beta 2. >> >> Problem 3 (still outstanding) Some FF that were in IOBs get converted >> to SRL16E. This breaks the I/O timing on the part. > > >We would love a small test case (or any test case). Our test cases >appear to work properly. We are not supposed to be sucking in flip >flops connected to I/Os. Looks like it's going to be a large test case, as this one only seems to happen on a full design. Oddly, on one 64 bit bus, only about half the flip flops are affected in this way. I can not spot anything in the source code that would cause individual bits in that bus to be treated differently. I have been contacted by Synplicity support about sending a test case. We are contacting the legal people here, as we're a bit nervous about giving away the full source for a chip. Regards, Allan.Article: 48629
Hello Mauro,
I have just checked in ISE 4.2i S.P.3 and it is still available. I don't
know about webpack 4.2i to be honest but being and old family as it is it
should be available in webpack for free. Just in case you don't know the
PARTGEN command, is very useful, you type 'partgen -i' and get a list of the
supported devices in your ISE (I guess is applicable to Webpack).
This is what you get:
4005e SPEEDS: -1 -2 -3 -4
PC84
PG156
PQ100
PQ160
PQ208
TQ144
CB164
I have just checked the Xilinx Answer Database and in this link (Record
8599)
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
1&getPagePath=8599
they mention that Webpack 4.1 only supports
Virtex (300E and smaller)
Virtex-II (250 and smaller)
Spartan-II
CoolRunner XPLA3
CoolRunner-II
XC9500
XC9500XL
XC9500XV
Bad luck
Ulises Hernandez
www.ecs-tech.com
ulisesh@ecs-vhdl.com
"Mauro Pintus" <triac11@yahoo.com> wrote in message
news:lw1t9.29916$dj7.189247@tornado.fastwebnet.it...
> Hi, I need to configure an old FPGA XC4005E, but in the WebPack is not
> present (i've tried 4.2 and 3.3 version).
> Any one know witch is the program that i have to use and where i can find
> it?
>
> Thanks
> Mauro
>
>
>
>
>
>
>
>
>
> --
> Mauro Pintus
> www.geocities.com/triac11
> --
>
>
>
Article: 48630Calvin Klein wrote: > > I have read the CompactFlash specs already but find not so useful. Precisely. Read up on PCMCIA and you'll understand a lot more about CF. The signals are (more or less) identical. > By the way, what's the link between IDE and ATA? I am pretty confused > that they are quoted inter-changeably. Don't quote me on this, but I think they are interchangeable - ATA is the new name for IDE, or something like that. Rgds, JohnArticle: 48631
Calvin Klein wrote: > > This is a general question. > > Does PCMCIA contain a functionality of auto-boot like a CD_ROM? I am > thinking about > whether I can copy the Win-XP OS into an IBM MicroDrive, and get rid of the > CDROM on > my notebooks. I think that would depend on your BIOS. If it can be convinced to look at a PCMCIA "disk" device, and boot from that, then there should be no problem. But I'm only guessing, so don't tawke my word for it! We're straying far from the charter of comp.arch.fpga here, maybe followup to a more appropriate group? Regards, JohnArticle: 48632
>Does this newsgroup allow commercial advertisements?
My opinion...
This newsgroup is not a dumping ground for press releases.
I like announcements, but only if...
They are on topic.
If you aren't sure it's on topic, then read the group for
long enough to figure it out.
They are short/crisp
I should be able to figure out what you are saying (and if I
want to read the rest of it) without scrolling. 10 or 20 lines.
Give a URL for the long story.
They are not too common/frequent
This is a bit fuzzy. New product announcements are good because
they are new. I'd get annoyed if every package and speed and size
of a family were "announced" here, one at a time.
Announcing yet another deadline-extended-to-submit-papers-for-XXXXX
turns me off. I'd actually prefer to see comments from a regular
poster telling me something about the conference rather than the
typical conference announcement.
I'd get annoyed if, say, opencores posted an "announcement" for
every one line bug fix. A summary of changes every month or two
would probably be interesting.
The poster participates in the group,
or at least sticks long enough to answer questions or see the flames.
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
Article: 48633>For the SRL16's, We generally try to put the last clock of delay into a FF >because of the relatively long clock->Q of the SRL16. I can't have that >flip-flop getting sucked into the SRL16, even if such modification is controlled >by the clock period. We generally turn the clock to 0 in synplify to keep it >from duplicating stuff that is RLOC'd in aggressive designs. That works fine as >long as the logic between registers is reasonably simple (eg., single level of >logic), but it also means that I don't want ff's I intend to follow an SRL16 >getting absorbed into the SRL16. I also don't want the SRL16 inference >automatically putting a flip-flop at the end if the SRL16 address is dynamic. >For static SRL16 address, automatic inference of a flip-flop after *EACH* SRL16, >even when there are several SRL16's in a chain is a nice feature. I believe 7.03 >does that just for the last SRL16 in a chain. Is it reasonable to expect a compiler to be able to do-the-right-thing in all cases like this? Or in most of them? Or is this a good example to show that we need some way to annote/supplement the source code with hints? Or should we just make library packages that instantiate what we really want whenever we need it? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48634
"Mancini Stéphane" <stephane.mancini@inpg.fr> wrote in message news:ap0u15$q6o$1@new-news.grenet.fr... > Hi all, > As anybody tried to use Nios dev. tools and > quartus on a Linux workstation ? > What are the cons and pros ? > Are the tools easy to use ? Are there special things to take care off ? > Is the use of the RedHat 7.1 mandatory or is it possible to > use those EDA soft with other linux distributions such as > Mandrake (9.0 for instance) or Suse or whatever ? > Thanks very much for your comments. > Stephane > > > We've got various EDA tools installed on Redhat 6.2. I tried to install Quartus, but it actually checks during installation for a 2.4 kernel. So I would guess that as long as you've got a distribution with a 2.4 kernel with a late enough version, it should work. Alan P.S. We've stuck to Redhat 6.2 because a number of EDA tools specified it at first. Now there are more which specify 7.1/7.2 so we may have to bite the bullet and upgrade at some point :-( -- Alan Fitch [HDL Consultant] DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 48635
Rene Tschaggelar wrote: > Hav a look at the datasheet at sandisk(google). > > Rene > > Karl wrote: >> Hi, >> >> I want to learn how to access a compact flash card with an FPGA. I have >> written .wav >> files from my PC into the card and now I read it out byte by byte. >> >> Can anyone give some websites which will teach how to handle the >> Windows-related aspect >> in the CompactFlash? have a look at the SystemACE controller stuff xilinx i am not sure what its microcontroller interface is able to but i now it can much more than reconfiguration of an fpga via jtag fhfArticle: 48636
I sure wish someone had a free (or cheap) 6809 core. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "MikeJ" <pacman@fpgaarcade.com> wrote in message news:1035241191.21317.0@iapetus.uk.clara.net... > www.free-ip.com still has a 6502 core to download. > Not tried it however. > > b.t.w I have verified the latest version of the t80 (z80) core at > www.opencores.org to be absolutely cycle accurate - at least for all the > code I have run on it so far - may have missed some though ;-) > > MikeJ > > "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message > news:ap1o65$2kff$1@msunews.cl.msu.edu... > > I would guess available as in "for license" as in for commercial payment. > > Does this newsgroup allow commercial advertisements? So... No it is not > > you, I read the posting and the newsgroup the same way as you did. BTW, a > > couple of years ago Green Mountain Computing offered a synthesizable > 68HC11 > > core that was downloadable for free. I used this core for a class project > > for a grad couse in HW-SW codesign. I suppose that posting could have > been > > considered as advertisement for Green Mountain but at least the core was > > free (even if it targeted their software for simulation, etc.) > > Just my opinion, > > Theron Hicks > > > > > > "Speedy Zero Two" <david@manorsway.NOSPAMPLEASE.freeserve.co.uk> wrote in > > message news:ap1ml8$vim$1@news7.svr.pol.co.uk... > > > how do you mean available? > > > no sign of anyway to download....or is it me? > > > > > > Dave > > > > > > "Rob Finch" <robfinch@sympatico.ca> wrote in message > > > news:rtJs9.1762$Kf.256319@news20.bellglobal.com... > > > > Hi, > > > > > > > > A 6502 compatible core is available at > > > > http://www.birdcomputer.ca/Cores/bc_6502.html > > > > Small and Fast. > > > > > > > > Rob > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >Article: 48637
Hi, the LPM simulation models only support the .hex format. In Quartus you can open the .mif file and save it (File/Save As) as a .hex file. You can use the .mif syntax for entry and easily convert it to a .hex file for functional simulation in ModelSim. Regards Wolfgang http://www.elca.de "Sudip Saha" <sudip.saha@philips.com> schrieb im Newsbeitrag news:ee79cf6.-1@WebX.sUN8CHnE... > Hi, > I have created through quartus .mif files for a lpm_rom(altera devices). > While simulating it in modelsim I am getting error as "Not a proper intel hex file". > Any clue why is not taking .mif file? > When I gave .hex file as initialization file, the simulation is correct. > But I want to create a hex file of 10kb. So it is very difficult to write all the data in hex file editor of quartus one by one.. > Any body can give me solution how to create a .hex file with my own hex data ?Article: 48638
Jan Gray wrote:
> Ralph Mason wrote
>
> > 1. As a learning process I have copped his adder, he says that it turns
> > into 17 LUT's although mine ends up at 52 - Is there some optimizations I
> am
> > missing here? are there any pragmas you can use in these situations to say
> > what you want? Can you get right down to the actual LUT level and connect
> > them up yourself? Using the free Xilinx tools can you actually see the way
> > it has connected the actual LUTs?
>
> First, congratulations on going to the trouble of actually looking under the
> hood and *inspecting* what came out of your tools. That is a very good
> practice.
>
> Welcome to "pushing on a rope". (fpgacpu.org/usenet/rope_pushing.html: "You
> know exactly what you want -- a particular optimal, hand-mapped, hand-placed
> layout for your datapath -- but the tools get in the way, and you spend
> hours trying to discover an incantation that persuades the tools to emit the
> desired result.")
>
Another example of `rope pushing', possibly simpler. I have this abstract
structure for an LUT RAM based FIFO read address. ra = the registered address
incremented on every read:
fifo_ra = (fifo_rd_a | fifo_rd_b) ? ra + 1 : ra;
but what I wanted to do was absorb the `or' into the LSB LUT of the adder.
Clearly I could have taken Ray's approach of instantiating the structure I
wanted but, lacking a generate capability (& my inbuilt resistance to VHDL), it
would be difficult to parametrise [in fact Synplify now handles Verilog's
"arrays of instances" step towards a full generate which would do the trick].
First problem: Synplify doesn't infer a carry chain adder for widths < 6 (for
width = 4 I can understand this and I think somewhere deep in the inference
engine there's a dumb coding error where xxx < 5 became xxx <= 5).
Fix = do a module with a min width of 6 *and* put a syn_hier = hard on it.
2nd problem: Getting the absorption to work. Following a suggestion of, IIRC,
John_H, recoding to the equivalent, but less readable, rope_push works [for Syn
v7.0.2 at least] :
fifo_ra[n:0] = {ra[N:1], (fifo_rd_a | fifo_rd_b)} + ra[0];
The moral being that it takes a fair amount of effort to both go fast and keep
the code "pure RTL".
Just a thought: This, and the OP, makes a potentially interesting test case for
the XST optimiser/mapper. Who knows, it might handle the original selector based
RTL better than Syn ?
Article: 48639The Xilinx guidelines recommend one HF cap per supply pin (VCCINT, VCCO, VCCAUX), yet the power pins are mostly in the centre of the chip. Assuming one via per pin, how have people managed to place decouplers close to these pins on the underside of the board to minimise trace length? Is it adequate to place the decouplers around the periphery of the chip, or is the only solution to use buried / blind vias with caps underneath the chip? Having viewed the recommended standard routing diagrams in the Virtex II databook it shows there is no unused area in the centre of the chip as there are in some of the BG packages for Virtex E. Has anyone got any words of wisdom? 'Bert RossArticle: 48640
Peng Cong wrote: > Please help > > I write a simple verilog programe to calculate a 4 * 4 matrix > multiplication. C = A * B, A is pre-defined. > I write a task calc_line to calculate one line, like follows: > > module matrix_multi > ... > for(j = 0; j < 16; j = i + 4) > calc_line(in[j], in[j + 1], in[j + 2], in[j + 3], out[j], out[j + > 1], out[j + 2], out[j + 3]); > ... > > task calc_line; > input a, b, c, d; > output dout0, dout1, dout2, dout3; > .... > //multiply here > .... > endtask > > endmodule > > After the synthesis/implementation, it seems that 4 physic calc_line > "blocks"(maybe not accurate, I don't know the term) > are prodused to run, it use too much resource, I only need one block and > re-use it in the loop. > > Hopes you can understand what I say, I don't know how to describe it in > special terms. > > How can I do it? > > I use Active HDL 5.1 , Xilinx ISE 4.1, FPGA is Xilinx VIRTEX2 > > Thanks for any advance Peng, Basically the synthesiser is doing exactly what you've asked it to do. To see this you have to realise that the "for" loop does not imply any time sequence, all 4 iterations happen every time its enclosing always block gets executed. If, for example, the block is clocked, then the description says that on each time tick all 4 vectors are produced. To reduce the resource consumption you'll have to explicitly pipeline *and* do the hard work in creating a good multiply-add structure. Secondly you should be aware that, for Verilog-1995 at least, tasks are not re-entrant. I think this has been modified in V2001 but who knows if the synth tools support this.Article: 48641
Cheers guys! "Michael Nicklas" <michaeln@nospam.slayer.com> wrote in message news:aoopch$de9$1$8300dec7@news.demon.co.uk... > Hi > > I need to implement a CRC generator polynomial using VHDL. I am using > Xilinx Foundation student edition 4.2i software and don't really mind which > device it is targeted at - the main objective is familiarity with design and > simulation tools. > > Is it simply a case of describing a series of registers and XOR's to fit my > polynomial? > > -- > Cheers! > > Mike > >Article: 48642
I have been trying to simulate a design using the test bench waveform, but I didn't have modelsim installed. So I have downloaded and installed it. However, after installing modelsim, selecting the .tbw file only gives me the option of viewing the file (before I installed modelsim I had options to run the simulation) Does anyone have any idea what is going on here and how I get those options back? Thanks RalphArticle: 48643
Rick Filipkiewicz <rick@algor.co.uk> wrote: >> Problem 3 (still outstanding) Some FF that were in IOBs get converted >> to SRL16E. This breaks the I/O timing on the part. > > Does `syn_useiobffs' stop it inferring SRL16Es ? If not this is a killer > bug and mucho thanks for the warning as I was just about to make the move > from 7.0.2 -> 7.2. It doesn't happen to all designs, or even all the pins on a bus. I wrote the code Allan described as #1. This bug appeared in 7.10, and is fixed in 7.11 and the 7.20 betas. The rest of the chip seems to be synthed correctly. The #2/#3 bug is still present in 7.11 and 7.20 beta 2. Cheers Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 48644
Hal Murray <hmurray@suespammers.org> wrote: > Is it reasonable to expect a compiler to be able to do-the-right-thing > in all cases like this? Or in most of them? > > Or is this a good example to show that we need some > way to annote/supplement the source code with hints? Not when the result is functionally incorrect. Flip-flops coded with asynchronous resets cannot be converted to SRL16s - SRL16s do not have asynchronous resets. I can live with syn_preserve, syn_replicate etc. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 48645
I do the third one in many cases. I do get occassionally rebuffed for doing so much
instantiation, but then it does get the job done. For the others, 'the right thing'
is not necessarily the same for everyone and every case. The problem is that what the
tools do is not consistent across tool versions, much less across vendors, so you get
into the pushing on a rope syndrome quite easily.
Hal Murray wrote:
> >For the SRL16's, We generally try to put the last clock of delay into a FF
> >because of the relatively long clock->Q of the SRL16. I can't have that
> >flip-flop getting sucked into the SRL16, even if such modification is controlled
> >by the clock period. We generally turn the clock to 0 in synplify to keep it
> >from duplicating stuff that is RLOC'd in aggressive designs. That works fine as
> >long as the logic between registers is reasonably simple (eg., single level of
> >logic), but it also means that I don't want ff's I intend to follow an SRL16
> >getting absorbed into the SRL16. I also don't want the SRL16 inference
> >automatically putting a flip-flop at the end if the SRL16 address is dynamic.
> >For static SRL16 address, automatic inference of a flip-flop after *EACH* SRL16,
> >even when there are several SRL16's in a chain is a nice feature. I believe 7.03
> >does that just for the last SRL16 in a chain.
>
> Is it reasonable to expect a compiler to be able to do-the-right-thing
> in all cases like this? Or in most of them?
>
> Or is this a good example to show that we need some
> way to annote/supplement the source code with hints?
>
> Or should we just make library packages that instantiate
> what we really want whenever we need it?
>
> --
> The suespammers.org mail server is located in California. So are all my
> other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's. I hate spam.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48646
I'm not adverse to the extra work to get it to do the right thing with RTL. Been
burned several times though by new versions doing something different, so the extra
work turns into a continuing maintenance program as well. XST does seem to do
pretty well on optimizing carry chain structures.
Rick Filipkiewicz wrote:
> Jan Gray wrote:
> The moral being that it takes a fair amount of effort to both go fast and keep
> the code "pure RTL".
>
> Just a thought: This, and the OP, makes a potentially interesting test case for
> the XST optimiser/mapper. Who knows, it might handle the original selector based
> RTL better than Syn ?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48647Are there any other companies other than Xilinx that produce FPGA's to match there latest Virtex II designs. I require 400 MHz DDR (800 Mbps) line side, with a 200MHz core containing at least 400 Kbits of RAM. It is for a communications protocol so features similar to Xilinx's DCM's that can centre a clock to a data eye (i.e. Phase shifting) and perform lane deskew. I have nothing against Xilinx but just interested to see if anyone else offered this kind of specification. Google search for High Performance FPGA's didn't give me any useful results. Also, interested to hear anyones recommendations or concerns about the claims that Xilinx make about their FPGAs, as an ASIC designer they seem a bit too good!? Regards, MattArticle: 48648
Altera is really the only competition in this end. Have you looked at
their Stratix?
Which claims specifically are you questioning? Xilinx competes very
favorably for run of the mill ASIC designs. ASICs hold an edge at the
very high speed and high density corners, but then most ASIC starts aren't
in those corners. FPGAs compete rather poorly in the low power corner as
well. To be fair, in order to compete, the designer MUST code to the FPGA
features and structure. That typically means some instantiation, and much
deeper pipelining than you may be used to doing. Plain vanilla RTL code
implemented in the FPGA is likely to yield very dissappointing results.
M Pedley wrote:
> Are there any other companies other than Xilinx that produce FPGA's to
> match there latest Virtex II designs. I require 400 MHz DDR (800
> Mbps) line side, with a 200MHz core containing at least 400 Kbits of
> RAM. It is for a communications protocol so features similar to
> Xilinx's DCM's that can centre a clock to a data eye (i.e. Phase
> shifting) and perform lane deskew.
>
> I have nothing against Xilinx but just interested to see if anyone
> else offered this kind of specification. Google search for High
> Performance FPGA's didn't give me any useful results.
>
> Also, interested to hear anyones recommendations or concerns about the
> claims that Xilinx make about their FPGAs, as an ASIC designer they
> seem a bit too good!?
>
> Regards,
>
> Matt
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48649
"Sudip Saha" <sudip.saha@philips.com> wrote in message news:<ee79cf6.-1@WebX.sUN8CHnE>...
> Hi,
> I have created through quartus .mif files for a lpm_rom(altera devices).
> While simulating it in modelsim I am getting error as "Not a proper intel hex file".
> Any clue why is not taking .mif file?
> When I gave .hex file as initialization file, the simulation is correct.
> But I want to create a hex file of 10kb. So it is very difficult to write all the data in hex file editor of quartus one by one..
> Any body can give me solution how to create a .hex file with my own hex data ?
I have used a MIF-like format for preloading memory blocks for my MSc
Thesis.
To convert input data (e.g. chars for pixel 8-bit values) to .mif
format is no really hard in C.
There exists some example code you can use. Since this ain't mine, but
avail by the author, i paste it here: (you could modify it to get
things going):
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
int main(int argc, char *argv[])
{
int depth,width;
char outstr[256];
char wkstr[256];
unsigned address;
unsigned digit;
unsigned count,i;
FILE *fptr;
if(argc != 3)
{
printf("Usage: s19_2_mif depth inputfile.s19\n");
return 0;
}
else
{
sscanf(argv[1],"%d",&depth);
sscanf(argv[2],"%s",outstr);
fptr = fopen( outstr,"r" );
}
printf("DEPTH = %d;\n",depth);
printf("WIDTH = 8;\n");
printf("ADDRESS_RADIX = HEX; \nDATA_RADIX = HEX; \n");
printf("CONTENT\n");
printf("\tBEGIN\n");
do
{
fgets(wkstr,255,fptr);
if(wkstr ==NULL) break;
// printf("%s",wkstr);
sscanf(&wkstr[2],"%2x",&count);
sscanf(&wkstr[4],"%4x",&address);
for (i=0; i< count-3; i++)
{
sscanf(&wkstr[i*2+8],"%2x",&digit);
printf("\t\t %x : %.2x; \n",(i+address)%depth,digit);
}
}
while (!feof(fptr));
printf("\tEND ;\n");
}
have fun!!!
Uncle Noah
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