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Hi again > Everything seems ok to me. Anyway this is an example I know that works. > "ngdbuild -p xcv100e-7-fg256 -uc ../lca_build/top.ucf -dd .. > ../lca_build/top.edf top.ngd" > Not much differences to be honest, I don't use the NGC command and the -nt > timestamp is a default option so you don't need to specify it. I have tried many combinations :( > What tool version are you using? I work on ISE 4.1.03i under Windows 2000 - maybe that's the point? Thanks for Reply. JerzyArticle: 48776
Ken McElvain schrieb: > You can use a physical synthesis tool like Amplify and generally > get enough improvement to save a speed grade. This is true for > RTL code. If you are instantiating and placing everything then > you may be done. Well I constrained (placement) all important elements and timing analysis showed that the path from the last FF to the IOB was the critical one. I could not find a shorter one by hand, so I think I'm done. Regards, PatrickArticle: 48777
Nicholas C. Weaver wrote: > The Xilinx Answer Record states that the RocketI/Os on the V2Pro have > been tested and verified to work with 1000BASE-SX (fiber Gb ethernet, > multimode fiber). > > The media for 1000BASE-T however is a 4 pair differential signaling, > rather than the serial send/receive of the fiber standards. > > Are there low cost solutions for driving 1000BASE-T ethernet using the > RocketI/Os? > I would say that you need a GigE Copper PHY (Broadcom among others makes those) and a magnetic part (Pulse makes those) before connecting to an RJ45 header. The only detail that I am not sure of is what would be the connection between the FPGA and the PHY? I think it is GMII (i.e: parallel interface) so the RocketI/O won't help you there ... BTW, is it an option in your case to go to Optical GigE? You just need the tranceiver (60$) and you're done vs multiple parts on the board and a higher cost I think. Those are my 2 cents ... DaliArticle: 48778
In state machines you also need to be sure there are no incomplete assignments - every branch of an if/case must assign the variable. Glitches also occur if the state machine is run faster than the logic can cope with - check you have a timing constraint when synthesising and that you meet it. Good Luck PhilArticle: 48779
I need to write an interface between Gbit MAC (ISP3 n ports) and an internal (fpga) design . Im looking for guidelines/designs that handle this issue. Regards Ron skalarv@hotmail.comArticle: 48780
>The only detail that I am not sure of is what would be the connection >between the FPGA and the PHY? I think it is GMII (i.e: parallel >interface) so the RocketI/O won't help you there ... Yes, the Broadcom PHY chips I've looked at use GMII. 125 MHz clock, 8 bits of data, and a few control bits. Repeat for the other direction. And a couple junk IO bits if you want to use the side door control path. It gets more complicated if you want 10/100 too. > BTW, is it an option in your case to go to Optical GigE? You just need > the tranceiver (60$) and you're done vs multiple parts on the board and > a higher cost I think. You have to do the 8B/10B encoding and decoding. Do transceiver parts include the clock recovery PLL now? If not, that's another external chip. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48781
I need to write an interface between Gbit MAC (ISP3 n ports) and an internal (fpga) design . Im looking for guidelines/designs that handle this issue. Regards Ron skalarv@hotmail.comArticle: 48782
Just as a matter of interest, How are DLLs and PLLs implemented internally in the hardware? Are they "proper" PLLs with VCOs, dividers, etc? How are DLLs implemented? Thanks in advanceArticle: 48783
Hi, I have a requirement to interface to a CMOS device which will be using 1.35V signalling levels 1. Can i power the VCCO rail in the virtexII to 1.35? The data sheet specs a min of 1.2V. 2. If i can, what will be the input and ouput threshold values. Will they be similar to LVCMOS15 with VCCO of 1.35V)? 3. If i power VCCO as 1.5V, and i specify LVCMOS15 as the standard, what is the VOHMAX value. The data sheet only specifies a VOH min value. Maybe its obvious and its 1.5V! 4. in the UCF, should i specify LVCOMOS15 as the standard even if the VCCO is at a lower level. Thanks Derek --Article: 48784
I know there was an issue with w2k S.P.3 but I can't tell. I use NT with 4.1.03i and it works fine with scripts, and w2k S.P. 2 with 3.1i and it works also fine. Good luck, -- Ulises Hernandez "Jerzy" <furia1024@wp.pl> wrote in message news:dc3feced.0210232340.561b1e1b@posting.google.com... > Hi again > > > Everything seems ok to me. Anyway this is an example I know that works. > > "ngdbuild -p xcv100e-7-fg256 -uc ../lca_build/top.ucf -dd .. > > ../lca_build/top.edf top.ngd" > > Not much differences to be honest, I don't use the NGC command and the -nt > > timestamp is a default option so you don't need to specify it. > > I have tried many combinations :( > > > What tool version are you using? > > I work on ISE 4.1.03i under Windows 2000 - maybe that's the point? > > Thanks for Reply. > > Jerzy >Article: 48785
Hi,
I'm using the LogicLock design flow to incrementally place and route
a design on a APEX1500KE device. Several people work on the project
and I
need to automate the compilation flow, so everything is done with tcl
scripts.
I followed the instructions from Altera but I still have some
problemes. The structure of the design is something like this :
top +-- A
| +--- AA
| +--- AB
| +---ABA
| +---ABB
+-- B
| +--- BA
| +--- BB
| +---BBA
| +---BBB
Here is what I do :
. I generate a edf file for each module (AA, BA, ABA, ABB, BBA, BBB)
with Leonardo.
. I run quartus for each submodule (AA, BA, ABA, ABB, BBA, BBB) to
generate the esf and vqm files. Each submodule contains one or
more
LogicLock regions.
. to generate the esf and vqm file of bloc AB I use the vqm and esf
files
generated for ABA and ABB plus an additional edf file. To enforce
the
hierarchie I use the LL_PARENT assignment. I change this
assignment
after importing the lower level .esf files, otherwise it doesn't
work.
...
. for the final place and route I use the files A.vqm A.esf B.vqm
B.esf and
top.edf. The LogicLock regions defined are visible and have the
correct
size at the top level. The position is chosen automaticly by
quartus
for the moment.
For the lower levels everything is fine but I get some problems at the
top
level. I get a lot of messages like the one :
Warning: Ignored back-annotated location assignment on node
bmicro:bmicro_inst|i2c:i2c_enabled_i2c_inst|i2c_intermediaire:i2c_intermediaire_inst|i2c_reste:reste|modgen_eq_445_ix46~I_I
assigned to LogicLock region
i2c_i2c:i2c_enabled_i2c_inst_bmicro:bmicro_inst because location is
outside region boundaries
How could this happen ? At the lower levels all the cells where inside
the
logiclock region and I didn't get the message. For the moment I didn't
try
to move manually the regions.
Quartus also complains about carry chains it couldn't place inside a
low level
logiclock region. But I didn't get this message when it fitted this
region or
the next higher level.
My next problem is that I need to chose the position of the logiclock
regions
because of timing issues. I can do this using the quartus gui but I
want to
move them from a tcl script. When I only change the LL_ORIGIN
assignment
the LL_LOCATION assignments aren't updated. Does anyone know which
command
I need to run ?
thanks for you help
stephen
Article: 48786Nick, The MGTs (serdes) in V2 Pro do all of the clock and data recovery on the incoming differential pair, and provide the proper transmit serial on its output differential pair. Physically at a minimum you need a transformer for isolation for a four wire interface, and an optical to electrical converter for a fiber interface. There are plenty of other details on the DC balnce of the code, what the bits mean, etc. that have to also be taken into account. But yes, they work. And yes, they are inside the Virtex II Pro. And yes, they do both clock and data recovery on RX and also do TX as they have the 20X multiplier PLLs to do that job. They were designed for the serial backplane business, not the 1G Ethernet business. There is also the Serial ATA business that is similar (but not really). There are many projects by folks to see where we fit without any issues (square pegs in square holes), and then we have those applications that folks are interested in working a bit harder to do (square pegs in round holes). As these other applications are made to work reliably, you will see them announced. Since we are using the Connexant serdes IP in Virtex II Pro, we are already compatible with their ICs, as well as many other serdes designed for backplane and on pcb high speed serial links. Again, that is the focus of the product. http://www.xilinx.com/esp/optical/xlnx_net/oif.htm http://www.xilinx.com/esp/optical/xlnx_net/pci_express.htm http://www.xilinx.com/esp/optical/xlnx_net/xaui.htm http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Aurora http://www.xilinx.com/esp/optical/xlnx_net/fibre_chan.htm http://www.xilinx.com/esp/optical/xlnx_net/inf_band.htm etc etc etc All built in, no extra ICs required. Austin "Nicholas C. Weaver" wrote: > The Xilinx Answer Record states that the RocketI/Os on the V2Pro have > been tested and verified to work with 1000BASE-SX (fiber Gb ethernet, > multimode fiber). > > The media for 1000BASE-T however is a 4 pair differential signaling, > rather than the serial send/receive of the fiber standards. > > Are there low cost solutions for driving 1000BASE-T ethernet using the > RocketI/Os? > > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48787
From the data sheet it looks like you have 1 set of differential transmit (2 wires) and 1 set of differential receive (2 wires) lines going into each Rocket I/O. Which has SERDES, Clock management (including clock and data recovery), 8b/10b and CRC encoding blocks. It looks pretty complete. Is the 1000BASE-T 8 lines (4 differential pairs). I'm not quite sure what 4 pair differential means. Steve "Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:ap40j8$gm4$1@agate.berkeley.edu... > The Xilinx Answer Record states that the RocketI/Os on the V2Pro have > been tested and verified to work with 1000BASE-SX (fiber Gb ethernet, > multimode fiber). > > The media for 1000BASE-T however is a 4 pair differential signaling, > rather than the serial send/receive of the fiber standards. > > Are there low cost solutions for driving 1000BASE-T ethernet using the > RocketI/Os? > > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48788
Hi John, There is no official RTOS for MicroBlaze yet. I know that there exists a iuTRON implementation in Japan. But when customer has asked for RTOS, we ask them why. And in most of the cases they want just want some kernel functionality or network services. So what we have added in the just released EDK many of these services in our own libraries. We have network services, kernel services, filesystem services and they are free. We even ship the source code for these libraries. The remaining requests for a commercial RTOS has not been strong enough yet to justify the cost for paying a RTOS vendor for the porting of their RTOS to MicroBlaze. That may however change in the future and would really like to know if there are customer who needs a RTOS for MicroBlaze. Göran John Williams wrote: > Hi folks, > > I am doing some research into the Microblaze architecture - Xilinx doco > states that there is no operating system support - it seems they (for > now) expect microblaze to run a monolithic application. > > I've looked around but not found anything substantial - does anybody > know about any operating system ports to microblaze, either free or > otherwise? I found a press release from Xilinx and Wind River talking > about vxWorks, but no further mention of it on either's website. I'd > love to hear about any budding linux / uClinux / other ports, or indeed > any microblaze developers' mailing lists and resources etc. > > thanks, > > JohnArticle: 48789
Anyone with low power experience out there? Among other things we are building a CompactFlash I/O card. We don't have control over the power source and no room for milliFarad power assist caps. I would be worried about causing a brownout in a PocketPC device upon card insertion. We only use low end families (Spartan not Virtex) for cost and would like to use SpartanIIE because we have a need for block RAM. I jumped ship to ACEX (bye bye distributed RAM). Geoff "Geoffrey Furman" <geoff_furman@iisvr.com> wrote in message news:urdv6qkh82hlfb@corp.supernews.com... > Does anyone have real world experience with this. The spec is outrageous > for the SpartanII / IIE /Virtex families. > I could get no detailed information from Xilinx which helped. > I build low power systems with very tight packaging constraints and don't > believe that it is possible to power up one of these devices. > > Please comment on your successes and failures. This issue needs to be > brought out in the open > >Article: 48790
Philips started I2C bus and publish the spec as well as other app notes "Soul in Seoul" <Far@East.Design> wrote in message news:3db74e36@news.starhub.net.sg... > Hi, > > I went to yahoo for "Lecture I2C Bus" and it returned me a bunch of french > websites. > Has anyone seen a good decent lecture notes on I2C bus? > > Thanks. > > >Article: 48791
One of the places I was hoping to use them was for SMPTE-292 HDTV serial
transmission, which is 1.485 Gbps. Unfortunately it looks like the jitter spec
for the PLL doesn't meet the SMPTE292 specification, so while it can probably be
used, it is not compliant.
Austin Lesea wrote:
> Nick,
>
> The MGTs (serdes) in V2 Pro do all of the clock and data recovery on the
> incoming differential pair, and provide the proper transmit serial on its
> output differential pair.
>
> Physically at a minimum you need a transformer for isolation for a four wire
> interface, and an optical to electrical converter for a fiber interface.
>
> There are plenty of other details on the DC balnce of the code, what the bits
> mean, etc. that have to also be taken into account.
>
> But yes, they work. And yes, they are inside the Virtex II Pro. And yes,
> they do both clock and data recovery on RX and also do TX as they have the 20X
> multiplier PLLs to do that job.
>
> They were designed for the serial backplane business, not the 1G Ethernet
> business. There is also the Serial ATA business that is similar (but not
> really). There are many projects by folks to see where we fit without any
> issues (square pegs in square holes), and then we have those applications that
> folks are interested in working a bit harder to do (square pegs in round
> holes).
>
> As these other applications are made to work reliably, you will see them
> announced.
>
> Since we are using the Connexant serdes IP in Virtex II Pro, we are already
> compatible with their ICs, as well as many other serdes designed for backplane
> and on pcb high speed serial links.
>
> Again, that is the focus of the product.
>
> http://www.xilinx.com/esp/optical/xlnx_net/oif.htm
> http://www.xilinx.com/esp/optical/xlnx_net/pci_express.htm
> http://www.xilinx.com/esp/optical/xlnx_net/xaui.htm
> http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Aurora
> http://www.xilinx.com/esp/optical/xlnx_net/fibre_chan.htm
> http://www.xilinx.com/esp/optical/xlnx_net/inf_band.htm
> etc etc etc
>
> All built in, no extra ICs required.
>
> Austin
>
> "Nicholas C. Weaver" wrote:
>
> > The Xilinx Answer Record states that the RocketI/Os on the V2Pro have
> > been tested and verified to work with 1000BASE-SX (fiber Gb ethernet,
> > multimode fiber).
> >
> > The media for 1000BASE-T however is a 4 pair differential signaling,
> > rather than the serial send/receive of the fiber standards.
> >
> > Are there low cost solutions for driving 1000BASE-T ethernet using the
> > RocketI/Os?
> >
> > --
> > Nicholas C. Weaver nweaver@cs.berkeley.edu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48792Steve, For even higher rates, they use 4 sets of 2.5 Gb/s lines. They them turn on and off the TX (ping pong) to get 10 Gb/s in one direction at a time. Austin Steve Casselman wrote: > From the data sheet it looks like you have 1 set of differential transmit (2 > wires) and 1 set of differential receive (2 wires) lines going into each > Rocket I/O. Which has SERDES, Clock management (including clock and data > recovery), 8b/10b and CRC encoding blocks. It looks pretty complete. Is the > 1000BASE-T 8 lines (4 differential pairs). I'm not quite sure what 4 pair > differential means. > > Steve > > "Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message > news:ap40j8$gm4$1@agate.berkeley.edu... > > The Xilinx Answer Record states that the RocketI/Os on the V2Pro have > > been tested and verified to work with 1000BASE-SX (fiber Gb ethernet, > > multimode fiber). > > > > The media for 1000BASE-T however is a 4 pair differential signaling, > > rather than the serial send/receive of the fiber standards. > > > > Are there low cost solutions for driving 1000BASE-T ethernet using the > > RocketI/Os? > > > > -- > > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48793
Hi, The design on my website does use a 74hc244. The schematics as well as the gerber files are online. Regards, Scott L Baker "scd" <scd@nospam.com> wrote in message news:74Jt9.1439$6F4.134577@newsread2.prod.itd.earthlink.net... > I have posted gerbers on my website if anyone wants > to roll their own. > > I have used these files to build a working Altera FPGA programmer cable. > However... the files on this page are offered with absolutely no warantee > or support. Use them at your own risk. > > http://home.teleport.com/~scd/free.htm > "Silvio Lauckner" <silvio.lauckner@inf-technik.tu-ilmenau.de> wrote: > You don't need the 74xxx244 bus driver as long as the cable is > short enough.Article: 48794
Bob wrote: <snipped>> > By the way, I believe that the latest software supports differential DCI, so > LVDS inputs will be terminated right at the pads (if DCI is enabled). > > Bob > > Yes, for inputs only, I think. Saw this in answer record 15633 regarding 5.1 SP1. A bit of a power hog, though : "Note that internal LVDS termination comes with a power-cost of 62.5mW per termination." Versus about a milliwatt for an external resistor. Let's see, 32 inputs * 62.5 mW = 2 watts. Ouch. regards, TomArticle: 48795
THanks. Background: This is what I want to build AFTER I file my dissertation, (unless someone else has built it for me), so still several months off: A V2Pro-7 module, with ~2 Gb ethernet (ideally BASE-T copper, but I can live with BASE-?X fiber and get a couple of media converters) interfaces out the front, and 6 gigabit+ backplane interconnects out the back (ideally BASE-?X fiber ethernet, for easier testing and fewer electrical hastles when interconnecting). 1 DDR SO-DIMM 1 Compact Flash slot, with SystemACE. Which I want to start playing with intrusion detection, anomoly detection, and other Gb rate tasks. But it is still all months away. In article <3DB811AD.5C574A01@xilinx.com>, Austin Lesea <austin.lesea@xilinx.com> wrote: >But yes, they work. And yes, they are inside the Virtex II Pro. And yes, >they do both clock and data recovery on RX and also do TX as they have the 20X >multiplier PLLs to do that job. > >They were designed for the serial backplane business, not the 1G Ethernet >business. There is also the Serial ATA business that is similar (but not >really). There are many projects by folks to see where we fit without any >issues (square pegs in square holes), and then we have those applications that >folks are interested in working a bit harder to do (square pegs in round >holes). Thanks. Thats what I was starting to figure: 1000BASE-?X is fiber, true serial, send and receive, so its simply a matter of using a transceiver. Xilinx tested. Ony difference between flavors being fiber (multimode vs singlemode), frequency, and range. 1000BASE-T is funkier, with 4 pair signaling and other funky stuff, so it would require substantial external ICs. At which point, just go with external MAC/PHY chips. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48796
Hello, I am in the process of a new design. The design is probably about 50% complete. All of the interfaces are defined to and from the chip but the internal fpga logic is not completely defined. Now I need to start the PCB design effort, and lock down some pins. I ran my design in its current state through the Xilinx tool set and had it choose the pins for me. Then I went back and glanced over the .ucf file and a few things stood out as less than optimal (at least seems that way to me). There are many buses throughout the design and I would have expected them to be grouped in a similar area of the chip, but they were not. The tools did manage to put all of my input clocks on global clock buffers and even a good portion of output clocks to other devices. I guess the question I am asking is what are some good rules of thumb (I know that these rules can't always be applied) for choosing pin configurations before a design is complete? Should I let the tools choose most of my pins and modify that list or should I group buses together with timing constraints, etc? I glanced through comp.arch.fpga for similar topics, but most of them were old and I was wondering if anyone had any new thoughts on the subject. This is my first major design that I am doing on my own (Xilinx Virtex 2 xc2v1000fg456, vhdl based, fpga express, xilinx 4.2i tools) and I want to make sure I do all I can to optimize my design. Thanks, Mike Schreiber Hardware Engineer Mschreiber75@yahoo.comArticle: 48797
Ray, Jitter generated, or jitter tolerated? If this is jitter tolerated, it might meet the spec (we just haven't tested to it). Austin Ray Andraka wrote: > One of the places I was hoping to use them was for SMPTE-292 HDTV serial > transmission, which is 1.485 Gbps. Unfortunately it looks like the jitter spec > for the PLL doesn't meet the SMPTE292 specification, so while it can probably be > used, it is not compliant. > > Austin Lesea wrote: > > > Nick, > > > > The MGTs (serdes) in V2 Pro do all of the clock and data recovery on the > > incoming differential pair, and provide the proper transmit serial on its > > output differential pair. > > > > Physically at a minimum you need a transformer for isolation for a four wire > > interface, and an optical to electrical converter for a fiber interface. > > > > There are plenty of other details on the DC balnce of the code, what the bits > > mean, etc. that have to also be taken into account. > > > > But yes, they work. And yes, they are inside the Virtex II Pro. And yes, > > they do both clock and data recovery on RX and also do TX as they have the 20X > > multiplier PLLs to do that job. > > > > They were designed for the serial backplane business, not the 1G Ethernet > > business. There is also the Serial ATA business that is similar (but not > > really). There are many projects by folks to see where we fit without any > > issues (square pegs in square holes), and then we have those applications that > > folks are interested in working a bit harder to do (square pegs in round > > holes). > > > > As these other applications are made to work reliably, you will see them > > announced. > > > > Since we are using the Connexant serdes IP in Virtex II Pro, we are already > > compatible with their ICs, as well as many other serdes designed for backplane > > and on pcb high speed serial links. > > > > Again, that is the focus of the product. > > > > http://www.xilinx.com/esp/optical/xlnx_net/oif.htm > > http://www.xilinx.com/esp/optical/xlnx_net/pci_express.htm > > http://www.xilinx.com/esp/optical/xlnx_net/xaui.htm > > http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Aurora > > http://www.xilinx.com/esp/optical/xlnx_net/fibre_chan.htm > > http://www.xilinx.com/esp/optical/xlnx_net/inf_band.htm > > etc etc etc > > > > All built in, no extra ICs required. > > > > Austin > > > > "Nicholas C. Weaver" wrote: > > > > > The Xilinx Answer Record states that the RocketI/Os on the V2Pro have > > > been tested and verified to work with 1000BASE-SX (fiber Gb ethernet, > > > multimode fiber). > > > > > > The media for 1000BASE-T however is a 4 pair differential signaling, > > > rather than the serial send/receive of the fiber standards. > > > > > > Are there low cost solutions for driving 1000BASE-T ethernet using the > > > RocketI/Os? > > > > > > -- > > > Nicholas C. Weaver nweaver@cs.berkeley.edu > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 48798
Ron wrote:
> I need to write an interface between Gbit MAC (ISP3 n ports) and an
> internal (fpga) design .
> Im looking for guidelines/designs that handle this issue.
Step one is to read the MAC data sheet and play
with the existing fpga testbench.
If there isn't a testbench, that's step one.
-- Mike Treseler
Article: 48799
Mike,
Just my experience, but for what it is worth...
I have been working on a design based on the Spartan2E series chip. The
FPGA is composed of a high spped timer counter, some serial d/a and a/d
signals and some other random i/o. The FPGA is being pushed in terms of
speed (200 MHz internal clock, 100 MHz external clock) but not in terms of
being full (less than 50% utilization). Tying down my I/O signals myself in
a somewhat inteligent fashion improved the timing results substantially
compared to the locations randomly picked by ISE. By the way, floorplanning
did not have nearly the impact on speed that locking i/o pins did.
Re-adjusting my picked locations to improve the "layout-ability" of the
circuit board did not substantially damage the timing of the circuit.
Remember that this circuit required speed but was not highly complex and did
not fill the chip beyond about 50%. I suspect that complex interaction
between portions of the circuit and/or high circuit utilization (in terms of
CLBs used) might likely cause problems with the circuit's maximum clock
speed.
Theron Hicks
"M Schreiber" <mschreiber75@yahoo.com> wrote in message
news:e8caa675.0210240939.389b197f@posting.google.com...
> Hello,
> I am in the process of a new design. The design is probably about 50%
> complete. All of the interfaces are defined to and from the chip but
> the internal fpga logic is not completely defined. Now I need to
> start the PCB design effort, and lock down some pins. I ran my design
> in its current state through the Xilinx tool set and had it choose the
> pins for me. Then I went back and glanced over the .ucf file and a
> few things stood out as less than optimal (at least seems that way to
> me). There are many buses throughout the design and I would have
> expected them to be grouped in a similar area of the chip, but they
> were not. The tools did manage to put all of my input clocks on
> global clock buffers and even a good portion of output clocks to other
> devices. I guess the question I am asking is what are some good rules
> of thumb (I know that these rules can't always be applied) for
> choosing pin configurations before a design is complete? Should I let
> the tools choose most of my pins and modify that list or should I
> group buses together with timing constraints, etc? I glanced through
> comp.arch.fpga for similar topics, but most of them were old and I was
> wondering if anyone had any new thoughts on the subject. This is my
> first major design that I am doing on my own (Xilinx Virtex 2
> xc2v1000fg456, vhdl based, fpga express, xilinx 4.2i tools) and I want
> to make sure I do all I can to optimize my design.
> Thanks,
> Mike Schreiber
> Hardware Engineer
> Mschreiber75@yahoo.com
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