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> I don't even know where to start, so any pointers would be helpful. Look at Altera DSP Builder. It has some kind of interface to Matlab. jerryArticle: 49451
"Philip Pemberton" <philpem@btinternet.com> wrote in message news:<aqm13o$b3voe$1@ID-122086.news.dfncis.de>... > Hi, > I've just bought an Altera EPM7128ELC84-10 EPLD for the knock down price > of £5 at a radio rally (hamfest). Does anyone know of a suitable programmer > for this thing? Altera's datasheet says it can't be programmed in-system - > does this mean I can't program it with a Byteblaster? > Has anyone tried to program a MAX7000E series FPGA with a Byteblaster? I > really don't fancy spending £400 on a programmer for a £5 chip... > > Thanks. The price from EBK is UKP7 a piece, but I think they have a minimum UKP175 order level. Altera doesn't sell online (AFAIK yet). Be careful when buying these devices second hand, as the specs say the guaranteed number of programming cycles is only 100 times. YOu may get a "retired" device. You may be better off buying CPLDs from Xilinx. Xilinx sells online via their website I think (postage and import duty may cost you dear though!). Their parallel programmer is also easy to make and you can download the circuit from their website.Article: 49452
"Amy Mitby" <amyks@sgi.com> schrieb im Newsbeitrag news:2d2a8f5d.0211121054.989342c@posting.google.com... > I'm designing an I/O device that must have ~70 32-bit > memory-mapped registers. Some are written by software > access, some are written by internal logic as status, > and all must be readable by software. The way I've done > this in the past with fewer MMRs is to just use the CLB > registers. But with 70x32 bits, that burns a lot of flops. > Granted, there are a lot of flops in the device (virtex2), > but I wanted to see if anyone had come across this problem > as well and solved it in a more area efficient manner. If you dont need fully parallel access to the register bits, you can use distributes RAM or BlockRAM to implement the registers. But then you need some kind of state machine to read/write individual registers from inside the FPGA. -- MfG FalkArticle: 49453
Is there anything 'wrong' with specifiying an output of a lower level VHDL module as a buffer so that you can read the output within the module... versus a dummy signal placed between the assignment to just an output port.Article: 49454
"Sanjay Patil" <sanjay@cg-coreel.com> schrieb im Newsbeitrag news:aqqko0$bvdvr$1@ID-164436.news.dfncis.de... > Hi, > It will generate .xnf file which is same as EDIF. > Only thing is it is Xilinx Proprietary. > It will also give .edn file at the project directory location. NO. EDIF output has been removed in version 5.1,. EDIF was never an official supported output format. -- MfG FalkArticle: 49455
what does 'pushing the rope' mean, ray? aaronArticle: 49456
visualize, visualize, visualize. answered my own question... aaronArticle: 49457
In article <ee7a49b.4@WebX.sUN8CHnE>, aaron <> wrote: >what does 'pushing the rope' mean, ray? Its a term for doing something that is really difficult and unintended. EG, ropes are designed to be pulled and under tension, they don't work when pushed. In the specific example, it is that RTL/HDL translation can be rather weird, so one tends to jump through hoops if one wants a specific result from translation. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 49458
"Phil Hays" <SpamPostmaster@attbi.com> wrote in message news:3DD05DC9.1395672B@attbi.com... > Mike Treseler wrote: > > > > Phil Hays wrote: > > > > > Austin Franklin wrote: > > > > >>That's simply not true. The Alpha CPUs were designed using schematic capture > > > > > ... by a large building full of designers. > > > > Who no longer work for Digital Equipment Corp. > > Yea. But fairness requires me to point out that schematic entry wasn't > the reason why DEC failed. Thanks for the laugh, Phil. I never even thought of that reply in that way ;-) The story of what happened to "some" of the Alpha developer, is they "went" to Intel, and worked on the subsequent Pentium processors. It was alleged (and very well founded in my opinion) that technology that was developed (and patented) by Digital for the Alpha was subsequently "used" in the Pentium designs. A lawsuit ensued. The disposition of these allegations was never legally determined, because the lawsuit was settled out of the courts...in a rather bizarre (in my opinion, at least) way. AustinArticle: 49459
Hi folks, Does anybody knows about a free EPP (parallel port) slave interface module (preferably in VHDL) ? I have checked on opencores, but it seems that their EPP controler project has no file on the CVS and has not been updated for a while. PS : this for non-commerciall use Steven Derrien IRISA, FranceArticle: 49460
The XNF format is no longer used. XST writes out an NGC file which is a Xilinx Proprietary file. This cuts out the intermediate step of reading and writing EDIF. Steve Sanjay Patil wrote: > Hi, > It will generate .xnf file which is same as EDIF. > Only thing is it is Xilinx Proprietary. > It will also give .edn file at the project directory location. > > Regards, > Sanjay > > "Young-Su Kwon" <yskwon@vslab.kaist.ac.kr> wrote in message > news:aqnceu$ll2$1@news.kreonet.re.kr... > > > > Is there anyone who have used ISE 5.1i? > > I have used ISE 4.2i previosly and succeeded to generate EDIF from XST, > > but XST of ISE 5.1i does not generate EDIF file. > > Does anyone know how to generate EDIF from XST of ISE 5.1i? > > > > > > -- > > > > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* > > Young-Su Kwon, > > E-mail : yskwon@vslab.kaist.ac.kr > > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* > > > > > >Article: 49461
Ruppen, I see a case difference between the pin names. Make sure that these match along with the bus index "<>" too. Craig Ruppen Michael wrote: > Hi, > > I have some problems with the bus macros that are used for 'intermodule > communication'. On my test-board is a virtex xcv800 FPGA and for my > diploma thesis I have to partially reconfigure this device. If I follow > the modular design flow for partial reconfiguration (xapp290), > 'ngdbuild' shows the following error: > > can not merge 'bm_4m' into block 'the_name_of_my_block' (TYPE=bm_4b) > because one or more pins on the block, including pin "li<3>", were not > found in the file. Please make sure that all the pins on the > instantiated component match pins in the lower-level design block. If > there are bussed pins on this block, make sure that the upper-level and > lower-level netlists use the same naming convention. > > bm_4b.nmc is the macro provided by Xilinx. When I open it with the > FPGA-Editor, the port names are exactly the same I use in my VHDL code > (LI, LT, RI, RT, O), but it doesn't work. Why? > Has someone some experience with this design flow? > > Thanks, > > Michael -- Craig Cholvin, Software Technical Marketing Manager Xilinx, Corp., 3100 Logic Drive, Longmont, CO 80503 Ph: (720) 652-3687, FAX: (720) 652-3444 Internet: craig.cholvin@xilinx.comArticle: 49462
David Binnie wrote: > > Apart from DOS based PALASM does anyone know of any freeware which can > generate a JEDEC file from Boolean equations or other descriptor ? The WinCUPL on Atmels web can do this. It can be used from the GUI, or from a std editor / command line mode. CUPL sits between PALASM and VHDL/Verilog and is somewhat analogous to a 'structured assembler on a uC'. CUPL can also create Test Vectors in the JED file, allowing 100% functional test after device program - well suited to 20/24/44 pin device flows. -jg -- ======= 80x51 Tools & IP Specialists ========= = http://www.DesignTools.co.nzArticle: 49463
"Goran Bilski" <Goran.Bilski@Xilinx.com> wrote > Quantitative (Number of operations per seconds/ needed area) > > Floating point : (100_000_000/6)/800 = 20833 > Integer : (250_000_000/1)/32 = 7812500 > > Integer operations are roughly 400 times more efficient than floating point. Thanks for the interesting data, Goran. Can you pipeline the above FP adder to get a factor of ~6 improvement in ops/area efficiency? Also, if you only care about ops/area cost efficiency, and not pure speed, you might be able to use bit or nybble serial approaches, use lots of SRL16s for delays, and thereby avoid the big expensive barrel shifters in the denormalize and renormalize paths. Jan Gray, Gray Research LLCArticle: 49464
Does anyone have any general suggestions or remarks from past work on a 200 MHz large Virtex2 design? For instance, did you have to do things like: - add input and output flops for each module and pipeline extensively within modules? - other RTL tricks? - use a physical synthesis tool like Amplify? - run multi-pass place and route? - use different cost tables? - hand place some or all of the design? - etc...Article: 49465
RE: "pushing on a rope": I think I brought this phrase into the vernacular of this forum. I picked up the concept years ago from Charles Simonyi, who observed (and this loose paraphrase does him little justice) that when you pull on a rope you control a force vector to effect a direct and specific result -- whereas when you are in a "pushing on a rope" situation, you exert little direct control, and can (at best) act indirectly to move the system towards a desired outcome. > In the specific example, it is that RTL/HDL translation can be rather > weird, so one tends to jump through hoops if one wants a specific > result from translation. >From fpgacpu.org/usenet/rope_pushing.html: 'This is "pushing on a rope". You know exactly what you want -- a particular optimal, hand-mapped, hand-placed layout for your datapath -- but the tools get in the way, and you spend hours trying to discover an incantation that persuades the tools to emit the desired result.' The same goes for writing C code over and over again until you discover what to say to the compiler so that it generates the assembly code you expect. Jan Gray, Gray Research LLCArticle: 49466
In article <2d2a8f5d.0211121414.8a292e8@posting.google.com>, Amy Mitby <amyks@sgi.com> wrote: >Does anyone have any general suggestions or remarks >from past work on a 200 MHz large Virtex2 design? I haven't done that on Virtex2, but I have done >100 MHz on Virtex I (non E) and 175 MHz on VirtexE (AES encryption): >For instance, did you have to do things like: >- add input and output flops for each module and pipeline > extensively within modules? Yes, lots. >- hand place some or all of the design? Yes, lots. Hand mapping and placing isn't that bad, if you use a nice modular design. The biggest annoying is actually the BlockRAMs, as on Virtex 1, they can't be relatively placed, only absolute placement, which is a pain when everything else is RLOCed modules. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 49467
In article <aqrul3$oke$1@slb2.atl.mindspring.net>, Jan Gray <jsgray@acm.org> wrote: >RE: "pushing on a rope": > >I think I brought this phrase into the vernacular of this forum. I picked >up the concept years ago from Charles Simonyi, who observed (and this loose >paraphrase does him little justice) that when you pull on a rope you control >a force vector to effect a direct and specific result -- whereas when you >are in a "pushing on a rope" situation, you exert little direct control, and >can (at best) act indirectly to move the system towards a desired outcome. Also see it alot in the economics vernacular. EG, the notion of a liquidity trap, when the interest rate is 0, the central bank can't make the interest rates any lower. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 49468
Stan wrote: > "rk" babbled: >> Peter Alfke wrote: >> >> [ snip ] >> >> > Do like all other >> > customers, trust us...:-) BTW, would you ever consider testing a >> > Pentium chip??? >> >> Couldn't resist: >> >> http://www.ku.edu/cwis/units/IPPBR/pentium_fdiv/pentgrph.html >> >> Now back to our regularly scheduled program. > Sorry to go so far off topic, but you did it first. The > Pentium problem was a DESIGN bug. This thread is about > testing for MANUFACTURING defects! Off topic, in usenet? Surely you jest! Anyways, I just went back and read the original post and it didn't discriminate, only stated functional testing. Peter didn't mention manufacturing defects either. Now, if you really want to get off topic, but software reliability is what, between 1 error per 100 lines of code (commercial) to 1 error per 1000 lines of code (hi-rel) to 10x better (really hi-rel) and how many lines of code are there in these CAE systems? P.S. I did have a defective Pentium chip. -- rk, Just an OldEngineer "A good engineer gets stale very fast if he doesn't keep his hands dirty." -- Wernher von Braun, 1964Article: 49469
How about
INST "*WDATABuf*" IOB=FALSE;
??
INST
"Shareef Jalloq" <sjalloq@arm_removeMe_.com> wrote in message
news:3DD13234.525C7CA6@arm_removeMe_.com...
> Hi all,
>
> I'm trying to disable IOB register packing but am having trouble with
> the UCF syntax. I know I want to put IOB=FALSE; in there somewhere but
> how do I do it? I need to add the constraint to a number of top level
> registers that are already grouped by a TIMEGRP constraint. I tried
> using the following but it didn't like it:
>
> TIMEGRP "SRAMData" = FFS("*WDATABuf*");
> INST "SRAMData" IOB=FALSE;
>
> Any ideas guys? Thanks for your help, Shareef.
>
Article: 49470Oh, I see. I've used Verilog to instance specific macros when Synopsys has done a poor job, but I don't think of that as a hardware description language, it seems to me more like using Verilog as a simple etlister. -Stan "Ray Andraka" <ray@andraka.com> wrote in message news:3DD090A2.9BC0559A@andraka.com... > One can code at the primitive level using an HDL, in which case it is > generally not regarded as RTL. The reasons for doing so include > instantiating features that do not get correctly inferred, and instantiating > a particular structure for performance or placement reasons or to avoid a the > 'pushing on a rope' that can often accompany an RTL design when there is a > particular structure desired. > > Stan wrote: > > > "RTL" stands for Register Transfer Level. As opposed to gate level or > > transistor level. > > > > I think a lot of people might make a statement like "I used a Hardware > > Description Language to code my design at the Register Transfer Level." > > > > Of course that statement is a bit redundant, because the idea of coding at > > the gate level or transistor level using an HDL doesn't make much sense. > > > > -Stan > > > > "Anonymous4" <nicemanYep@yahoo.co.uk> wrote in message > > news:f9028e31.0211111347.2bc4c99c@posting.google.com... > > > Hello, > > > Basic Question i know but confused on: > > > what is the difference between Hardware Description Language (HDL) and > > Register > > > Transfer Logic(RTL) > > > Thanks > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 49471
Hello, when i try to synthesize the following code using Leonardo Spectrum for Xilinx FPGAs, I get errors " Syntax Error near 'when' " If I dont use a process and then synthesize this code, it works fine. But I do need to have a process in my design. Can someone provide me a solution for this. Thanks Anup Raghavan entity mux_tbuf is port (SEL: in STD_LOGIC_VECTOR (4 downto 0); A,B,C,D,E: in STD_LOGIC; clk : in std_logic; SIG: out STD_LOGIC); end mux_tbuf; architecture RTL of mux_tbuf is begin sync: process (clk) is begin if clk'event and clk = '1' then sig <= A when sel = "11110" else 'Z'; sig <= B when sel = "11101" else 'Z'; sig <= C when sel(2)= '1' else 'Z'; sig <= D when sel(3)= '1' else 'Z'; sig <= E when sel(4)= '1' else 'Z'; end if; end process sync; end RTL;Article: 49472
"Max K." wrote: > > hello, > me & my partner need to test this chip. > > is there a systematic way of functional testing of an FPGA chip ? I have a paper here called "Testing FPGA Devices using JBITS" which considers exactly this problem. The authors are all from Xilinx - Sundararajan, McMillian and Guccione. I found it on the web, if you search for the title and authrs names you should find it. Regards, JohnArticle: 49473
Terry Newton wrote:
> >http://www.sussex.ac.uk/Users/tapu9/publications/uk_acm_sigda_02.pdf
>
> Very interesting. I haven't tested, but I made two versions of
> the 74181 ALU using schematic entry, differing only in carry
> lookup connections (synthesis wouldn't allow unused nets/pins).
> The "no carry out" version (for low/middle slices) used 23 lookup
> tables, the "no propagate" version (for the high slice) used 24.
I pointed out that "If nothing else the review of examples was weak." I
maybe should have complained more.
Plugging the "HDL structural description" into Synplify Pro for a 4004A
gave me:
---------------------------------------
FMAPs: 23 of 200 (12%)
HMAPs: 4 of 100 (4%)
Total packed CLBs: 12 of 100 (12%)
---------------------------------------
Webpack XST (5.1) will not target the 4004, so I pointed it to a
Spartan2.
------------------------------------------
Number of 4 input LUTs: 26
------------------------------------------
> A '182 CLG took only 7 LUT's. These "parts" were entered directly
> from data sheet logic diagrams into WebPack 4.2 targeted for a
> Spartan II ('50), only one 4-in gate was omitted in the nco
> version so a full 181 should consume 25 LUT's.
>
> The VHDL structural description in the article required 46 CLB's,
> which for the 4004 I'm assuming contains 1 LUT.
Two 4-in LUTs plus a small 3-in LUT per CLB in the 4000 family. The
HMAP or 3 in LUT isn't very usable, as the choice of inputs is quite
limited.
> This seems to
> imply that schematic entry is almost twice as efficient as
> structured VHDL!
Weak examples imply nothing.
--
Phil Hays
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