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I'm not aware of a currently available reference design. I would suggest you
pick up a copy
of Marv Frerkings digital communications text. It is an excellent reference for
digital
communications, very well written and practical. If you order through this link
http://www.amazon.com/exec/obidos/ASIN/0442016166/andraka/103-9628892-6638266
or through the bookstore on my website, I get a kickback which helps to
maintain the website.
I'd also recommend the Uwe Meyer DSPs in FPGA book for hardware implementation
for FPGAs (not much specific to radio in there), and the Lee and Messerschmitt
is a
good companion to the Frerking book.
You can't jsut drop samples unless your signal is already bandlimited to have a
bandwidth
less than your end sample rate. You can however often get away with fairly
simple filters
at the higher data rates. Usually, we will try to filter and decimate as soon
as practical
in order to reduce the processing load. If your signal is narrow band, you can
use a
multirate filter to decimate the signal rather efficiently. Only one stage of
that filter
has to be real good (and that is usually done at the lowest sample rate). The
other stages can
be CIC or halfband filters which give you lots of bang for very little hardware.
Jeff wrote:
>
> I want to know where I can get a reference design in FPGA about my problem.
> FPGA venders have such library?
> Of course, I have to get the analog antialiase filter specification in order
> to design the digital low pass filter. Are there any such filter designs in
> FPGA?
>
> About the decimating filter, if I select the sample clock rate at integer
> times of input data rate, I can simply discard some bits regularly? If not,
> I can digitally interpolate value and decimate data?
> I have no practical experience about these. What book or website can give me
> some reference, especially applications on FPGA?
>
> Thanks
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49526"Ray Andraka" <ray@andraka.com> wrote in message news:3DD333C0.702E42EF@andraka.com... > Nothing says you have to use full IEEE floating point. A numerical analysis of your > problem will provide how much dynamic range and accuracy you need at each step. > From there you can determine how many bits of exponent and significand are really > needed. Small format Floating point and allowing it to denormalize over several > operands can get you an implementation that is more efficient than fixed point. Well, more efficient than putting a huge number of fixed point bits to cover the required dynamic range. Floating point add and subtract are complicated by pre and post normalization, which takes a lot of cells. Multiply and divide are complicated, but not much more than fixed point. LU decomposition is similar to matrix inversion, it will have a lot of add, subtract, multiply, and divide. With only three variables, there might be simplifications that can be made. Depending on how fast it needs to be, one can adjust the pipeline depth (and reuse some of the logic for successive rows/columns, or not). Also, depending on speed required the logic of the mutliplier and divider can be reused for some number of cycles to get all the bits through. Books on pipelined computer architectures give the algorithms for implementing multipliers and dividers. Another possibility is to implement a large number of simple bit serial processors to process many of these in parallel. -- glenArticle: 49527
bbrown wrote: > I'm looking for resources, either free or IP, I can use to make a > simple kind of switching fabric in an FPGA. I have a bunch of 8-bit > busses (actually 5 sets of input/output busses) I would like to funnel > into a single FIFO, or connect arbitrarily to each other. I've heard > horror stories of trying to do this muxing inside an FPGA and meet > timing (I'll be running these busses at 54 MHz) so I'm interested in > what people have experience with. > > thanks in advance, > brandon Are the busses source synchronous? Are all your incoming busses synchronous to each other? I have implemented something close to this but with source synchronous serial busses and it is actually doable but you need to do rate adaptation if you have different clocks coming in. In addition, you need to be aware that it is really difficult to manage the skew between parallel lines inside the FPGA. My 2 cents ... DaliArticle: 49528
<Jee@hotmail.com> wrote in message news:3DD29440.FF1E5D38@hotmail.com... > Hi, > I am using Xilinx ISE5.1i, I have a design with has some IOBUF pins > requiring LVDCI_25 type, I was told I can name the IOBUF type in UCF > file, but I do not know the syntax. Could you point me the correct > syntax for that? > Is that NET "sdr_dq<0>" LOC ="T2", attribute = LVDCI_25; ? > > Thanks, Try this: NET "net_name" IOSTANDARD = LVDCI_25; BR, Jyke.Article: 49529
"dan" <whimsica@aol.com> wrote in message news:819c1aba.0211110000.3c1eae8b@posting.google.com... > I want to take a 1920x1440 rgb output, Break it up into 9 640x480 > pieces, and broadcast each piece to a separate uhf channel. > > How much would it cost to build something like that. > What kinds of skills would a person need to have? > > It's for a science project Others have given you some answers. This sounds about like an undergrad senior project, which will take most of the year (while also taking classes) to work on. Maybe a little ambitious for that, but high end people could probably do it. If you can keep it digital, you would have a much better chance, but there is still much of digital signal processing theory that you should know about. The book "Techniques & Standards for Image, Video, and Audio Coding" describes much of digital audio and video coding systems. You might find it in a university library. -- glenArticle: 49530
"Nicholas C. Weaver" wrote: > In article <aqrul3$oke$1@slb2.atl.mindspring.net>, > Jan Gray <jsgray@acm.org> wrote: > >RE: "pushing on a rope": > > > >I think I brought this phrase into the vernacular of this forum. I picked > >up the concept years ago from Charles Simonyi, who observed (and this loose > >paraphrase does him little justice) that when you pull on a rope you control > >a force vector to effect a direct and specific result -- whereas when you > >are in a "pushing on a rope" situation, you exert little direct control, and > >can (at best) act indirectly to move the system towards a desired outcome. > > Also see it alot in the economics vernacular. EG, the notion of a > liquidity trap, when the interest rate is 0, the central bank can't > make the interest rates any lower. > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu The first time I ever read it was in some article/book by JK Galbraith applied to the general idea of attempting to control the economy exclusively through interest rate manipulation.Article: 49531
"Justin A. Kolodziej" wrote: > Does anyone have a pointer to a canonical list of things to do and avoid > doing when you want to write VHDL that has a good chance of actually > synthesizing correctly in Leonardo? > > I only know that what I do tends to work better than what my students do > (I have the unfortunate task of TAing a class in embedded systems and > reprogrammable logic), but I admit that I don't have such a list of rules > that will guarantee that VHDL works when it is synthesized, even if it > works in simulation. > > Certainly someone out there must have a list... and I don't mean the > "Synthesizable VHDL" subset, because even if the synthesis tools gives no > warnings or anything, things can break horribly when additional processes > are added, it seems. As others have said the basic rule is ``keep it synchronous'' with the side rule of understanding what to do for signals that cross clock domains e.g. between the system and PCI clocks. A corollary of this is that your code should really not have any explicit delay statements (*). If you stick to this rule then its useful to have some script that goes through the post-synth report(s) looking for inferred latches. One grey area is inference of memories from HDL structures. This is tool dependent with Synplify & Leonardo being able to do it for FPGAs but FPGAExpress/FPGACompiler not. What will happen is that for Synplify & Xilinx you might get a small number of RAM16X1s but from F-Exp you'd get a huge number of register bits and a large morass of address decode logic. Even if small memories can be inferred it can be problematic to write code for the big dualport RAMs in X & A FPGAs. (*) I question I've always wanted to know the answer to here. Why is it so common to see this sort of thing: `ifdef VCS // ... some comment about avoiding a race condition ... #1 `endifArticle: 49532
Shareef Jalloq wrote: > hamish@cloud.net.au wrote: > > > INST "*" IOB = FALSE; > > is useful for test routes of sub-modules. > > Hi again guys, > > although I used the above syntax in the UCF file, the Xilinx tools still > packed the flops into the IOB! What can I do aside from adding a dummy > output so that the fanout of the Q pin is higher than 1. This would at > least guarantee that the flops could not be packed into the IOB. I'm using > version 4.2.03i of the Xilinx tools on Solaris. > > Shareef. First I'd check whether MAP is being run with the -pr (pack registers) flag. IIRC the UCF is supposed to override -pr but I do remember some historic bugs in this area. If this doesn't work then it may be time to trawl the Xilinx answers database. If nothing there then its time to file a bug report + test case with Xilinx.Article: 49533
Amy Mitby wrote: > I'm designing an I/O device that must have ~70 32-bit > memory-mapped registers. Some are written by software > access, some are written by internal logic as status, > and all must be readable by software. The way I've done > this in the past with fewer MMRs is to just use the CLB > registers. But with 70x32 bits, that burns a lot of flops. > Granted, there are a lot of flops in the device (virtex2), > but I wanted to see if anyone had come across this problem > as well and solved it in a more area efficient manner. ... not to mention all the LUTs needed for the address decoding ... If you're in a position to do so - i.e. not cloning some other device or protocol spec. - then the very first step is to go back to the system architect(s) and push very hard for a simplification of the s/w interface to the device.Article: 49534
first of all, thanks everyone for your valuable insights. equation: AX=B A 3x3 X 3x1 B 3x1 Maybe i was wrong in implementing LU decomposition. So i try to write it down in the normal way of solving the matrix inverse by first calculating the cofactors of each, taking the adjoin matrix and divide by the determinant. Finally, i multiply it with the B on the RHS. i dont' have experience in writing HDL so i started with verilog. But i have problems with the dividing part, any suggestions? it say error:Xst:870 Can not use the DIV Anyone done this before? or anyone know any useful website which has a collection of verilog examples be it matrix, arithmetic? Thanks again.Article: 49535
Peter and Erich thank you for the help !Article: 49536
Hello, I have an EPC16 which have to configure 4 FPGA EP20K400. I load my design in the APC16 using QuartusII through the JTAG interface. I also verify it, using an other programmer. The signals nInitConf/nConf and nOE/Status go high but the DClk is not toggling. This state should occured when the EPC16 doesn't contain design which is in contradiction which what the programmer tell me. Why the DClk doesn't run? Could you help me to configure my FPFA through my EPC16? Thanks a lot,Article: 49537
lass <lass@xilinx.com> wrote in message news:<3DD1750B.A09AFF46@xilinx.com>... > The XNF format is no longer used. XST writes out an NGC file which is > a Xilinx Proprietary file. This cuts out the intermediate step of reading > and writing EDIF. > > Steve > > Sanjay Patil wrote: > > > Hi, > > It will generate .xnf file which is same as EDIF. > > Only thing is it is Xilinx Proprietary. > > It will also give .edn file at the project directory location. > > > > Regards, > > Sanjay > > > > "Young-Su Kwon" <yskwon@vslab.kaist.ac.kr> wrote in message > > news:aqnceu$ll2$1@news.kreonet.re.kr... > > > > > > Is there anyone who have used ISE 5.1i? > > > I have used ISE 4.2i previosly and succeeded to generate EDIF from XST, > > > but XST of ISE 5.1i does not generate EDIF file. > > > Does anyone know how to generate EDIF from XST of ISE 5.1i? > > > > > > > > > -- > > > > > > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* > > > Young-Su Kwon, > > > E-mail : yskwon@vslab.kaist.ac.kr > > > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-* > > > > > > > > > Hi, Will this give any better performance compared to the .edf from some other synthesis tool and give to xilinx's ISE5.1i Place and Route tool? have any one experienced on this? Best regards, MuthuArticle: 49538
fictionalsam@mail.com (fictionalsam) wrote in message news:<48fbbbca.0211112121.19fddd53@posting.google.com>... > polly@rz.fh-augsburg.de (Thomas Pollischansky) wrote in message news:<6b0e63fc.0211060947.186ef2b0@posting.google.com>... > > Has anyone got experiance in using Nios 1.1 together with Quartus II > > 2.11. > > My Nios processor designs are not completely compiled. Half of the > > NIOS processor is missing on the FPGA (no internal memory..). > > Has anyone had problems like that or know what might be the reason > > (forgotten Options in Quartus...)? Thanks for any answers! > > Two things to try > 1. in Project->General Setting->Library, make sure you have an entry > pointing to the directory where your nios stuff was built, ie. > directory where nios.ptf, nios.v, cpu.v, etc reside. There are a bunch > of black boxes in the nios design that Quartus will need to find, like > boot_rom_lane0.v, ram lanes, etc and mifs that go inside those > internal rams. > 2. Make sure you dont have any synthesis directives inside any of the > files Quartus reads. Quartus 2.1 has started respecting synthesis > directives like "synthesis syn_black_box=1", "synthesis translate > off", etc. If you have any of these in any of the files Quartus reads > in, then Quartus will leave the blackbox as is and will not insert the > contents of the black box. > > Let me know (thru this newsgroup) if any of these help. > > PS: The Project->General Setting->... part might be slightly off. I > dont have Quartus here to check the correct menu options to get to > there. Thanks for your answer! I have updated to the newest Quartus and Nios software products - no the compilation process runs without any problems. As I stated in a earlier message - according to Altera support not all versions of each program fit together. ThomasArticle: 49539
Hello, I was wondering if anyone on here might have some idea on how to bring in a signal that needs to be tristated on one input pin and route it out to another pin as an output. This seems to be fairly "simple" but evidently webpack sees the need to route through a macrocell. Don't the I/O blocks have tristate buffers built in, is there some way to force routing without going through a macrocell ? Thanks!Article: 49540
Try Chameleon POD on www.amontec.com Falk Brunner wrote: > "Steven Derrien" <sderrien@irisa.fr> schrieb im Newsbeitrag > news:3DD17371.5C0234D9@irisa.fr... > >>Hi folks, >> >>Does anybody knows about a free EPP (parallel port) slave interface >>module (preferably in VHDL) ? I have checked on opencores, but it seems >>that their EPP controler project has no file on the CVS and has not been >>updated for a while. > > > Have a look at www.beyondlogic.org > They have tons of techical papers, also many about parallel port /EPP. > Doing a state-machne to interface to a EPP is easy. Just sample Data_stobe > and Address_strobe, thendo your descision on this. > Se the code snippet below. > > -- > MfG > Falk > > ---------------------------------------------------------------------------- > ----------------- > -- > -- A basic EPP state machine > -- > ---------------------------------------------------------------------------- > ----------------- > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.NUMERIC_STD.ALL; > > entity epp_fsm is > Port ( clk : in std_logic; -- clock > input >1 Mhz > reset : in std_logic; > > epp_data : inout unsigned(7 downto 0); -- data > epp_write : in std_logic; -- > epp_wait : out std_logic; > epp_data_strobe : in std_logic; > epp_adr_strobe : in std_logic); > > > end epp_fsm; > > architecture Behavioral of epp_fsm is > > type state_type is (idle, wait_end, wait_end_read); > > signal state : state_type; > signal data_strobe : std_logic; -- > synchronized data strobe form EPP > signal adr_strobe : std_logic; -- > synchronized address strobe form EPP > signal data_register : unsigned (7 downto 0); -- data > register, just a example > signal address_register : unsigned (7 downto 0); -- > address register, just a example > > begin > -- some signal assignments > > -- IO MUX for EPP data > > process(state, data_register, address_register) > begin > if state=wait_end_read then > if data_strobe='1' then > epp_data <= address_register; -- address > read access > else > epp_data <= data_register; -- data read > access > end if; > else > epp_data > -- no read access > end if; > end process; > > -- sample control lines from EPP > > process(clk, reset) > begin > if reset='1' then > data_strobe <= '1'; > adr_strobe <='1'; > elsif clk='0' and clk'event then > data_strobe <= epp_data_strobe; > adr_strobe <= epp_adr_strobe; > end if; > end process; > > -- the state machine > > process(clk, reset) > begin > if reset='1' then > state <= idle; > epp_wait <='0'; > elsif clk='0' and clk'event then > case state is > when idle => if data_strobe='0' then -- beginning > of an data access > epp_wait <= '1'; > if epp_write='0' then -- it is a > write access > > -- place instructions HERE for data write > access > data_register <= epp_data; -- example > > state <= wait_end; > else -- it is a > read access > > -- place instructions HERE for data read > access > > state <=wait_end_read; > end if; > elsif adr_strobe='0' then -- adress > access > epp_wait <= '1'; > if epp_write='0' then -- it is a > write access; > > -- place instructions HERE for address write > access > address_register <= epp_data; -- > example > state <= wait_end; > else -- its a > read access > > -- place instructions HERE for address read > access > state <= wait_end_read; > end if; > end if; > > when wait_end => if data_strobe='1' and adr_strobe='1' > -- wait for the end of a write access > epp_wait <='0'; > state <= idle; > end if; > when wait_end_read => if data_strobe='1' and adr_strobe='1' > -- wait for the end of a read access > epp_wait <='0'; > state <= idle; > end if; > when others => null; > end case; > end if; > end process; > > end Behavioral; > > >Article: 49541
Hi Laurent, Laurent Gauch wrote: > > Try Chameleon POD on www.amontec.com > Do you have any specific link ? I have browsed through your website but I could not find anything related to an EPP vhdl core. Thank you, StevenArticle: 49542
iluvfpgas@yahoo.ca (Alfredo) wrote in message news:<afaad421.0211131255.252e949d@posting.google.com>...
> What is systemC? How is it different from other verification
> languages?
1. SystemC is not a pure language as VHDL or Verilog or C/C++; it is
set of C++ class libraries. Its main purpose is description and simulation
of large systems where software and hardware coexist on equal terms.
> Is SystemC compatible with System Verilog, Super log, or the like?
2. It is not, and it is good thing.
<swithing to sarcastic mode> System Verilog and Superlog are miserable
attempts to convert Verilog into something resembling normal programming
or hardware description language. Since Verilog camp zealots are totally
impervious to discussion based on issues, going any further here is pointless.
<back to regular mode>
> Are assertion based languages competing in the same space as SystemC?
3. No, they have narrower scope than SystemC
> What are the alternatives to SystemC when architecting/simulating
> hardware systems?
4. When it is pure hardware system (no embedded microcontrollers etc.)
you will do everything faster and more efficiently using VHDL or Verilog.
If your system contains RTOS (real time operating system) or any other
significant software part, SystemC saves a lot of time wasted on constant
translations between C descriptions and HDL descriptions. Plus, it is the
only solution that is close to standarization phase...
> Why would anyone bother to lear and use SystemC? Or, is it better to
> wait for "wide acceptance" before spending time & effort on yet
> another modeling language?
5. If you are designing small to medium FPGAs you can skip SystemC for a
moment. If you are in large FPGA/ASIC designs, it is good idea to start
right now, because sooner or later SystemC is going to get you...
Some remarks after my personal experiences with SystemC:
I. On the PLUS side:
- you can get sources for SystemC for free, compile them using your C++
compiler and you are ready to go
- testbench is necessary part of esch design, because what you get after
final compilation is an executable you can run on your system
- if you have good C++ compiler, your simulation should be very fast
(I have seen it on small designs, have not aquired/created large designs
for verification of this statement yet.)
- if you have working knowledge of C/C++ and either VHDL or Verilog, you
can write your first SystemC designs relatively fast
II. On the MINUS side:
- while installing and running SystemC on Unix/Linux is regular task,
Windows users should beware: commercial C++ compilers have issues with
SystemC. I have tried Microsoft and Borland and wrecked my nerves -
switching to Cygwin/g++ finally worked...
- if you are using VHDL/Verilog on daily basis, you will be suprised
how irritating some features of SystemC are for hardware descriptions:
== switch statement accepts only inetger select expression anb choices
(compare to case with vector expressions in HDLs)
== bit-level access to vectors is possible only for variables, but not
for ports and signals; simple task od splitting a bus or combining
individual signals into a bus requires some heavy coding
== ...
- majority of documentation for SystemC was written by system people
for system people (chapter demonstrating SystemC coding for VHDL users
in official manual is repository of most ridiculous coding styles).
The only good book on SystemC for hardware people is "A SystemC Primer"
by J. Bhasker - highly recommended!!!
Hope it helps,
Jerry
Article: 49543"Justin A. Kolodziej" <jkolodzi@students.uiuc.edu> wrote in message news:<Pine.GSO.4.31.0211111730001.3254-100000@ux13.cso.uiuc.edu>... > Does anyone have a pointer to a canonical list of things to do and avoid > doing when you want to write VHDL that has a good chance of actually > synthesizing correctly in Leonardo? > > I only know that what I do tends to work better than what my students do > (I have the unfortunate task of TAing a class in embedded systems and > reprogrammable logic), but I admit that I don't have such a list of rules > that will guarantee that VHDL works when it is synthesized, even if it > works in simulation. > > Certainly someone out there must have a list... and I don't mean the > "Synthesizable VHDL" subset, because even if the synthesis tools gives no > warnings or anything, things can break horribly when additional processes > are added, it seems. Hi Justin, Isn't it just a case of the VHDL having to match the software interpreting it, that is the synthesis tool. Packages like FPGA Express have a large manual telling you how to write VHDL that will be correctly synthesised. A wise person would follow these templates religiously. However easy to remember rules of thumb are more interesting and memorable. Good question! Regards PhilArticle: 49544
What about Verisity Specman? -- Marty "Jerry" <jaroslawk@hotmail.com> wrote in message news:711e889f.0211140852.633528d9@posting.google.com... > iluvfpgas@yahoo.ca (Alfredo) wrote in message news:<afaad421.0211131255.252e949d@posting.google.com>... > > What is systemC? How is it different from other verification > > languages? > 1. SystemC is not a pure language as VHDL or Verilog or C/C++; it is > set of C++ class libraries. Its main purpose is description and simulation > of large systems where software and hardware coexist on equal terms. > > > Is SystemC compatible with System Verilog, Super log, or the like? > 2. It is not, and it is good thing. > <swithing to sarcastic mode> System Verilog and Superlog are miserable > attempts to convert Verilog into something resembling normal programming > or hardware description language. Since Verilog camp zealots are totally > impervious to discussion based on issues, going any further here is pointless. > <back to regular mode> > > > Are assertion based languages competing in the same space as SystemC? > 3. No, they have narrower scope than SystemC > > > What are the alternatives to SystemC when architecting/simulating > > hardware systems? > 4. When it is pure hardware system (no embedded microcontrollers etc.) > you will do everything faster and more efficiently using VHDL or Verilog. > If your system contains RTOS (real time operating system) or any other > significant software part, SystemC saves a lot of time wasted on constant > translations between C descriptions and HDL descriptions. Plus, it is the > only solution that is close to standarization phase... > > > Why would anyone bother to lear and use SystemC? Or, is it better to > > wait for "wide acceptance" before spending time & effort on yet > > another modeling language? > 5. If you are designing small to medium FPGAs you can skip SystemC for a > moment. If you are in large FPGA/ASIC designs, it is good idea to start > right now, because sooner or later SystemC is going to get you... > > Some remarks after my personal experiences with SystemC: > I. On the PLUS side: > - you can get sources for SystemC for free, compile them using your C++ > compiler and you are ready to go > - testbench is necessary part of esch design, because what you get after > final compilation is an executable you can run on your system > - if you have good C++ compiler, your simulation should be very fast > (I have seen it on small designs, have not aquired/created large designs > for verification of this statement yet.) > - if you have working knowledge of C/C++ and either VHDL or Verilog, you > can write your first SystemC designs relatively fast > II. On the MINUS side: > - while installing and running SystemC on Unix/Linux is regular task, > Windows users should beware: commercial C++ compilers have issues with > SystemC. I have tried Microsoft and Borland and wrecked my nerves - > switching to Cygwin/g++ finally worked... > - if you are using VHDL/Verilog on daily basis, you will be suprised > how irritating some features of SystemC are for hardware descriptions: > == switch statement accepts only inetger select expression anb choices > (compare to case with vector expressions in HDLs) > == bit-level access to vectors is possible only for variables, but not > for ports and signals; simple task od splitting a bus or combining > individual signals into a bus requires some heavy coding > == ... > - majority of documentation for SystemC was written by system people > for system people (chapter demonstrating SystemC coding for VHDL users > in official manual is repository of most ridiculous coding styles). > The only good book on SystemC for hardware people is "A SystemC Primer" > by J. Bhasker - highly recommended!!! > > Hope it helps, > > JerryArticle: 49545
"Jens Niemann" <Jensniemann@gmx.de> schrieb im Newsbeitrag news:aquop4$deqj4$1@ID-92522.news.dfncis.de... > Hi folks, > I have to program a Spartan2 with a USB Microcontrolle in JTAG mode. > (I know that programming in serial mode would be easier) > The data stream should come from the host directly to the FPGA and also to > large I2C memory. > The I2C memory is for booting without host. > Now I need some information about the Bit file format or any other file > format that fits my wishes. > Also I would be very happy about some suggestions, tips and hints to > possible traps. Configuring a Spartan-II in JTAG mode is easier than it looked to me some weeks before. All you need to do is - set the JTAG FSM to reset, which is just five or more clocks on TCK while TMS is HIGH - load the CFG_IN instruction - load the complete datastream, just byte by byte into the device. You can use the *.bit file for this, just make sure you skip the crap at the begining. The real data stream starts with the 0xFFFFFFFF sequence, which has an (non-fixed !!) offset somewhere about 50..100. - load the JTSART instruction - load 12 or more dummy databit into the data register - You are done. Make sure you select the JTAG clock when generation the bitfile, otherwise the device will not start. xapp188 is a good source of informations on this topic. -- MfG FalkArticle: 49546
"Mark Smith" <mark.smith@latticesemi.com> wrote in message news:<BqEA9.4299$R5.2396272@nnrp1.ptd.net>... [...] > P.S. However, I'd be genuinely interested to know if anybody HAS used the > Lattice devices in real comparison tests with X & A, and what they > think...feedback is always welcome... You asked for it... here it is, short and sweet (related to the FPSC): 1. Software needs a serious upgrade - it is like Xilinx *WAS* (5 years ago) 2. The support we received for the SONET framing function was greatly lacking, at least in Dallas. 3. The internal 2.5 Gbps SERDES are super 4. Need more logic cells Details on #2: Using the demo system we couldn't get the SONET framing functions to interoperate with an HP test set. So the inexperienced FAE starts sending us "possible" bitstream fixes for us to try. Except he didn't have any way to test them, so they didn't work either. After a number of weeks, we received an unrelated fix for the demo software that allowed us to start trying configurations, which we quickly figured out. My concern is why that wasn't a plug-and-go type demo - it must have been done before! Hard cores for various applications are appearing more and more to be the way of the future. If you have the right selection of hard cores (channelized SONET framers, MAC's, SERDES', etc) available and easy to use, you'll win lots of designs assuming the other stuff is corrected. Lattice actually has a slight lead, but others are on your heals... MarcArticle: 49547
On Thu, 14 Nov 2002 19:00:24 +0100, Falk Brunner <Falk.Brunner@gmx.de> wrote:
>"Jens Niemann" <Jensniemann@gmx.de> schrieb im Newsbeitrag
>news:aquop4$deqj4$1@ID-92522.news.dfncis.de...
>> I have to program a Spartan2 with a USB Microcontrolle in JTAG mode.
>
>Configuring a Spartan-II in JTAG mode is easier than it looked to me some
>weeks before. All you need to do is [chop]
>
>Make sure you select the JTAG clock when generation the bitfile, otherwise
>the device will not start.
>xapp188 is a good source of informations on this topic.
All good information. For the various parallel port JTAG
adaptors, I have working code posted at
http://recycle.lbl.gov/~ldoolitt/jtag.html
I have a new version almost ready, which (thanks to Ludovic L'Hours)
can also _re_program a Spartan-II. None of this has any bearing
on the OP's request to also handle the programming of a large I2C memory.
- Larry
Article: 49549Don wrote: > Hello, > > I was wondering if anyone on here might have some idea on how to bring > in a signal that needs to be tristated on one input pin and route it > out to another pin as an output. This seems to be fairly "simple" but > evidently webpack sees the need to route through a macrocell. Don't > the I/O blocks have tristate buffers built in, is there some way to > force routing without going through a macrocell ? Thanks! For XC95K parts the I/O blocks are tied to specific macrocells and all inputs are distributed to the function blocks via the switch matrix. So the only way from one pin to another is: I/O input A -> switch matrix -> macrocell B -> I/O output B
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