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Bob W wrote:
>
>
> I failed to mention that I use Altera's MaxPlus software rathern than
> Quartus II. Sorry, I should have mentioned that in my original post
About a year and a half ago, when I started to developing a PCI
IP core, I needed some kind of a development tool.
Because Altera and Xilinx were letting people use MAX+PLUS II-BASELINE
and WebPACK ISE respectively for free, I tried both of them.
I decided to use WebPACK ISE because I simply hated MAX+PLUS-II's
outdated looking GUI, and Altera's offering didn't come with a free
HDL-based simulator (Xilinx did let me use ModelSim XE-Starter for
free.).
In retrospect, that was a good decision because I found a company
(Insight Electronics) that sold a low cost PCI prototype board for only
$145, whereas Altera FLEX10KE PCI prototype from Altera cost $2,000 . .
.
> I use ISE's GUI also. It really is more of a shell over a bunch of
> command lines tools rather than a real GUI. None of the tools can talk
> to each other. For example, in Maxplus when you get an error, you
> click on it and it takes you to the source file and shows you the
> location of the problem. ISE shows an error. If you click on that
> error, most of the time nothing happens. If it does show you
> something, it is usually in an intermediate file. For example, you
> have an error in the schematic and ISE shows you the VHDL file that it
> made from the schematic. It then points to a net with a Xilinx
> generated name. It is up to the user to hunt around in the schematic
> and find the problem.
I am fine with the way ISE reports errors, and I personally
don't mind looking around for them.
I personally really hate MAX+PLUS II because the GUI looks so outdated.
> Chipview is just a quick and dirty editor that edits the UCF file.
> Even if you manually edit the UCF file by clicking on Edit UCF you end
> up with the same problem.
>
I don't deal with CPLDs, so I don't personally know much about
Chipview, but nonetheless I put all the pin information within a .UCF
file, and I don't have any problems with that.
> The same problem happens whether you start from the ISE or start it by
> itself. The splash screen starts up and the program terminates. Altera
> has its simulator integrated into the program. If there is an error
> (even a licensing issue, it tells you. You then click on the error and
> it takes you to the source of the problem.
One of the reason I turned down using MAX+PLUS II-BASELINE was
because I did not want to do simulation with a waveform simulator
because it takes so much time entering the stimulus.
Perhaps your project wasn't too big that you can get way without using
an HDL-based simulator.
> Again, I use Altera MaxPlus so I can't comment on Quartus's
> shortcomings.
Fine, but I must say MAX+PLUS II is far worst than Quartus II
when it comes to the usefulness of their floorplanner and timing
analyzer.
Also, Quartus II doesn't crash as often as MAX+PLUS II (The Quartus II
fitter is a lot more stable than MAX+PLUS II's fitter.).
> I just ran ISE 5.1 to get a fit for a design. Because it could not
> route (even though I was only using about 55% of the resources), I set
> it to run in "Exhastive Fit" mode where it keeps trying to get a fit.
> After running for 2 hours and not finding a fit, it stopped because
> it had used all of Windows virtual memory. This is on a Windows 2K
> system with with 512 Mb of RAM. The program obviously has a memory
> leak where it eats memory on every fit attempt.
>
I don't deal with CPLDs, so I cannot really comment on your
problem, but the virtual memory leak sounds like the tool's bug to me.
You may want to try ISE WebPACK 4.1 or 4.2 instead.
> Where is Xilinx's floorplanner for CPLD designs? The Altera tools work
> accross PLD's, CPLDs, FPGA's with the same consistant toolset.
I believe ISE's floorplanner is for their FPGAs only.
> MaxPlus has a floorplanner that shows routing.
Really?
I will guess that when you say MAX+PLUS II has a floorplanner that shows
chip's routing, you probably mean that the floorplanner shows the
simplified version of the connection between a LUT and a LUT or between
a PLA and a PLA.
Xilinx's FPGA Editor lets you see which routing line connects to which
pass transistor, and I don't believe Altera even offers such a low level
tool.
However, I am a poor ISE WebPACK user, so I cannot use FPGA Editor (It's
for paid versions only.).
Regardless, Altera's floorplanner is far inferior than Xilinx because it
doesn't show whether or not a LUT or a FF is actually being used
graphically (Yes, the Altera's floorplanner shows the LUT equation which
is nice, but that's not enough to overcome its shortcomings.), and the
fitter often duplicates the LUT the user hand placed automatically.
As far as I know, there is no way to disable the automatic duplication
of LUTs.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 48101
For some reason, Mailgate.org was down for about 5 days.
The postings I made right after Mailgate.org resumed the service didn't
seem to make it to the newsgroup, but more recent ones did finally show
up at Google's newsgroup search engine.
So, I guess Mailgate.org working OK now.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Speedy Zero Two wrote:
>
> yep,
> I made a similar observation several months ago but never did rectify it !!!
>
> Dave
Article: 48102There is an interesting discussion on Verilog vs VHDL going on on the comp.arch.verilog. Any comp.arch.fpga user group opinions about the above topic :) ? I am a big Verilog fun myself and did all my FPGA's in VerilogArticle: 48103
Nothing to say about it except that Verilog rules. It takes 1/3 the typing to get stuff done, and it's more intuitive and easier to read. VHDL looks clunky, whereas Verilog looks like C. Oh, but you are not trying to start a war, here, are you? : ) BB ============================================ "Dmitry Zarubin" <dmitry_zarubin@yahoo.com> wrote in message news:93603cec.0210101918.775beda3@posting.google.com... > There is an interesting discussion on Verilog vs VHDL going on on the > comp.arch.verilog. > > Any comp.arch.fpga user group opinions about the above topic :) ? > > I am a big Verilog fun myself and did all my FPGA's in VerilogArticle: 48104
> Imagine have your C code >chopped up with no regard for your subroutines and then randomly moved >around till its "pretty close to what you want." Works well in some cases. :) Run the code, sample the PC, move things around to avoid cache conflicts and/or cache polution by unused code. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48105
Hi, Here i am working in xilinx's 4.1i. But how can i know, which service pack i am using now? This will be helpful for tracking the xilinx answer records. Thanks and Regards, MuthuArticle: 48106
Sure: First standard cell- In this type of chip, you're building your circuit from chuncks on the level of flip-flop, 2 input and gate, 5 input or gate, etc. Each different chunck is the same (standard) height, but can be a different width depending on the number of transistors it took to make it. The chuncks (cell) are layed out in rows on the die, think about the Scrabble pieces on the little holder they give you. You may mix in whatever memory is available from your foundary and fill the cells in around them gate array- This is less customized than standard cell. In this type of design, the gates and memories are already layed out on the die, what you get to configure is the interconnect layers on top of the gates on the die. Cheaper and faster to produce in low quantities than a standard cell part because presumably the foundary has already pre-fabbed the wafers with gates and held at "metal" waiting for your design to come in. Lower performance than standard cell because you don't always have the exact cell you wanted so you end up building your function from smaller gates. I don't hear that much about gate arrays these days. Hope this helps! Regards "skillwood" <skillwood@hotmail.com> wrote in message news:<ao115k$ghqdk$1@ID-159866.news.dfncis.de>... > HI all, > > I am familiar with VHDL . > > I found the following terms in the syllabus of a VLSI training School > > 1)standard cell based design > 2)Gate array based design. > > Can somebody explain what are these ??Article: 48107
I don't think an LCELL is going to do what you want, those are used to force seperation of logic that may have been minimized. Also its a bad habit to get into to instantiate cells in your HDL, its non portable and hard to read. I've been able to save some cells by making sure that the EDIF importation configuration is using the dedicated carry logic that your negations are using. I got the feeling the tool default was set up to optionally use them to make the fitting easier, but it costs cells. Another important lesson here is the development efficiency that a high level language affords. It saves you from having to worry about where that extra and gate came from. If you're that close to what you expected, you're done, have a beer, then get started on your next project. Maybe since you're just getting started you can track it down, but in the future, your time will generally be more valuable than a few % of lcells. Dirty trick: if you can live with a 1 LSB offset in your output, just do a 1's compliment, and you'll gain a lot of cycle speed. Peter de Vries <devriesp@skynet.ca> wrote in message news:<vFMo9.7820$9f2.757909@news20.bellglobal.com>... > Greetings all. > > I'm wondering if some of the experts out there can shed some light on > this. I am a student working with Altera MaxPlus2 on Flex10K devices. > I am trying to minimize a simple project of mine to the lowest number of > logic units possible. The project is basically a simple combinatorial > which negates (2s complement) a number if a control line is high. > > I am down to 52 logical units for this design.. but on paper I think > that 46/47 LU's are possible. From the report file it looks like MP2 is > not creating exactly what I envision to be the most optimal solution. > Since the design is so simple.. I am thinking this LCELL primitive might > be useful. From what I understand it allows you to manually specify the > configuration of cells. There are very few concrete examples available > on how LCELL is used within VHDL. Does anyone have a pointer to some > worked out examples or guidance on this problem? > > Any help would be greatly appreciated. > > Peter de VriesArticle: 48108
On Thu, 10 Oct 2002 09:06:24 -0700, "Barry Brown" <barry_brown@agilent.com> wrote: >At least with Synplify, initialization values seem to be retained in >synthesis. The following code works: This applies for signals *without* drivers, as in simulation they hold their initial value. For signals *with* drivers (i.e. they appear on the left hand side of an assignment statement somewhere) the initial values will be ignored by synthesis tools, and the tool should issue a warning if an initial value is used in the code. At least, that's what's supposed to happen. YMMV. Regards, Allan. >---------------------------------------------------------------------------- >----------- >architecture rtl of Fifo is > > signal Logic0 : std_logic := '0'; > signal Logic1 : std_logic := '1'; > > >begin > > bram_gen: > for i in 0 to 7 generate > bram: RAMB4_S4_S4 port map ( > ADDRA => ReadAddr, > ADDRB => WriteAddr, > DIB => WriteData(4*i+3 downto 4*i), > DIA => Logic0Bus, > WEA => Logic0, > WEB => WriteEnable, > CLKA => Clock, > CLKB => Clock, > RSTA => Logic0, > RSTB => Logic0, > ENA => Logic1, > ENB => Logic1, > DOA => ReadData(4*i+3 downto 4*i), > DOB => open > ); > end generate bram_gen; >--------------------------------------------------------------------------- > >Barry Brown > >"Ulises Hernandez" <ulises@britain.agilent.com> wrote in message >news:1034261597.151867@cswreg.cos.agilent.com... >> Hi Ken, >> >> The initialisation value assigned to a signal when it is defined (signal >> global_rst: std_logic;) is ignored during synthesis. >> It's valid for simulation only and most of today's synthesis tools will >flag >> that as a WARNING and just ignore it. >> >> Regards >> >> -- >> Ulises Hernandez >> Design Engineer >> ECS Technology Limited >> ulisesh@ecs-tech.com >> >> >> "Ken Mac" <aeu96186@yahoo.co.uk> wrote in message >> news:ao3uc8$gb1$1@dennis.cc.strath.ac.uk... >> > >> > Hello, >> > >> > Hopefully an easy question: >> > >> > If I have a single bit signal that is initialised to either 0 or 1 such >> as: >> > >> > signal INIT : std_logic := '1'; >> > >> > how exactly is this initialised into a slice? >> > >> > I assume it ends up as the output of one of the flip-flops but is it set >> > directly into the RAM cell of the flip-flop by the bitstream or does it >go >> > into the LUT and is then clocked into the flip-flop - or is it set by so >me >> > other means? >> > >> > I had a look on google groups and found some posts but they don't seem >to >> > describe how the value is actually set from the bitstream. >> > >> > Thanks for your time. >> > >> > Ken >> > >> > >> >> > >Article: 48109
>I am an independent consultant developing FPGAs and PLDs using both >Xilinx and Altera development software. ... >The Altera tools are such a pleasure to use. The tools are very well >integrated into a single Windows program. ... >The Xilinx toolset is a hodgepodge of command line tools with a lousy >user interface on top of it. ... Sounds like you are doing one person sized projects and that you like GUIs. GUIs are good for things you only do a few times. They are horrible if you need to keep track of all the fine print (flag/option settings) and/or want somebody else (on a different machine) to be able to reproduce your work exactly. As FPGA designs become more complicated, the problem is changing from hardware/schematics to software/simulation. Hopefully the FPGA tool builders will learn/steal from the software community rather than reinventing too many wheels. I think the key step that most non-tiny software projects need is to be able to recreate a set of output bits from a specified version of the input files. That means you need to identify all the input files and record the recipe for a sequence of commands (with their flags and parameters) [or the GUI interactions] that are needed to make the output files. Most software projects use some form of source control setup to keep track of versions of the source files. If you have something like that then it is often reasonable to use something like make to hold the recipe in a file called "makefile". My main gripe about the Xilinx software is that the documentation needed to do make style (aka command line) work flow was hard to find/understand. I could find the info on each indivdual command but I missed the big picture. What I wanted was a flow-chart style diagram with something like boxes for files, circles for commands, and diamonds/branches for checking the status of the previous command. A sample makefile would be great too - or two, one for a tiny project and one for a large sample. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48110
On 10 Oct 2002 22:04:59 -0700, kayrock66@yahoo.com (Jay) wrote: > < snip > > I don't hear that much about gate arrays these days. > Don't say that aound Xilinx and Altera! Just because they're not -hard- gate arrays.....Article: 48111
Hi, This is what I do. Run Project Navigator (or Design Manager or FPGA Editor...or any of the applications) go to 'Help' and then 'About the Project Navigator'. It pops up a window with all the necessary information, something llike 'Release Version 4.1.03i' (Service Pack 3) and so on 4.1.02i for SP 2... I hope it helps. Regards -- Ulises Hernandez Design Engineer ECS Technology Limited ulisesh@ecs-tech.com "Muthu" <muthu_nano@yahoo.co.in> wrote in message news:28c66cd3.0210102041.4e2a738c@posting.google.com... > Hi, > > Here i am working in xilinx's 4.1i. But how can i know, which service > pack i am using now? This will be helpful for tracking the xilinx > answer records. > > Thanks and Regards, > MuthuArticle: 48112
hmurray@suespammers.org (Hal Murray) writes: > GUIs are good for things you only do a few times. They are horrible > if you need to keep track of all the fine print (flag/option settings) > and/or want somebody else (on a different machine) to be able to > reproduce your work exactly. Hal, we're probably from the same planet, even though I'm probably a little closer to the North Pole :-) > My main gripe about the Xilinx software is that the documentation > needed to do make style (aka command line) work flow was hard > to find/understand. I could find the info on each indivdual > command but I missed the big picture. What I wanted was a > flow-chart style diagram with something like boxes for files, > circles for commands, and diamonds/branches for checking the I found a flowchart on page 2-4 of http://support.xilinx.com/support/sw_manuals/3_1i/download/dev_ref.zip This together with a description of all the different programs was fairly easy to incorporate into script to run partgen, ngdbuild, map, par, trce, bitgen, promgen, ngdanno, and ngd2ver. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48113
Falk, Thanks - I think I may need to provide a reset during operation however - I will bear the ROCBUF in mind though - your message has been saved off! Ken "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:ao49hd$iq965$4@ID-84877.news.dfncis.de... > "Ken Mac" <aeu96186@yahoo.co.uk> schrieb im Newsbeitrag > news:ao45re$i5q$1@dennis.cc.strath.ac.uk... > > > > Ok - I'd better do a bit of a rethink and use a RESET signal in that case! > > If you need this reset only for a controlled power up reset (no reset during > operation), you should use a ROC buffer, which delivers a Reset On > Configuration. > Have a look at the documentation about ROCBUF. > -- > MfG > Falk > > > >Article: 48114
Ray,
I don't instantiate flip-flops but I do infer a lot of them - how do I tell
if the global reset sets an inferred flip-flop? Do I have to make this
happen or is it inferred from a coding style?
On the general topic of signal initialisation - I think my best option is to
add a RESET signal to my entity and have a process something like this:
SignalInit : process (CLK)
begin
if (rising_edge(CLK)) then
if (RESET = '1') then
signalblah <= '1';
signalblah2 <= "1010";
// etc
end if;
end if;
end process;
I think Synplify will warn me that RESET is not in the sensitivity list of
the process but will it make any difference to the synthesis/mapping results
if RESET is in the list or not?
If the process is synchronous to the rising edge of CLK, why would it matter
what RESET is doing if nothing happens unless there is a rising clock edge?
Surely, all that ever need be in the sensitivity list is CLK for synchronous
designs?
Thanks for your time,
Ken
> You can indeed put an initialization on the flip-flops. Synplicity will
> automatically put the attribute on the inferred flip-flop if the global
reset
> sets that flip-flop. If you instantiate flip-flops, the FDSE, FDS types
will
> default to initial 1, others to '0'. You can change that by adding an
INIT=
> attribute:
> attribute INIT of FF0: label is "S"; to set, or
> attribute INIT of FF0: label is "R"; to clear
> these attach the appropriate attribute string tothe flip-flop primitive in
the
> edif file. To make simulation match the hardware, you also need to
set/reset the
> INIT generic to match.
Article: 48115"Dmitry Zarubin" <dmitry_zarubin@yahoo.com> wrote in message news:93603cec.0210101918.775beda3@posting.google.com... > There is an interesting discussion on Verilog vs VHDL going on on the > comp.arch.verilog. > > Any comp.arch.fpga user group opinions about the above topic :) ? > > I am a big Verilog fun myself and did all my FPGA's in Verilog This is a type of question that, in my opinion, has no definitive answer. As in the software world, selecting a programming language over another is not a black/white decision. You find strong points in Both VHDL and Verilog that is not present in the other one. For example, being a designer mostly involved in DSP application in FPGAs, I tend to heavily use the mixture of signed and unsigned calculations inside a module. For this type of applications, so far, VHDL has been much simpler and synthesizers happily accept such a code and produce decent results. But in Verilog, well, it's not an easy task... But the good point here is that today, mixed language support is present in both synthesize and simulation tools and this gives us a unique opportunity to mix VHDL and Verilog code inside a single design, using each one of them to find the most efficient way to describe each single module. Personally, yet I continue to use VHDL most of the time because of it's type system that sometimes let's me to program in a "higher" level of abstraction and also create beasts that would both simulate and synthesize very well. Yet, in some occasions I use verilog to describe certain parts of my designs as I find it easier to do it for those certain tasks easier. The moral of the story is, as a designer I feel free to use anything that would help me do my job easier. If VHDL does it, then I use it. If Verilog does it, then I use it. And I feel no obligation to keep my toolset the same for all my designs.... use what you find best suit your application and always be open to learn new things.Article: 48116
"Blackie Beard" <BlackBeard@FearlessImmortalWretch.com> writes: > Nothing to say about it except that Verilog rules. It takes 1/3 > the typing to get stuff done, and it's more intuitive and easier > to read. Use vhdl-mode for emacs and you only end up typing the things that really need it, which is probably about the same amount as in verilog... > VHDL looks clunky, whereas Verilog looks like C. ... or Verilog looks clunk, whereas VHDL looks like ADA :-) > Oh, but you are not trying to start a war, here, are you? > As if that could ever happen! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 48117
Petter Gustad <newsmailcomp3@gustad.com> writes: > Colin Marquardt <c.marquardt@alcatel.de> writes: [..snip..] > > My guess is that it sets an X property like "override redirect" on > > the main window which would make it stay on top like you describe > > (but "override redirect" would also bring it out of reach of the > > window manager AIUI). If you don't get an answer form Altera, I'd > > try asking on comp.windows.x. > > Good suggestion. I'll try some other window manager first to see if I > can get any clues from that first. I tried the Motif window manager (mwm) and it does *not* result in the odd behavior as in fvwm2. So this appears to be a problem related to the Quartus/fvwm2 combination. I'll see if I can find some fvwm2 related mailing list or something... Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48118
One can also use the program.his or fe.log files out of the gui to
reconstruct the command sequence and exact switch settings.
Petter Gustad wrote:
> hmurray@suespammers.org (Hal Murray) writes:
>
> > GUIs are good for things you only do a few times. They are horrible
> > if you need to keep track of all the fine print (flag/option settings)
> > and/or want somebody else (on a different machine) to be able to
> > reproduce your work exactly.
>
> Hal, we're probably from the same planet, even though I'm probably a
> little closer to the North Pole :-)
>
> > My main gripe about the Xilinx software is that the documentation
> > needed to do make style (aka command line) work flow was hard
> > to find/understand. I could find the info on each indivdual
> > command but I missed the big picture. What I wanted was a
> > flow-chart style diagram with something like boxes for files,
> > circles for commands, and diamonds/branches for checking the
>
> I found a flowchart on page 2-4 of
>
> http://support.xilinx.com/support/sw_manuals/3_1i/download/dev_ref.zip
>
> This together with a description of all the different programs was
> fairly easy to incorporate into script to run partgen, ngdbuild, map,
> par, trce, bitgen, promgen, ngdanno, and ngd2ver.
>
> Petter
> --
> ________________________________________________________________________
> Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48119Thanks!Article: 48120
Petter Gustad <newsmailcomp3@gustad.com> wrote: > I don't know, but I would guess no. However, you can get the ARM core > used in the XScale from ARM (www.arm.com). Altera provides an FPGA > with an embedded ARM core, namely the Excalibur. > > Petter > Intel has put a lot of supporting devices around the core and > enhanced the architecture, but the ISA is the same. Actually, XScale is Intel's own IP. Intel created the XScale core via clean-room approach, licensing only the instruction set from ARM Ltd. The Intel StrongARM processor, on the other hand, uses an ARM core developed by ARM Ltd. Take care, -Chris -- /> Christopher Cole <\ <\ << Cole Design and Development \\ email: cole@coledd.com \\ \\ Computer Networking & Embedded Electronics \\ web: http://coledd.com >> \> \> </Article: 48121
Thanks for reading this. I am simming a virtex 2 design and I am having trouble locating some of my register outputs. The design is a schematic with VHDL modules. I have no problem finding components I "name" in schematic format. The problem is what dies the output of a register written in VHDL look like eg: signal data_reg : std_logic_vector (3 downto 0); process blah... begin if (clk'event and clk = '1') then data_reg <= "1010"; what will the signal name for the input(s), output(s) , clock and enable(if used) be? Thanks for any input.Article: 48122
On Fri, 11 Oct 2002 13:58:40 GMT, Christopher Cole wrote:
>Petter Gustad wrote:
>> Intel has put a lot of supporting devices around the core and
>> enhanced the architecture, but the ISA is the same.
>
>Actually, XScale is Intel's own IP. Intel created the XScale core via
>clean-room approach, licensing only the instruction set from ARM Ltd.
>The Intel StrongARM processor, on the other hand, uses an ARM core
>developed by ARM Ltd.
Close. Intel got the StrongARM in the collapse of DEC.
A lot of the same DEC team that designed the Alpha designed the
StrongARM, and yes, they licensed key patents covering the
instruction set from ARM Ltd.
There is a nice techical 23-page write-up of the original StrongARM
design, title "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor", by
James Montanaro et al. See IEEE Journal of Solid-State Circuts, volume
31, number 11, November 1996, pages 1703-1714. I found a copy floating
around the web somewhere that says "Updated: 27 August 1997".
- Larry
Article: 48123Christopher Cole <cole@scoob.coledd.com> wrote: > > Actually, XScale is Intel's own IP. Intel created the XScale core via > clean-room approach, licensing only the instruction set from ARM Ltd. > The Intel StrongARM processor, on the other hand, uses an ARM core > developed by ARM Ltd. The part about Intel's XScale is correct, but the StrongARM part is wrong. The SA was developed by *DEC* basically ground-up, with some assistance from ARM(for a few misc. items). DEC had to license the instruction set from ARM but the implementation was certainly their own. When Intel acquired (stole?) the StrongARM division, they had to re-negociate licenses with ARM. SA supports the ARM v4 ISA, but doesn't use any "cores" or other licensable IP from ARM. Interestingly enough, the SA-1110 (basically the SA-1100. circa 1996-7), in a .35um process with "high" core voltages is still the premiere SOC. If you think XScale competes, look at the PXA250 errata and barf...no write back cache? What an innovation for a processor made in the year 2002.. S2.Article: 48124
In article <b2pp9.2246$Im6.162311300@newssvr21.news.prodigy.com>, Steve Casselman <sc_nospam@vcc.com> wrote: >This is not a clear picture of what it is all about. By understanding the >bit level you can do some very interesting things. You can an algorithm and >design it so that when given the data you produce a design just for that >data. This is the way to be ASICs. For example there is a DES paper done in >JBits where you take the key and generate a DES design just for that key. >Sure an ASIC could use the same techniques but who wants to buy a chip that >can only encode/decode with one key? Probably IDEA, not DES, as IDEA is the one which really benefits from specialization (turns 16x16->32 multiplies into multiplies by constant). And this is only suitable when you unroll the whole encryption pipeline anyway, which costs a fair amount of area. AES wins effectively nothing from specialization (removes 128 xors/round and the space used to store whateever subkeys, when you can easily do AES fully key agile) I always like specialization, but I've never been able to think of too much use for it beyond cases where you can strenght reduce a multiply/divide or radically shrink a bitwidth. > The only reason we are still using (say it with me) sucky simulated > annealing is everyone treats FPGAs like ASICs and not like > CPUs. Imagine have your C code chopped up with no regard for your > subroutines and then randomly moved around till its "pretty close to > what you want." It is historically hysterical. Some day it will be > different. I more blame the synthesis tools, as a synthesis tool's produced datapath shouln't care about the placer at all, because everything should be nicely locked down. But everyone's heard this rant already. > I'm also working on tools that let you manipulate the bit stream and > they work with the V1 and V2 parts. You should be able to give a > name to some LUT or flop and change it from a command line and have > the software generate a partial packet and down load the change > live. I'll have that working in a few weeks. Nifty. -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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