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"Muthu" <muthu_nano@yahoo.co.in> wrote in message news:28c66cd3.0210072023.605b244c@posting.google.com... > "xtalca" <xtalca@hotmail.com> wrote in message news:<anrbht$gp6u2$1@ID-159866.news.dfncis.de>... > > hi all, > > all ic manufacturers says that there IC is made of some .13 micron or .18 > > micron technology. what exactly this dimension correspond to ? > > Hi, > > Actually this is the size of a transitor in that IC ? Since all > circuits is build using the transistors, the transistor size will > decide about the packing densitiy and the size of the chip. No, it's the length (or effective size, or drawn size, or whatever) of the gate of a transistor. The transistor also needs a drain and a source, and contacts to all of them. The length of a transistor is thus significantly larger than the gate length, usually in both dimensions. Everything scales [roughly] with the gate length, though, so the overall length of one side of a [digital] chip in a given process is [generally] proportional to the gate length. Not always, YMMV, yada, yada, yada. -- Mike --Article: 48176
> >Thanks! > > www.fpga-faq.com > I think http://vhdl.org/comp.lang.vhdl/ is better choice:)Article: 48177
I have to disagree with you. The VHDL FAQ mentions FPGAs but only in the context of VHDL and simulation. There are a lot of FPGA issues that have nothing to do VHDL. www.fpga-faq.com addresses the issues of programming and using FPGAs for example relative placement as well as common tool problems. Steve "Jan Pech" <j.pech@noSPAMieee.org> wrote in message news:aoa59s$pnl$1@ns.felk.cvut.cz... > > >Thanks! > > > > www.fpga-faq.com > > > > I think http://vhdl.org/comp.lang.vhdl/ is better choice:) > >Article: 48178
"Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> writes: > However, in the $QUARTUS/adm/qenv.csh file that is invoked by the > $QUARTUS/bin/quartus script, this variable is always removed from the > environment. > > Thus, what I suggest to get rid of your problem is to change the line in > $QUARTUS/adm/qenv.csh that says > > unsetenv MWWM > > to say > > setenv MWWM ALLWM Thank you Ben, that did it! Actually somebody (DS) suggested to set MWWM til ALLWM, but if Quartus will start a csh and unset it won't help much to set it in my parent bash shell. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48179
Hi Kevin Much thanks for your extensive reply. Sorry that I didn't describe so precisely my FSM sequencer, that you had to think about many possibilities causing my problems.I had PCI LB specification rev 2.1, and I've tried carefully carry about all specifications. My FSM have got B_Busy state and support Burst Read&Write but haven't got Disconect With/Without Data yet(and probably never would have). It turned out that the condition to change between Idle and B_Busy wasn't full enough. I'd been decoding AD(10..0) , CBE, IDSEL and FRAME# lines but I didn't write condition which detect change FRAME# from 1 to 0 ( only I detected low state on FRAME# line).I was sure that IDSEL could be only asserted when FRAME# goes low, at the beginning of new transaction on addres phase, was it? I thought that detecting falling edge of FRAME# is obligatory on all others transactions except Configuration Access,(signal IDSEL high for me was enough) Visibly I was wrong,becouse that additional condition cause that my card doesn't do any conflicts. Perhaps TV card or LAN which are additionaly Masters, had done some actions which require to detect falling edge of FRAME# by my card(but I haven't seen that actions in PCI Specification) Lucky now that problem's gone:) Your post give my attention to many problems which earlier I haven't take so seriously. Until now I haven't seriously take care about timing parameters, especially Tval, which in my PCI core is about 15ns(in Post P&R simulation). Could you explain me more precisely using FFs(Flip-Flops??) with Clock Enable to get right Tval? In my project synthesis generate latches for AD signals with direction from card to PCI, and after them there are Tri-State IOBUFT_PCI33_5. What do you think about it? As I said in previous post I'm not experinced in programmable logic, I had only few xilinx .pdf (one about webpack4(for beginers) and spartan2 documentation) and two books about writting in VHDL read yet. I've got another questions for you.Signals SERR# and INTx# are o/d(open drain).Could you tell me if I can use OBUFT_PCI33_5 to drive them?? I haven't seen output that type yet. And last thing, when software wants to do Memory Read Access, but my card "knows" that for many clocks it couldn't establish transaction,because it's busy(in high speed writting samples from analog/digital converter to SRAM memory).Is good way then ignore initiator and don't assert DEVSEL# & TRDY# although that addres&command is right? Memory Access C++ functions, which I'm going to use in my software, returns some value when transaction was failed or didn't established. Many thanks Kevin, Regards LeszekArticle: 48180
Hi all, I just wondering what is the main purpose of polisilicon in ASIC development. I still not clear on this issues. Basicly, it provides a mask to cover the silicon substrate to spray another layer of resist. Thanks Duy K DoArticle: 48181
VHDL has tons of inconsistencies. (0) component ends with "end component" and package ends with package name. (1) in the following the first <= test for equalities , the second is an assignment if a <= 2 then a <= 2; (2) VHDL goes all of its way to forbid you from assigning std_logic_vector to unsigned, but then provides a zillion helper functions to let you do it Martin Thompson <martin.j.thompson@trw.com> wrote in message news:<uzntl9tiz.fsf@trw.com>... > "Blackie Beard" <BlackBeard@FearlessImmortalWretch.com> writes: > > > Nothing to say about it except that Verilog rules. It takes 1/3 > > the typing to get stuff done, and it's more intuitive and easier > > to read. > > Use vhdl-mode for emacs and you only end up typing the things that > really need it, which is probably about the same amount as in verilog... > > > VHDL looks clunky, whereas Verilog looks like C. > > ... or Verilog looks clunk, whereas VHDL looks like ADA :-) What do you expect, it comes from the same folks that invented that sick language. > > > Oh, but you are not trying to start a war, here, are you? > > > > As if that could ever happen! > > Cheers, > MartinArticle: 48182
Yes, you're right. But it's (I hope meanwhile) so little information on the www.fpga-faq.com today that I usually have to find my answer in the vhdl faq or somewhere else. Jan "Steve Casselman" <sc@vcc.com> wrote in message news:qo1q9.3813$hc6.313909358@newssvr13.news.prodigy.com... > I have to disagree with you. The VHDL FAQ mentions FPGAs but only in the > context of VHDL and simulation. There are a lot of FPGA issues that have > nothing to do VHDL. www.fpga-faq.com addresses the issues of programming and > using FPGAs for example relative placement as well as common tool problems. > > Steve > > > "Jan Pech" <j.pech@noSPAMieee.org> wrote in message > news:aoa59s$pnl$1@ns.felk.cvut.cz... > > > >Thanks! > > > > > > www.fpga-faq.com > > > > > > > I think http://vhdl.org/comp.lang.vhdl/ is better choice:) > > > > > >Article: 48183
Hello, I have designed a hard macro (a CLB slice) with the FPGA editor from Xilinx foundation. The problem is that when I instantiate this macro in my VHDL code and synthesize/implements the code, the input pins to the CLB slice LUTs are swapped. Normally, this would not be a problem, because the LUT contents are also changed. But I need to be able to change the LUT contents with special made software after the bitfile is generated, something that gets impossible if I can't predict how the inputs to the LUTs are connected. Was this question understandable? Does some of you know if it is possible to stop the xilinx tools from swapping these LUT input pins? AsbjørnArticle: 48184
Hi, Does anyone has a Xilinx Virtex II?? I want to create new peripherals for my board, and wants to look at some examples first so that I can understand more. Xilinx has some basic peripheral given to you. However the .vhdl file that they give can't be read. I think they don't want user to see it. Does anyone have any solution to this? Greatly appiciated, TimArticle: 48185
Q: What is the proper notation to use in a Xilinx
*.UCF file, to reference embedded nets?
In the example below, the external signal CLKIN
can have speed constraints set in the UCF thus:
NET clkin PERIOD = 50ns ;
How do I write such a constraint for the net CLK,
which doesn't exit the design, existing only in
the block TOP and those below?
I have tried constructs such as:
NET clkgen1/clko PERIOD = 50ns ;
and
NET top/clk PERIOD = 50ns ;
Both of these being rejected by the tools.
library ieee ;
use ieee.std_logic_1164.all;
entity TOP is port ( -- Dummy entity: no outputs
CLKIN : in std_logic );
end TOP ;
library ieee ;
use ieee.std_logic_1164.all;
architecture struct of TOP is
signal CLK : std_logic; -- The one I want to constrain
component CLKGEN port ( -- Source of CLK
CLKI : in std_logic;
CLKO : out std_logic );
end component;
component DM port ( -- Dummy consumer of CLK
CLK : in std_logic );
end component;
begin
DM1 : DM port map (
CLK => CLK );
CLKGEN1 : CLKGEN port map (
CLKI => CLKIN,
CLKO => CLK );
end struct;
library ieee ;
use ieee.std_logic_1164.all;
entity CLKGEN is port(
CLKI : in std_logic ;
CLKO : out std_logic );
end CLKGEN;
library unisim;
use unisim.all;
architecture DUMMY of CLKGEN is
component BUFG port (
I : in std_logic;
O : out std_logic );
end component;
begin
CLKBUF : BUFG port map ( -- Global clock driver
I => CLKI,
O => CLKO );
end DUMMY;
-- TIA,
Article: 48186Hi, I want to use lpm libraries in mentor paltform(pldflow). Can anyone help me ? I want to know how to create the lpm library so that my design(vhdl files, created through quartus megawizard, and I want to compile, simulate, synthesize them in mentor platform) can use lpm.lpm_components.all; Sudip Saha sudip.saha@philips.comArticle: 48187
"David R Brooks" <daveb@iinet.net.au> schrieb im Newsbeitrag news:v8liqu8b8ttg1u9911b9brjm06etk210iq@4ax.com... > Q: What is the proper notation to use in a Xilinx > *.UCF file, to reference embedded nets? > > In the example below, the external signal CLKIN > can have speed constraints set in the UCF thus: > NET clkin PERIOD = 50ns ; This is just fine. You problem is you dummy entity. Its really a dummy. Since it has no outputs, everthing is removed during the optimization phases. Make a simple route through (clock in and clock out) and you will see the light. . -- MfG FalkArticle: 48188
In all fairness, your second point (1) can also be said for verilog.
The only differences being, I've never seen the 'if' construct used
without the condition being tested inside of '( )', and in verilog you
don't need to write out the "then". ( ; I just wish that verilog would
let you use { & } instead of begin & end, but they had to make { & }
concatenation operators. Something had to do that, I suppose.
"Will" <wv9557@yahoo.com> wrote in message
news:4a885870.0210122135.412513be@posting.google.com...
> VHDL has tons of inconsistencies.
> (0) component ends with "end component"
> and
> package ends with package name.
>
> (1) in the following the first <= test for equalities , the
> second is an assignment
>
> if a <= 2
> then a <= 2;
>
> (2) VHDL goes all of its way to forbid you from assigning
> std_logic_vector to unsigned, but then provides a zillion
> helper functions to let you do it
>
>
>
>
> Martin Thompson <martin.j.thompson@trw.com> wrote in message
news:<uzntl9tiz.fsf@trw.com>...
> > "Blackie Beard" <BlackBeard@FearlessImmortalWretch.com> writes:
> >
> > > Nothing to say about it except that Verilog rules. It takes 1/3
> > > the typing to get stuff done, and it's more intuitive and easier
> > > to read.
> >
> > Use vhdl-mode for emacs and you only end up typing the things that
> > really need it, which is probably about the same amount as in verilog...
> >
> > > VHDL looks clunky, whereas Verilog looks like C.
> >
> > ... or Verilog looks clunk, whereas VHDL looks like ADA :-)
>
> What do you expect, it comes from the same folks that invented that
> sick language.
>
> >
> > > Oh, but you are not trying to start a war, here, are you?
> > >
> >
> > As if that could ever happen!
> >
> > Cheers,
> > Martin
Article: 48189Take a look at App Note AN204 "Using ModelSim-Altera in a Quartus II Design Flow". http://www.altera.com/literature/an/an204.pdf It covers in detail both Behavioral simulation done prior to synthesis, and Timing simulation, after synthesis and place and route. It goes through the full flow, setting up of libraries etc. The LPM libraries that you need are provided with Quartus II. The App Note describes how you point to the libraries from Modelsim, and their directory location in the installed Quartus II tree. - DS "Sudip Saha" <sudip.saha@philips.com> wrote in message news:ee79955.-1@WebX.sUN8CHnE... > Hi, > > I want to use lpm libraries in mentor paltform(pldflow). > > Can anyone help me ? I want to know how to create the lpm library so that my design(vhdl files, created through quartus megawizard, and I want to compile, simulate, synthesize them in mentor platform) can use lpm.lpm_components.all; > > Sudip Saha > sudip.saha@philips.comArticle: 48190
"Steve Casselman" <sc@vcc.com> writes: > Ok there are 10 of us in the world who want to have Open source tools of > some sort. Hmmm, I know about 5 of them by name. Did not think I knew half the world FPGA developer population :-). > My problem is I want to make a living off of the tools I write. > How do I do this. The way I do it (I am a professional programmer) is to work part time on an paying job (which just to be nice also produces open source stuff) and the rest of the time on my tools. At my last job I had 80% (so 4 days work, 3 days for me). As I was earning way more than I was using (about an 55% part) I deliberately have taken my present job at 40% (2 days work, 5 days for me) with an option to go up to 60% whenever I want (in about 1-2 years). > their stuff got stock but most didn't. Is that viable here? No stock stuff here (Universities don't have stock). > Is there some > model where we can all make money? I am getting on nicely. > I'm sure that 10 part time people could > make place and route tool along with a very good gui. With that manpower sure. > Will people pay for > that kind of tool? Hint: Split the project into small modules with an known row of implementation. Find an specific person who wants an specific part (preferably the next or soon next part that needs implementing). Then get them to pay for its development, like as if you were writing normal contract work software. But arrange with them that you can contribute it to the open source collection. For that (it does not add costs to them, but may help their competitior for free) they will most likely want something in return, such as say reduced pay rate for you. > I'm working on tools that Xilinx does not offer like > being able to read, change and update a device while it is in operation. > Being able to do this over a network between different operating systems. Try and find out if someone wants to use that. Offer them to be sponsor for the next development step. > JBits only works for V1 flavors right now and they might pull the rug on it > at any time so I don't think it is wise to depend on it. One reason driving me to get on my own feet. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - hardware runs the world, software controls the hardware code generates the software, have you coded today?Article: 48191
Speaking of FAQs... Does anybody have a list/FAQ on development/prototyping boards for FPGAs? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48192
In article <6ud6qeb21v.fsf@chonsp.franklin.ch>, Neil Franklin <neil@franklin.ch.remove> wrote: >> My problem is I want to make a living off of the tools I write. >> How do I do this. > >The way I do it (I am a professional programmer) is to work part time >on an paying job (which just to be nice also produces open source >stuff) and the rest of the time on my tools. This is not a good way to get a quality tool, but a prototype. Remember Mythical Man Month, one of the early pieces is the observation that making a quality PRODUCT, as opposed to Prototype, is about 9x the effort. So if you assume that you are doing prototypes, you can do so much more interesting things in your time. THis is not to say that I think open source tools targeting commercial FPGAs wouldn't be nifty, they would. But the free-beer tools are already damn good, so I'd rather see people spending their time studying and PROVING what could be done to make the tools better, without having to spend a huge amount of time reingeneering the commercial tools. And for that, you don't need to reimplement the toolflow, just integrate into it. EG, datapath placer: Take EDIF in, recognise the datapth, spit EDIF back out with RLOCs everywhere so that the datapath can't be fucked by Simulated Annealing. There have been academic prototypes along these lines, but it would be really useful to have some nice results for commercial FPGAs, as bludgens to get REAL enhancements into the next version, as now we have a hammer to go to the synthesis vendors and FPGA vendors saying "See, here's this paper, this prototype, how to improve your results by 30% or whatever. You really should do this." >> I'm sure that 10 part time people could >> make place and route tool along with a very good gui. > >With that manpower sure. I disagree. 1-3 can make a good PROTOTYPE, 3-10 can make a very good prototype or fairly crude real tool, but 10 would probably not make a quality tool which could compete with the commercial tools. There are so many nonlinearities in programming manpower and such a gap between prototype and project. Saying right off the bat that you are making a prototype makes life so much easier, and allows you to concentrate on the FUN parts of the problem. >> Will people pay for >> that kind of tool? > >Hint: Split the project into small modules with an known row of >implementation. Find an specific person who wants an specific part >(preferably the next or soon next part that needs implementing). Then >get them to pay for its development, like as if you were writing >normal contract work software. This is really hard, unless you already have a substantial infrastructure in place. >> I'm working on tools that Xilinx does not offer like >> being able to read, change and update a device while it is in operation. >> Being able to do this over a network between different operating systems. > >Try and find out if someone wants to use that. Offer them to be >sponsor for the next development step. So much of that is board specific, on the Virtex parts. (I haven't looked to see if the Virtex 2 parts make it a bit easier). Also, once you start talking network as opposed to internal, I start seeing BIG security flags, as I can see my Evil Twin Binky trying to load corrupted bitfiles. Getting the security right is a tediously large amount of engineering, but uninterseting. IF you are making a product, something USABLE, this engineering is necessary. If you just want to show that it can be done, here is how, this cool technique and nifty prototype, you can ignore all the gross, tedious security engineering. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 48193
I'll give them a try. Transmit a pof, sof,... as binary over the cable ... Rene John_H wrote: > http://www.altera.com/literature/an/an116.pdf > > The key word is "Configuration" or "Configuring." I found this within > four mouse clicks and I've only been hanging out at brand X's site lately. > > Rene Tschaggelar wrote: > >> I found surprisingly little material about programming the FPGA >> myself. The (Altera-) tools pproduce *.pof & *.sof files and >> usually send them through the attached programmer. >> I wasn't able to find a reference about their format or how they >> are going to be sent to the FPGA or its config-chip. >> Only the JTAG interface was described.Article: 48194
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) writes: > In article <6ud6qeb21v.fsf@chonsp.franklin.ch>, > Neil Franklin <neil@franklin.ch.remove> wrote: > > > >The way I do it (I am a professional programmer) is to work part time > >on an paying job (which just to be nice also produces open source > >stuff) and the rest of the time on my tools. > > This is not a good way to get a quality tool, but a prototype. I do not consider my tools to be prototype quality. I intend them for full real-world use. Possibly by not too demanding users. When it comes to FPGAs I am at present a hobbyist. Other users who intend to use my stuff are students, and their teachers. But that said, the tools should be up to at least the standards that professional CPU programming tools had in the 1980s. > So if you assume that you are doing prototypes, you can do so much > more interesting things in your time. I intend to do what is needed that I can produce actual FPGAs, which can be used. > >> I'm sure that 10 part time people could > >> make place and route tool along with a very good gui. > > > >With that manpower sure. > > Saying right off the bat that you are making a prototype makes life so > much easier, and allows you to concentrate on the FUN parts of the > problem. Well I am not making prototypes. I am making what I consider good enough to use. That may be less than you want. But you can allways then add what you regard as missing. It is open source after all, and that grows be accretion of different peoples additions. The problem is the initial "got moving" work. That is what I am presently doing. > >Hint: Split the project into small modules with an known row of > >implementation. Find an specific person who wants an specific part > >(preferably the next or soon next part that needs implementing). Then > >get them to pay for its development, like as if you were writing > >normal contract work software. > > This is really hard, unless you already have a substantial > infrastructure in place. Getting over the "initial hump" is more work. But that is what savings are for. And I do have 4 years of working at 150% of what I use in money behind me. So I could go 2 years at no income. I am actually going at the moment at about 2/3 use, so I have 6 years time. I expect to use 2 of them. So I have time for an factor 3 miss-estimate. > >> I'm working on tools that Xilinx does not offer like > >> being able to read, change and update a device while it is in operation. > >> Being able to do this over a network between different operating systems. > > > >Try and find out if someone wants to use that. Offer them to be > >sponsor for the next development step. > > So much of that is board specific, on the Virtex parts. (I haven't > looked to see if the Virtex 2 parts make it a bit easier). Then implement it for one board, and then later extend to flexible multi board stuff when an second project pays for flexibilising. That is one of the "steps" I referred to. Open source works bottom up. CS top down people may not like that. Millions of Linux users regard it as adequate. > Also, once you start talking network as opposed to internal, I start > seeing BIG security flags, as I can see my Evil Twin Binky trying to > load corrupted bitfiles. Getting the security right is a tediously > large amount of engineering, but uninterseting. Which I solve by running my stuff over an existing network service, such as ssh. So networking inclusive security becomes as simple as using stdin/stdout. That is the Unix way to modularity. And why the FSF for its GNU project selected Unix as its basic design. So that it can be implemented piecemeal by many independant people, at whatever rate and part they want to work on. The result is what today is known as Linux. IBM sells systems with it, to many companies, including Fortune 500, that want to use it. That is my definition of usable. Definitely not prototype. > necessary. If you just want to show that it can be done, here is how, > this cool technique and nifty prototype, you can ignore all the gross, > tedious security engineering. Or let someone else do it for you. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - hardware runs the world, software controls the hardware code generates the software, have you coded today?Article: 48195
Sorry, perhaps I should have been more clear. In the example, it is a dummy entity, to keep things simple. The *real* entity is very far from being a simple pass-through: the hierarchy shown in the example is required. "Falk Brunner" <Falk.Brunner@gmx.de> wrote: :"David R Brooks" <daveb@iinet.net.au> schrieb im Newsbeitrag :news:v8liqu8b8ttg1u9911b9brjm06etk210iq@4ax.com... :> Q: What is the proper notation to use in a Xilinx :> *.UCF file, to reference embedded nets? :> :> In the example below, the external signal CLKIN :> can have speed constraints set in the UCF thus: :> NET clkin PERIOD = 50ns ; : :This is just fine. You problem is you dummy entity. Its really a dummy. :Since it has no outputs, everthing is removed during the optimization :phases. :Make a simple route through (clock in and clock out) and you will see the :light. :.Article: 48196
On Sun, 13 Oct 2002 19:06:38 -0000, hmurray@suespammers.org (Hal Murray) wrote: >Speaking of FAQs... > >Does anybody have a list/FAQ on development/prototyping boards >for FPGAs? I have been accumulating FPGA board links I have gathered at this URL: http://www.dspia.com/fpga-boards.html Hope it helps, Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 48197
Hi Group I have a question regarding the implementation through VHDL flow. My target chip is spartan 2. Question is : How to assign clk through startup while implementation. I want to use manual clock. If I use an external clock . how to interface it to the chip. Pls. Help me if anybody can. --SanjayArticle: 48198
For this case, you are only changing the LUT content and not the routing.
You really have several options, one of which does not even require
reconfiguring the device to reload the LUT.
1) you can put an SRL16 in as a placeholder, then replace it with a LUT
in the reconfiguration. SRL16's (the shift register primitive in virtex
parts) lock the pin assignments, so the mapper is forced to leave them
alone.
2) If you can live with the minor route restrictions an SRL16 imposes
(namely, you can't use the direct set/reset to the flip-flop), you can
also leave the LUT as an SRL16. The SRL16 behaves exactly like a LUT
when the WE pin is held low.
3) If you do use an SRL16, you can replace the LUT contents with new ones
in 16 clocks by bringing the WE pin high and presenting the LUT contents
serially to the D pin. This gives you a capability of reloading 'LUT'
contents without actually reconfiguring the part. It is really handy for
distributed arithmetic filters where the coefficients are programmable
or in some cases for adaptive filters.
4) As I understand it, starting with version 4.1 there is a pin lock
constraint for LUTs similar to the MAP constraint under XACT. I haven't
used it yet, so I can't tell you how well or if it really works. I don't
believe it is in the documentation at all.
My preference is for 3), since it gives you a capability of
reconfiguration that works in the context of the current FPGA
configuration, which means that your simulator can also handle simulating
the configuration, plus you don't have to manage multiple bitstreams.
Option 1, even though you replace the SRL16 with a LUT in the operational
bitstream, still blocks the reset pins on the flip-flops since the
routing is done with an SRL16 there. Option 2 puts the SRL16's in but
disables the shift permanently. Option 3 just adds a small amount of
support logic to allow you to shift in new LUT contents.
The best part is that you don't have to mess with the bitstream at all
(and in fact, you don't even need to know where the LUT is placed).
Asbjørn Djupdal wrote:
> Hello,
>
> I have designed a hard macro (a CLB slice) with the FPGA editor from
> Xilinx foundation.
>
> The problem is that when I instantiate this macro in my VHDL code and
> synthesize/implements the code, the input pins to the CLB slice LUTs
> are swapped.
>
> Normally, this would not be a problem, because the LUT contents are
> also changed. But I need to be able to change the LUT contents with
> special made software after the bitfile is generated, something that
> gets impossible if I can't predict how the inputs to the LUTs are
> connected.
>
> Was this question understandable? Does some of you know if it is
> possible to stop the xilinx tools from swapping these LUT input pins?
>
> Asbjørn
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
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temporary safety deserve neither liberty nor safety."
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Article: 48199Russell wrote: > > rickman wrote: > > However there is *nothing* to adapt to. There are *no* open source > > tools that can be used on a production design. > > Linux and open source are only fairly new, and there's a certain > learning curve before capable developers appear for more specialized > tool development. Also, before jbits, creating open source tools is > completely uninteresting if all it involves is making a pretty front-end. The front end doesn't have to be the *only* part, but it makes sense to me that it should be the *first* part. The backend tool is of no value without a frontend tool. Right now you can get by without an open source backend because you can use the only *good* backend tool available which just happens to be available for free. To start with building the backend tool, you would need a good front end tool. You could use the one from Xilinx, but I hear a lot of complaints about it and that is where a lot of improvements can be made with much less effort. The front end tools have a lot more in common with current compiler technology. Maybe I am wrong, and I am not planning to help with any of this. So if you no playah da game, you no makeah dah rules. So I will butt out. > > You can expect what you want, but that won't make it happen. There are > > very few engineers that are going to start a significant project with > > open source FPGA tools when their company will pay for the commercial > > tools. You make a lot of predictions that won't be tested for 10 years > > or more. > > I would start with an open source tool if there was one at the time. I'd > also be doing bug fixes and adding *useful* features (i'm not quite up > to that level on linux yet). I would submit that you would start with an open source tool not because that would be the best for your project, but because that is what interests you. The engineers that use these tools need to get design work done and don't have time to improve the tools. > > Someone correct me if I am wrong, but Xilinx and Altera have NO $5-digit > > tools (unless you are counting the pennies). The expensive tools are > > the synthesis and simulation tools. These are third party and they > > charge so much because they are so good. > > Leonardo-spectrum GUI good? Most of the other tools could be improved > too. I don't give a rat's ass about the GUI. I care about how well a tool works to give me usable gates. I also have never used Leonardo-spectrum. The tools I have used may have warts, but I could get my work done with them. That is what I care about. > > But this is the first place > > that open-source tools should show up. All the interfaces are defined > > in public standards, the functionality is known, all that is needed is > > the open source code. So where is it??? Where are the open source > > synthesizers and simulators? > > There's no motivation to do it if there's no info available for the > low-level control of most fpgas. It would be like doing open source > development if the only compilers available had to be bought from > microsoft. The opcodes and assembly instructions of microprocessors > are freely released by cpu vendors to encourage tool creation. The > same should apply to fpgas. FPGAs have a short life cycle because > the industry is immature. Process limits will slow this down in a > few years, when open-source will be much more common-place. I don't know what motovates you, but I don't think it is the same as most users of the tools. I would like to stop working with analogies and hear what the game plan is. Can you give us a roadmap of how you would procede? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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