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Since Altera seems to be active in this group, I will ask the question here. I have finally gotten an acceptable price on the EP1K30 part (5 volt tolerant) and will be using it in my design provided I don't step on any landmines looking at the data sheet in fine detail. One item that is missing is the startup current. I called support and got a number of 194 mA. But I asked if this was over temp and voltage and he didn't know. He said he would dig up the answer and get back to me which never happened. So who can tell me the power-up current for the EP1K10, EP1K30, EP1K50 and EP1K100 in both commercial and industrial temp grade over temperature and voltage? Also, I am not certain I understand the quiescent current spec on this part. There are two values, one has a footnote... ICC0 VCC supply current (standby) (12) This parameter applies to -1 speed grade commercial temperature devices and -2 speed grade industrial and extended temperature devices. Does this mean the lower value (5 mA) without the footnote applies to all other devices? Am I correct in assuming that this spec is for a configured part with no clock as well as an unconfigured part? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57676
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F04660E.33F1EF2@yahoo.com... > David Brown wrote: > > > > I fully support the option of being able to buy the CD - even for those of > > us with reliable internet connections, there are times where a single CD in > > the post can be more convenient. And I agree that reliability is the main > > factor for the internet connection - a 57kbaud modem can download 150 MB > > overnight, but only if it is reliable enough! But is it really that hard or > > that expensive to get a solid line? I find it is an essential requirement > > for my work - speed is not critical (we have a 386 kbit ADSL line for the > > office), but reliability is. > > > > Incidently, you might like to try NetAnts for downloading over a dodgy line, > > although I'm sure everyone has there favourite download utility. > > I don't know about my line being "dodgy". I just know that the > combination of ISP, phone line, modem, OS and browser software makes it > hard to get a 17 hour download to complete without error. It is also a > PITA tying up the modem connection for a day while this is going on. It > makes it very slow to browse or even get emails. > > As to the effort required to get a solid data line, there is virtually > *nothing* you can do if your voice capability is not affected. I have > talked to the phone company before and they have made it clear that a > phone line is not a data line. They guarantee no specific data rate. > DSL is not available in the second largest city in Maryland and Cable > Modem is a fixed installation, it can not be easily moved from one > computer to another. Cable Modem also goes out in nearly every storm > along with the TV. > > I only wish I could get connected at 57 kbps! > Can't you use a firewall/router connected to a cable modem? Of course, it won't fix the storm problem, and not every isp's contract will let you connect a whole network to their system. Can you get ISDN there? I have no real idea whether that is available in the US or not - it is popular in Europe for businesses, and used to be common for internet access before ADSL became so widespread. Maybe you can get radio internet connections? Many of these are pretty ropey, but there are some ISP's here in Norway that manage to do it well, so it's certainly possible. Other than that, I can offer nothing but sympathy (and surprise - I knew the US had a problematic telephone system, but I didn't know it was that bad).Article: 57677
This is beautiful ! I had felt like commenting, but it's so much better coming from a user. Thanks, Rickman! We should put our best foot forward, and be as honest as we can. But I will not slam Altera's products. Maybe needle their people... :-) Have a safe Fourth of July ! Peter Alfke rickman wrote: > Marc, > > If you learn nothing else about dealing with IC vendors it should be > that you never, ever, EVER listen to what one vendor says about > another. Feel free to check it out yourself, but you should always > assume that any vendor will put his competition in the worst possible > light, perhaps even unfairly. > > So don't blame a vendor for being a vendor. They all do it. Just learn > to be a discriminating listener. Kinda like when you watch commercials > on TV. :) > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57678
> I very seriously doubt that Xilinx is going to replace the XC2 line. It > is not very old at all. The XPLA3 line is 5 volt tolerant (sort of) and > no new process can replace that. Where did you hear this new line? The FAE told me that the next CR, say CR-III, will be very low voltage again like 1.5 or 1.8. That would certainly not be a replacement for the XPLA3 family since it is 3.3V. It is far more likely it would replace the CR-II family. At least that's what the Xilinx FAE thought. Chris.Article: 57679
Petter Gustad <newsmailcomp5@gustad.com> wrote in message news:<871xx7oevc.fsf@filestore.home.gustad.com>... > Is there a way to generate SVF files in Quartus II? If not, is there a > way to convert JAM files to SVF? > > TIA > > Petter In Quartus II, open the programmer. Click on the File->Create/Update->Create JAM/SVF/ISC.. file. - Subroto Datta Altera Corp.Article: 57680
Jim Granville wrote: > Can we get a quick summary of what's removed, and what >legacy versions of SW are needed to support which family ? > > The current software (version 5.1i, 5.2i, 6.1i) supports Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan II, Spartan IIE, and Spartan-3. ISE Classics (version 4.2i) supports XC4000E, XC4000L, XC4000EX, XC4000XL, XC4000XLA, Spartan, and SpartanXL. Contact the hotline if you need software for: 3.1i supporting XC3000A, XC3000L and XC5200. XACT 6 supporting XC2000, XC3000, and XC4000, XC4000A and XC5200. SteveArticle: 57681
The Xilinx Spartan-3, Virtex-II, and Virtex-II Pro FPGAs have DDR registers as part of each I/O block. For high-performance applications, you would want to use two outputs from the Digital Clock Manager, one being the de-skewed, non-shifted clock output and the de-skewed, 180 degrees phase-shifted clock output. This technique minimizes any potential duty-cycle distortion and gives you most of the entire half-period for your logic application. You might take a look at the following web site as it contains both application notes and sample code. http://www.xilinx.com/xlnx/xil_prodcat_systemsolution.jsp?title=xaw_memory_dram_ddr_page -- --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3 Tel: (408) 626-7447 E-mail: steve.knappNO#SPAM@xilinx.com --------------------------------- "itsme" <itsme@gmx.de> wrote in message news:bdud1q$enh$02$1@news.t-online.com... > Hi all, > here is a quit simple, general question: > Why do the FPGAs (as fare as I know) not use Double Data Rate on Chip for > their FlipFlips? > + This would reduce the power for the clock tree. > + I could directly use the Data from an external DDR-DRAM > > >Article: 57682
In article <gZ0Na.1998$as1.558049332@twister1.starband.net>, Steven K. Knapp <steve.knappNO#SPAM@xilinx.com> wrote: >The Xilinx Spartan-3, Virtex-II, and Virtex-II Pro FPGAs have DDR registers >as part of each I/O block. > >For high-performance applications, you would want to use two outputs from >the Digital Clock Manager, one being the de-skewed, non-shifted clock output >and the de-skewed, 180 degrees phase-shifted clock output. This technique >minimizes any potential duty-cycle distortion and gives you most of the >entire half-period for your logic application. I think the origional poster means the opposite, having the internal registers in teh FPGA trigger on both the rising and falling clock edge, to save power in clock distribution. Unfortunatly, this would require even clock phases in all cases, significantly more complex flip-flops, and I'm guessing the power-savings in the clock distribution (now running at half speed) would be swamped by the additional power draw within the flip-flops themselves to allow them to trigger on both edges. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 57683
sdatta@altera.com (Subroto Datta) writes: > Petter Gustad <newsmailcomp5@gustad.com> wrote in message news:<871xx7oevc.fsf@filestore.home.gustad.com>... > > Is there a way to generate SVF files in Quartus II? If not, is there a > > way to convert JAM files to SVF? > > > > TIA > > > > Petter > > In Quartus II, open the programmer. Click on the > File->Create/Update->Create JAM/SVF/ISC.. file. Thanks! Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 57684
Peter Alfke <peter@xilinx.com> writes: > Old software is available for free, but may require an old computer > OS. What about releasing the source of unsupported tools into the public domain, or as Free Software? Unmaintained binary only software is not a big help, but old source code that one can maintain oneself is a winner. You might also learn a thing or two about the 'Free Software / Open Source community' that way and how it might help you make Xilinx more popular. -- GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3 331E FAF8 226A D5D4 E405Article: 57685
Marius Vollmer <mvo@zagadka.de> wrote: : Peter Alfke <peter@xilinx.com> writes: :> Old software is available for free, but may require an old computer :> OS. : What about releasing the source of unsupported tools into the public : domain, or as Free Software? Unmaintained binary only software is not : a big help, but old source code that one can maintain oneself is a : winner. : You might also learn a thing or two about the 'Free Software / Open : Source community' that way and how it might help you make Xilinx more : popular. To cite the Bible: "Eher geht ein Kamel durch's Nadeloehr, als dass ..." Probably the software is hopelessly interweaved with externelly licensed software and other parts that are still considered crucial. I doubt that there is a big difference between an FPGA suite and Netscape. And look what effort it took to get from Netscape to Mozilla. The audience for a FPGA suite is oders of magnitude smaller. Anyways, such a move would be great... Bye B.t.w.: For mantaining legacy version of windows software, the windows emulator wine (www.winehq.com) might be an option for the not-so-faint-hearted. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57686
Marius Vollmer <mvo@zagadka.de> wrote: : Peter Alfke <peter@xilinx.com> writes: :> Old software is available for free, but may require an old computer :> OS. : What about releasing the source of unsupported tools into the public : domain, or as Free Software? Unmaintained binary only software is not : a big help, but old source code that one can maintain oneself is a : winner. : You might also learn a thing or two about the 'Free Software / Open : Source community' that way and how it might help you make Xilinx more : popular. To cite the Bible: "Eher geht ein Kamel durch's Nadeloehr, als dass ..." Probably the software is hopelessly interweaved with externally licensed software and other parts that are still considered crucial. I doubt that there is a big difference between an FPGA suite and Netscape. And look what effort it took to get from Netscape to Mozilla. The audience for a FPGA suite is orders of magnitude smaller. Anyways, such a move would be great... Bye B.t.w.: For maintaining legacy version of windows software, the windows emulator wine (www.winehq.com) might be an option for the not-so-faint-hearted. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57687
Hi, I'm new to Synopsys Design Compiler. I have some questions: 1. Should I always set drive strength and load driven by the ports before optmization? But I don't know what kind of value i can use and how to get the value? for drive strength and load? 2. Should I always set input_delay and output_delay? In the tutorial manual of Synopsys Design Compilefr, it only set output delay to the Clock? Why don't we need to set input_delay? 3. After I compiled my design, and I found slack time for all end-points are zero? Is this correct? Thanks. LiangArticle: 57688
Too many German quotes. Uwe's was "It is easier for a camel to go through the eye of a needle, than for a rich man to enter into the kingdom of God" New Testament, St. Matthew 19:24 Maybe you remember from Sunday School... Peter A ====================== Uwe Bonnes wrote: > To cite the Bible: > > "Eher geht ein Kamel durch's Nadeloehr, als dass ..." > >Article: 57689
Hi Marc, > I love competitive comparisons, and I love Altera for continuing to > push the level of competition higher, but PLEASE, could you keep this > FUD free? Interesting... I thought my posting was relatively FUD free. Have I have been on the dark side for too long? :-) > Xilinx tells everybody that the speed files that are released for the > Spartan-3 are very preliminary and quite conservative, and I'm sure > your tech people know that. I am a tech person... I assure you that we're the last customer of ISE that Xilinx cares to inform about future performance! The software is the silicon -- it doesn't matter how fast the chip is if you don't know how fast your design will run on it. I would be leary of relying on a nebulous future performance improvement; I think the performance reported *today* is very relevant for people making decisions today. Besides, in postings to this newsgroup at least, Xilinx has indicated that they sacked performance in order to reduce costs. So how conservative is the timing? 5%? 10%? 100%? I don't know. Do you? >This is bordering on the same level of > FUD that I got from my Altera rep about some Virtex II availability or > yield or some such nonsense early this year. Hmm... I'd go listen to some Xilinx conference calls from the same time period, and look at recent dielectric decisions on VIIPro, and look at when products shipped vs. dates indicated in announcements before proclaiming that FUD. > All of these would be better talking points than some nebulous claim of being > 30% faster than a part that is nowhere near released and whose claimed > speed is known to be artificially low. I guess it's not that fair for me to compare a released, available, fully characterized product with a final timing model against a product that is barely sampling. But that is what the original poster was asking for, and that's all I can compare against. And the "nebulous" claim was 20% faster (slowest Cyclone to only Spartan 3 speed grade), or ~55% for the fastest Cyclone speed grade. These are not "up to" numbers -- they are geometric averages over 50+ user designs. Have yourself a great long weekend, Paul Leventis Altera Corp.Article: 57690
Quartus II software version 3.0 is now available on the PC, Solaris, Red Hat Linux, and HP-UX operating systems. Customer CD shipments will be made from July 11 - July 21. The Web Edition is available for download now. Learn about the new features in Quartus II version 3.0 at <http://www.altera.com/products/software/pld/products/q2/whats_new/qts-whatsnew.jsp> For general Quartus II software information visit <http://www.altera.com/products/software/pld/products/q2/qts-index.html> To download the free Quartus II Web Edition software for PCs visit <http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html> - Subroto Datta Altera Corp.Article: 57691
Rick, On your question on startup current - I don't know this offhand but will track this down with the hotline guy, as we don't want to duplicate effort. The other question about quiescent current: Your interpretation is correct. The 5 mA value applies to -2 and -3 commercial-temp devices and -3 industrial/extended-temp devices, while the 10 mA value applies to -1 commercial-temp devices and -2, -3 industrial/extended-temp devices. The spec applies to a configured part with no toggling inputs. We do not have a spec for the unconfigured part. In reality it may be slightly higher, but not much more. Greg Steinke Altera Applications gregs@altera.com rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F047811.D824824C@yahoo.com>... > Since Altera seems to be active in this group, I will ask the question > here. I have finally gotten an acceptable price on the EP1K30 part (5 > volt tolerant) and will be using it in my design provided I don't step > on any landmines looking at the data sheet in fine detail. One item > that is missing is the startup current. I called support and got a > number of 194 mA. But I asked if this was over temp and voltage and he > didn't know. He said he would dig up the answer and get back to me > which never happened. > > So who can tell me the power-up current for the EP1K10, EP1K30, EP1K50 > and EP1K100 in both commercial and industrial temp grade over > temperature and voltage? > > Also, I am not certain I understand the quiescent current spec on this > part. There are two values, one has a footnote... > > ICC0 VCC supply current (standby) > > (12) This parameter applies to -1 speed grade commercial temperature > devices and -2 speed grade industrial and extended temperature devices. > > Does this mean the lower value (5 mA) without the footnote applies to > all other devices? > > Am I correct in assuming that this spec is for a configured part with no > clock as well as an unconfigured part? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57692
Chris_S wrote: <snip> > The Altera people told me that a new CPLD family is coming out soon. It > will be lower power. Sounds like Altera has gotten very sick of hearing > their parts are current hogs. Can they elaborate on the 'out soon', in this industry, that can reach to the end of 2004 :) > Xilinx says that they also have a new CR (2.5V) part coming out, but it will > probably replace the XC2 line, not XPLA3. They say XPLA3 is not going to be > obsolete. This sounds a little mangled, and someone from Xilinx may enlighten us. It may be that the 'new' CoolRunner is the XC2 family ? The XC2 is so new, only the XC2C256 gives web supply hits. Once released, a device will only go obsolete if volumes get too small, or the FAB line closes. The latter happened to Lattice and Xilinx, but only affected design lines they purchased. -jgArticle: 57693
rickman wrote: > > Chris_S wrote: <snip> > The Altera people told me that a new CPLD family is coming out soon. It > > will be lower power. Sounds like Altera has gotten very sick of hearing > > their parts are current hogs. > > Did they give you a schedule by any chance? If they don't have a > schedule then you shouldn't expect it within the year. Oh, yeah, don't > expect it to be 5 volt tolerant. If you only need LVTTL, then you > should be ok, but all newer devices are 5 volt phobic. Not entirely - the new Lattice devices offer 5V tolerance, but they also spec 'no more than 32 IO' at a time. Strange spec, how does one IO 'know' the state of another ?! On some devices the IO tolerance is spec'd also CORE relative, so you can get caught if your IO power is present, and the core voltage is not! Lattice appear to be using on-chip regulators, so the multi-rail dance is showing signs of simplifying. The regulator is a bit 'ordinary', so the Icc goes up on those variants. There are uC being released with regulated core voltages (eg AT89C51ED2) so that is a sensible solution, esp for the smaller CPLD's -jgArticle: 57694
Hello, NRZ (Non-Return to Zero) has only two signalling levels. NRZI is a non-return to zero code where a 0 is represented by a transition in the signal and a 1 is represented by no transition. Note that the NRZ codes are not inherently self clocking, either an external clock or some method of limiting the number of bit intervals with no transitions is needed. See http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?Non+Return+To+Zero Return to Zero (RZ) http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?Return+To+Zero often used bipolar + and - voltages for 1 and 0, returning to zero volts between bits (3 level signalling). Daniel Lang ><guest> wrote in message news:ee7e625.2@WebX.sUN8CHnE... >Dear Falk & Peter, > Thanks for replying, As Iam basic to this information, Please correct me if iam wromg >NRZ coding say it doesn't return to 0v. For transmitting '1' +V is used >and for transmitting '0' -V volt is used. >we have signalling standards like LVTTL, TTL, CMOS they represent '1' as +V and '0' as 0V . >What do i say the chip, which provides the NRZ interface, > 1) Its signalling varies from +v to -v doesn't return to 0V > 2) Or it has used NRZ coding over Some (say CMOS) signalling standard then one is represented by + Vdd and zero is represented by 0V, am I wright..? >3) what is NRZ, is it not an line coding, i.e how to represent the 1 and 0 across the physical link ? >Thanks in AdvanceArticle: 57695
why altera doesn't provid QuartusII Web Edition for Linux? "Subroto Datta" <sdatta@altera.com> wrote in message news:ca4d800d.0307031507.7de6a279@posting.google.com... > Quartus II software version 3.0 is now available on the PC, Solaris, > Red Hat Linux, and HP-UX operating systems. Customer CD shipments will > be made from July 11 - July 21. The Web Edition is available for > download now. > > Learn about the new features in Quartus II version 3.0 at > <http://www.altera.com/products/software/pld/products/q2/whats_new/qts-whats new.jsp> > > For general Quartus II software information visit > <http://www.altera.com/products/software/pld/products/q2/qts-index.html> > > To download the free Quartus II Web Edition software for PCs visit > <http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebma in.html> > > - Subroto Datta > Altera Corp.Article: 57696
Using the Memec MB1000 eval board with the Virtex-2 on it, I tried one of the Memec projects "Lab06_Own_Periph_VirtexII1000". Building this under the EDK 3.2 works fine on eval board. But, if I change line 163 of the file "opb_pwm_core.vhd" which reads: SIn_DBus(I) <= '0'; to SIn_DBus(I) <= '1'; which just changes the default output of the user IP, the system just hangs after downloading the bitstream to the eval board. Any ideas? Could there be some kind of contention within the OPB bus? I assume that contentions are generally caught by the synthesis tools. If I inspect the automatically generated vhdl, it seems that the bus interfaces are generated correctly for the various peripherals tied to the OPB bus. So, I'm at a loss as to why this is happening! Bob -- Direct access to this group with http://web2news.com http://web2news.com/?comp.arch.fpgaArticle: 57697
You mean the warning is a suggestion for the simulation process. and nothing wrong with the model ISE generated. "Sandeep Kulkarni" <sandeep@insight.memec.co.in> 写入消息新闻 :be15fd$27q4$1@ID-199516.news.dfncis.de... > Hello, > The "glbl.v" module connects the global signals to the design, which makes > it necessary to compile this module with the other design files and to load > it along with the "toplevel.v" file or the "testbench.v" file for > simulation. > > You need to compile it in the simulator, with the timing netlist. > > Sandeep > "Jay" <yuhaiwen@hotmail.com> wrote in message > news:be0h4j$117mq8$1@ID-195883.news.dfncis.de... > > in ISE project navigator, when I run the 'generate post-PAR simulation > > model' process, I get a warning below: > > > > WARNING:NetListWriters:108 - In order to compile this verilog file > > successfully, please add $XILINX/verilog/src/glbl.v to your compile > command. > > > > I'm using a GUI software, how can I change its default command line under > > the button? > > > > > >Article: 57698
Really good idea. but it can't cover all the situation, when I want to divide the clock by 4, 8... maybe use glbl.GSR is a common solution. "jetmarc" <jetmarc@hotmail.com> ??????:af3f5bb5.0307021455.6db3d07e@posting.google.com... > > I know the reason. without a reset signal to give it a initial value of '0' > > or '1', the clkout will keep the value 'x' during simulation. > > In VHDL you can write: > > process (clkin) > begin > if rising_edge(clkin) then > if clkout='0' then > clkout <= '1'; > else > clkout <= '0'; > end if; > end if; > end process; > > That works both in the chip, and in the simulator. The trick is that > the ELSE statement covers both '1' and 'x'. > > MarcArticle: 57699
Could someone please let me in on how the Flip Flops work in ISE Webpack schematics. Where is the Q/ . Do I simply run an inverter off from Q or what. Are these also global clk and rst or only if you assign them that way. When running a clock into the chip for a design (say 6mhz) which pin is best to use? Sorry for all the Newbe questions but this stuff is hurting my head.... Man why can't they just use easy software like Palasm :) Thanks, Fred
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