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> I know the reason. without a reset signal to give it a initial value of '0' > or '1', the clkout will keep the value 'x' during simulation. In VHDL you can write: process (clkin) begin if rising_edge(clkin) then if clkout='0' then clkout <= '1'; else clkout <= '0'; end if; end if; end process; That works both in the chip, and in the simulator. The trick is that the ELSE statement covers both '1' and 'x'. MarcArticle: 57601
"Bill" <bconnersprint03@earthlink.net> wrote in message news:7f8da00b.0307021255.5f6d3c79@posting.google.com... > "Leon Heller" <leon_heller@hotmail.com> wrote in message news:<bdv712$oki$1@hercules.btinternet.com>... > > <eholbrook@austin.rr.com> wrote in message > > news:874r24dalp.fsf@vole.holby-net... > > > I'm looking for a DIMM format FPGA board like Pilchard or the AcB from > > > (now defunct?) Nuron. I've done several web searches, but found > > > nothing that both fits the bill, and is from a company that is > > > apparently alive. I've found a couple of things that are close to what > > > i want (from mite.cz, and sunrise-systems.de), but they don't return > > > emails, so i figure they're dead, too. > > > > > > Has anyone heard of something like this, or do i need to design/build > > > it myself? > > > > I was thinking of developing one. How about us collaborating? > > > > Leon > > > From what I hear, SRC Computers holds patents in this area and is not > licensing to anyone right now. > > www.srccomp.com I can't see how one can patent the idea of putting an FPGA on a DIMM. I put a CPLD on a SIMM ages ago. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 57602
Antti, the Linux demo shipping with ML300 comes with X Windows and a ton of servers and applications. If for some reason your board came with just a very simple command line version of Linux you can get the full MicroDrive image from the ML300 lounge accessible from http://www.xilinx.com/ml300. If you want to start your own development with Linux on Virtex-II Pro please contact MontaVista and ask them for MontaVista Linux 3.0 for ML300. They will be able to give you more information on the content and the pricing of their product. V2PDK is still supported by Xilinx. However, it is in the process of being replaced with EDK. The V2PDK design for the ML300 is currently ported over to V2PDK and you should be able to download it from the ML300 lounge in the near future. A first version of the port will not support all peripherals that have been available in V2PDK but will give enough functionality to boot Linux. The TFT in EDK works as it is the same as in V2PDK. - Peter Antti Lukats wrote: > Hi > > just a few comments, hope the may save some time for someone > > ML300 is shipped with V2PDK > most V2Pro 'reference designs' are only for V2PDK > V2PDK is no longer supported by xilinx > the V2PDK examples only compile with synplicity, > not with XST, well XST compiles the verilog versions > and one simple VHDL example also compiles. > when using XST synthesis (with the verilog example) with almost > all options turned off the VP7 device on ML300 is 89% percent full? > > with EDK 3.2 there are no similar examples (for the V2Pro) as in > the V2PDK, as example the TFT LCD (available and working in V2PDK) > is 'obsoleted' and not replaced in EDK 3.2 so if you want to build > a standalone system with EDK 3.2 (and TFT) then you have no support - > the obsoleted core can be 'forced' to be visible in EDK/XPS but > no idea if it would function or not. > > ml300 does boot linux, ok, but all you can do is starting a calculator > - there is no docu about the linux implementation at all, yes there > is linux but how to write simplest application for it, no idea, from > montavista there is link back to xilinx. a round-trip. well at least > ml300 is now listed by montavista as supported platform (few months > ago still wasnt even listed). > > the VxWorks 'demo' with ml300 simply loads 5 bitmaps in delayed sequence. > > maybe I am missing some information, but that are my first feelings with > V2Pro/ml300 > > anttiArticle: 57603
i have in fact buy a CMUCam with the C3088 board. the C3088 is a little PCB with the OV6620 chip. so i hav elegaly buy a OV6620 !.. but Omnivision nevre answer my question. i have the datasheet for the camera .. but my english is not perfect, and i have no logic analyser. i have some doubt about the right code between the camera and my FPGA .. so i ask for help !.. the group is here for help every one .. if i can have help dirctly from Omnivision, i don't ask here .. but unlucky.. never answer if anyone can help me .. thank's Philippe "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> a écrit dans le message news: bdvkp2$c58$1$830fa17d@news.demon.co.uk... > "PC" <philippe.chagny**@NOSPAM@**@free.fr> wrote > in message news:3f033fb1$0$4611$626a54ce@news.free.fr... > > > please, if anyone can help me to find some information to interface the > > OV6620 to my FPGA ( VHDL ), don"t hesitate ! > > ov6620 : www.ovt.com > > ther is no application note .. no support.. :-( > > ahem, no, it's just that (I quote the website) > > >>> The DATASHEET for the OV6620 requires an NDA. > > (NDA = Non Disclosure Agreement, a confidentiality > contract agreeing that you won't give away any technical > information without the vendor's permission). > > On the other hand, there is a full data sheet for the > OV6630 part on the web site. > > If you got the sample device legitimately, how about > contacting them, signing the NDA and getting the data > that way? > > Hint: If anyone else HAS the data, they've signed the > NDA already and therefore they would be breaking their > contract with Omnivision by telling you about it. > > Cheers > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > > >Article: 57604
Kartik Krishnan wrote: > i want to use some ARM C/C++ compiler which is independent of the > operating system. > What i am looking for is plain translation of my C/C++ benchmarking > code into plain ARM assebly and then into binaries... > if i use the ADS C/C++ compiler it generates some software interrupts > which kinda throws everything off track... Did any one have the same > problem before...? > or shoudl i get started with writing my own ARM compiler (but would > take ages (: ) > Thanks > Kartik you can do what you want to do with ADS, but if you use something semihosting to do printf's and such I think it will use SWIs You may also have to provide the startup assembly file that does stack setup and memory init, yourself -LasseArticle: 57605
Bill wrote: > "Leon Heller" <leon_heller@hotmail.com> wrote in message news:<bdv712$oki$1@hercules.btinternet.com>... > >><eholbrook@austin.rr.com> wrote in message >>news:874r24dalp.fsf@vole.holby-net... >> >>>I'm looking for a DIMM format FPGA board like Pilchard or the AcB from >>>(now defunct?) Nuron. I've done several web searches, but found >>>nothing that both fits the bill, and is from a company that is >>>apparently alive. I've found a couple of things that are close to what >>>i want (from mite.cz, and sunrise-systems.de), but they don't return >>>emails, so i figure they're dead, too. >>> >>>Has anyone heard of something like this, or do i need to design/build >>>it myself? >> >>I was thinking of developing one. How about us collaborating? >> >>Leon > > > > From what I hear, SRC Computers holds patents in this area and is not > licensing to anyone right now. > > www.srccomp.com What! maybe I read it too fast maybe I just can't read patents or maybe I just don't understand, but don't they basically claim that they have patented programble logic memory mapped on a microprocessor? I would have guessed that that is widely used and has been for some time :) -LasseArticle: 57606
I know this is an FPGA news group, and my question is about CPLDs, but there did not seem to be a CPLD news group! So here goes... I am comparing these two families. Going to pick one of the two for a bunch of new designs. After comparing the features, the XPLA3 seem to be much better bang for the buck compared to the MAX3000. Price seems to be equal, but on a feature basis the XPLA3 is significantly better. However, Xilinx cut the XPLA1 and XPLA2 lines. My fear is that the same could happen to XPLA3. The Altera folks tell me that Altera/MAX has huge market share and focus in CPLDs, while CPLDs only account for 10% of Xilinx business. Any comments? Do you think the XPLA3 parts are gonna stay in production over the long haul? Thanks, Chris.Article: 57607
If, as you say, one of the clocks is derived from the other, then they have a fixed delay or phase relationship, and you should not have a problem. If, however, these two clocks are incoherent, you have a real tricky problem on your hands, and ignoring that will just get you deeper and deeper into trouble. Keep the design synchronous. Double-synchronize to reduce metastability problems. Flip-flops are almost free these days. Peter Alfke, Xilinx ============ Matt wrote: > > Mike Treseler wrote: > > > The change you show should not have made any difference. Post the complete process. Something else is going on. > > Thanks for the reply, Mike - here's the whole reciever UART process I'm > currently synth'ing... I started with a basic UART design from freecores.org and > wound up rewriting a bunch of it in order to process things like break > conditions and the like, as well as adding in the small FIFO to help with > handling data flow. As written below, the UART seems to function pretty much > normally when synthesized into the chip. However, beyond the problem I > origionally mentioned (the FIFOhead not seeming to update right away) this UART > also seems to have the quirk of occasionally letting two of the same received > byte slip thru when data is constantly streaming in. > > Unfortunatly this system contains two seperate clocks - one which is devided > down to run the UART at standard baud rates, and another which drives the main > chunk of the system which reads the recived bytes from the UART. It seems that > on occasion (and this is verifiable on a logic analyzer) the clocks seem to line > up such that status data is not read correctly, and the UART is somehow being > read twice in quick succession. > > Do I need to include a higher-level syncronization method to ensure the two > clocks don't cause issues when inevitably lining up such that one is reading > data controlled by the other, whilst the data is in the middle of a transition? > > I've played with a couple possible solutions, but nothing seems to work with > the double-reads. This seems like a nice simple recieving UART, but I'm stumped. > Any ideas? > > Regards, > -- Matt > > ................ > entity RxUnit is > port ( > Clk : in Std_Logic; -- system clock signal > Reset : in Std_Logic; -- Reset input > Enable : in Std_Logic; -- Enable input > ReadA : in Std_logic; -- Async Read Received Byte > RxD : in Std_Logic; -- RS-232 data input > RxAv : out Std_Logic; -- Byte available > DataO : out Std_Logic_Vector(7 downto 0); -- Byte received > Break : out Std_Logic; -- Break Detected > Debug : out Std_Logic); -- debug > end entity; > > architecture Behaviour of RxUnit is > signal RReg : Std_Logic_Vector(7 downto 0); -- receive register > signal ReadS : Std_Logic; -- Synchronised load signal > > component synchroniser is > port ( > C1 : in Std_Logic; -- Asynchronous signal > C : in Std_Logic; -- Clock > O : out Std_logic);-- Synchronised signal > end component; > > -- the FIFO > type FIFOarraytype is array (integer range 0 to 4) of std_logic_vector(8 > downto 0); > signal FIFO:FIFOarraytype; > > begin > > -- Synchronise Read on Clk > SyncLoad : Synchroniser port map (ReadA, Clk, ReadS); > --Busy <= LoadS or TBufL; > > -- Rx Process > RxProc : process(Clk,Reset,Enable,RxD,ReadS) > variable BitPos : INTEGER range 0 to 11; -- Position of the bit in the frame > variable SampleCnt : INTEGER range 0 to 3; -- Count from 0 to 3 in each bit > variable FIFOhead, FIFOtail : INTEGER range 0 to 4; -- FIFO head and tail > > begin > if Reset = '0' then -- Reset > --RRegL <= '0'; > --RRegLcache <= '0'; > BitPos := 0; > FIFOhead := 0; > FIFOtail := 0; > elsif Rising_Edge(Clk) then > > DataO <= FIFO(FIFOtail)(7 downto 0); -- always output whatever is on the FIFO tail > Debug <= FIFO(FIFOtail)(0); -- a signal to the outside world for debugging on > logic analyzer > Break <= FIFO(FIFOtail)(8); > > if (ReadS = '1' and FIFOhead /= FIFOtail) then -- advance FIFO on read edge > if(FIFOtail = 3) then > FIFOtail := 0; > else > FIFOtail := FIFOtail + 1; > end if; > else > Debug <= '0'; > end if; > > if(FIFOhead /= FIFOtail) then -- there is stuff in the FIFO > RxAv <= '1'; -- Indicate there is data avaliable to be read > else > RxAv <= '0'; > end if; > > if Enable = '1' then > case BitPos is > when 0 => -- idle > if RxD = '0' then -- Start Bit > SampleCnt := 0; > BitPos := 1; > end if; > when 10 => -- Stop Bit > BitPos := 11; -- next is holding pattern for breaks > if(FIFOhead = 3) then > FIFOhead := 0; -- wrap around > else > FIFOhead := FIFOhead + 1; > end if; > FIFO(FIFOhead)(7 downto 0) <= RReg; -- DUMMY 'WAIT' > FIFO(FIFOhead)(8) <= RxD; -- stash the break bit > FIFO(FIFOhead)(7 downto 0) <= RReg; -- stash the recieved data > > when 11 => -- Holding pattern for break release (so only one break is > recieved) > if(RxD = '1') then > BitPos := 0; > end if; > when others => > if SampleCnt = 1 then -- Sample RxD on 1 > RReg(BitPos-2) <= RxD; -- Deserialisation > end if; > if SampleCnt = 3 then -- Increment BitPos on 3 > BitPos := BitPos + 1; > end if; > end case; > if SampleCnt = 3 then > SampleCnt := 0; > else > sampleCnt := SampleCnt + 1; > end if; > > end if; > end if; > end process; > end Behaviour; > .............Article: 57608
Steve Lass <lass@xilinx.com> wrote: [snip] :I'm driving the ship and like I said, we have no plans to drop any other :architectures from our :software. All the FPGAs we have in the software now are derivatives of :the Virtex arcitecture :so keeping them in the release is not difficult. My apologies if I've missed something: I join this thread late. But now I'm worried: I was about to start a new design using Spartan: exactly what has been dropped? (It wasn't evident from the Xilinx website).Article: 57609
Look into why you have so many (147) luts used as route-throughs. 3 input LUTs: 230 (147 used as route-throughs) 230 - 147 = 83 = HMAPS reported by Synplify Pro. You can go into FPGA editor and see what the configuration is for some of these route throughs. Anand P Paralkar wrote: > Hi, > > I am using the following flow: > > VHDL - Entry > Synplify Pro - Synthesis > Xilinx Design Manager - Post synthesis, place and route, etc. > > The target device is Xilinx Spartan XL - XCS20XL. > > I am trying to understand the two summaries: > > 1. Synthesis Summary > -------------------- > Logic Mapping Summary: > FMAPs: 243 of 392 (62%) > HMAPs: 83 of 196 (43%) > Total packed CLBs: 173 of 196 (89%) <-*-*-*- > (Packed CLBs is determined by the larger of three quantities: > Registers / 2, HMAPs, or FMAPs / 2.) > > 2. Xilinx Design Manager Summary > -------------------------------- > Design Summary: > Number of errors: 1 > Number of warnings: 6 > Number of CLBs: 250 out of 196 127% <-*-*-*- > CLB Flip Flops: 346 > CLB Latches: 3 > 4 input LUTs: 246 > 3 input LUTs: 230 (147 used as route-throughs) > Number of bonded IOBs: 48 out of 112 42% > IOB Flops: 34 > IOB Latches: 0 > Number of clock IOB pads: 4 out of 8 50% > Number of TBUFs: 2 out of 448 1% > Number of BUFGLSs: 4 out of 8 50% > 32 unrelated functions packed into 31 CLBs. > (12% of the CLBs used are affected.) > Total equivalent gate count for design: 4178 > Additional JTAG gate count for IOBs: 2304 > ------------------------------------------------------------------- > > Why is there a discrepancy between the Number of CLBs reported > by the synthesis tool (173) and the Xilinx design manager (250)? > > As you would observe, the design manager reports an error due > to the excess usage of CLBs. As a result the flow does not proceed > to Place and Route etc. Any suggestions? > > Thank you for your time. > > Thanks, > Anand > >Article: 57610
In VHDL, use a signed type and use '*' - synthesis should generate a good result. In current verilog, just use a signed type. In older verilog versions you can simply sign extend the inputs to the width of the result and perform an unsigned multiply. Synplify will recognize this as a signed multiply and trim the input arguments back down. Synthesis tools should give you a good implementation directly. All you need to do is figure out where the binary point went and take the bits you want. praveen wrote: > Hello, > I am implementating Fixed point signed multiplication. Is there a > algorithm to implement it. I have done the usual method of > multiplication i.e partial products ...shift and add method. But its > very slow. If you know any algorithm which will faster do mention. Any > reference will be great. How does the signed multipliers in xilinx > that fast. what algorithm do they use. I need to first implement in on > MATLAB and see the result. > > waiting for reply > praveen >Article: 57611
David R Brooks wrote: > > Steve Lass <lass@xilinx.com> wrote: > [snip] > :I'm driving the ship and like I said, we have no plans to drop any other > :architectures from our > :software. All the FPGAs we have in the software now are derivatives of > :the Virtex arcitecture > :so keeping them in the release is not difficult. > > My apologies if I've missed something: I join this thread late. > But now I'm worried: I was about to start a new design using Spartan: > exactly what has been dropped? (It wasn't evident from the Xilinx > website). I'm not saying that you should or shouldn't use the Spartan chips. But I am curious as to why you would use such an old technology. Certainly there are cheaper, faster, bigger chips available. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57612
chris_s wrote: > > I know this is an FPGA news group, and my question is about CPLDs, but there > did not seem to be a CPLD news group! So here goes... > > I am comparing these two families. Going to pick one of the two for a bunch > of new designs. After comparing the features, the XPLA3 seem to be much > better bang for the buck compared to the MAX3000. Price seems to be equal, > but on a feature basis the XPLA3 is significantly better. > > However, Xilinx cut the XPLA1 and XPLA2 lines. My fear is that the same > could happen to XPLA3. The Altera folks tell me that Altera/MAX has huge > market share and focus in CPLDs, while CPLDs only account for 10% of Xilinx > business. > > Any comments? Do you think the XPLA3 parts are gonna stay in production > over the long haul? The XPLA3 is a relatively new family. Some of the members were only introduced a year ago. It is also very low power. The Altera parts are relative power hogs. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57613
chris_s wrote: > > I know this is an FPGA news group, and my question is about CPLDs, but there > did not seem to be a CPLD news group! So here goes... > > I am comparing these two families. Going to pick one of the two for a bunch > of new designs. After comparing the features, the XPLA3 seem to be much > better bang for the buck compared to the MAX3000. Price seems to be equal, > but on a feature basis the XPLA3 is significantly better. > > However, Xilinx cut the XPLA1 and XPLA2 lines. My fear is that the same > could happen to XPLA3. The Altera folks tell me that Altera/MAX has huge > market share and focus in CPLDs, while CPLDs only account for 10% of Xilinx > business. > > Any comments? Do you think the XPLA3 parts are gonna stay in production > over the long haul? I'd also look at the Atmel ATF15xx, and Lattice ispMAX4000 families. Altera may have the largest CPLD chunk, but they have not done much in an Architectural sense, and their Icc is quite high. Xilinx have the newer XC2 in front of the XPLA3, so you could spin a design, and check the FIT in both families. With Atmel, Lattice and Xilinx all offering low static Icc CPLDs, Altera are looking a tad dated. -jgArticle: 57614
Hi, I've written a very simple application (hello world :) for the Linux in ML300 using ELDK's ppc_4xx cross compiler. http://lists.linuxppc.org/linuxppc-embedded/200305/msg00033.html I think it will be great if Xilinx can issuse some reference about how the Linux demonstrating platform can be built. It will be useful for building a customerized embedded Linux platform. Cheers, tk "Antti Lukats" <antti@case2000.com> ????? news:80a3aea5.0307021103.7a8add38@posting.google.com... > Hi > > just a few comments, hope the may save some time for someone > > ML300 is shipped with V2PDK > most V2Pro 'reference designs' are only for V2PDK > V2PDK is no longer supported by xilinx > the V2PDK examples only compile with synplicity, > not with XST, well XST compiles the verilog versions > and one simple VHDL example also compiles. > when using XST synthesis (with the verilog example) with almost > all options turned off the VP7 device on ML300 is 89% percent full? > > with EDK 3.2 there are no similar examples (for the V2Pro) as in > the V2PDK, as example the TFT LCD (available and working in V2PDK) > is 'obsoleted' and not replaced in EDK 3.2 so if you want to build > a standalone system with EDK 3.2 (and TFT) then you have no support - > the obsoleted core can be 'forced' to be visible in EDK/XPS but > no idea if it would function or not. > > ml300 does boot linux, ok, but all you can do is starting a calculator > - there is no docu about the linux implementation at all, yes there > is linux but how to write simplest application for it, no idea, from > montavista there is link back to xilinx. a round-trip. well at least > ml300 is now listed by montavista as supported platform (few months > ago still wasnt even listed). > > the VxWorks 'demo' with ml300 simply loads 5 bitmaps in delayed sequence. > > maybe I am missing some information, but that are my first feelings with > V2Pro/ml300 > > anttiArticle: 57615
To find out where SOPC Builder is: Run "regedit32" from Start menu/Run. Look for the Software/Altera/SOPC Builder branch. This will tell you all of the currently installed versions of SOPC Builder, and also which one is currently active. I hope I got the branch right .. I don't have my work PC in front of me at the moment. One other thing: Do you also have a separate Cygwin installed? This can seriously screw things up. I've done this and got the symptoms you have, and it took awhile to debug. HTH, -- Pete > I'm trying to follow the NIOS tutorial for the Stratix1S10. > At one point, page 16 of the 'tt_nios_hw_stratix_1s10.pdf' > I should start the SOPC builder. A quick console window opens, > to fast to recognize anything, and vanishes. > There is no error message, nowhere. > There is no SOPCBuilder as it should be according to the pdf. > I browswed the SOPC Builder solutions in the knowledge base. > > From this FAQ I could gleam that the SOPC builder has to > be installed. How can I check whether it was installed, and if > not, where is this SOPC Builder to be found ? > > I'm using Quartus2 Build 176 02/04/2003 SJ Full Version > plus the SP1 > > > ReneArticle: 57616
in ISE project navigator, when I run the 'generate post-PAR simulation model' process, I get a warning below: WARNING:NetListWriters:108 - In order to compile this verilog file successfully, please add $XILINX/verilog/src/glbl.v to your compile command. I'm using a GUI software, how can I change its default command line under the button?Article: 57617
Hello, I am looking for an ARM (preferably StrongARM) w/ FPGA development board. StrongARM preference is for mainly for Linux. Any other supported processor will do as well. Thanks a lot! -SumeetArticle: 57618
Hi all, I am an extreme newbe to the xilinx CPLD's. I will try to explain what I have and what I am having problems with. If someone can help out that would be great. After trying to download most of the versions of webpack I finally got version 3.8 to work on my windows 98 setup. I am using the schematic entry and using a xilinx xc9572 in plcc44. I am not sure if you need to use verlog or what, but I pick one and then use the schematic entry. My questions are when you make a schematic is it mandatory to use ibuf and obuf on your inputs and outputs. Also none of the flip flops have a /Q output. Do you simply use an inverter on the Q output for Q/ ? I have made a couple of schematics and programmed the chip, but they do not function as I would expect. I think that you must have to be a rocket scientist to figure this stuff out :) Thanks for any help. FredArticle: 57619
Who makes the best FPGA? Lattice or Cypress?Article: 57620
On 3 Jul 2003 00:34:59 -0700, seannstifler69@hotmail.com (Stifler) wrote: >Who makes the best FPGA? Lattice or Cypress? :-)Article: 57621
> > > > > > > > Personally, I agree with your statement and have been trying to convince > > the > > > > powers that be to add additional Spartan-3 devices to WebPack. The > > folks > > > > responsible for WebPack are concerned about the total download size. > > The > > > > larger devices have multi-MB support files. > > > > > > If the size of the download is the issue, there are very simple ways to > > > address that. One is to split the download into two parts, one for the > > > current configuration and one for the added support for the larger > > > devices. The other is just to ship the CD as you already do. I don't > > > think adding all the chips will blow away a CD will it? As it is, I > > > don't think it is very practical to ask a user to download a 150 MB > > > file. At least it is not practical for me to download it. > > > > > > > There's little doubt that multiple optional download parts is the most > > elegant solution - along with the possiblity of getting everything on CD for > > those that want that. However, the current WebPack is so large that a few > > extra megabytes for extra part support would not make a significant > > difference. And anyway, are there many companies with the resources to be > > involved in fpga design, but without a permanent internet connection? Even > > if it's a bit slow, you can always leave a download running overnight. > > Overnight does not cut it. As for the resources, it really does not > take a lot and a high speed internet connection is not even on the list > other than for this sort of download. These files are so large that the > reliability of the connection becomes a significant factor. The last > time I actually downloaded webpack, it took me about five trys and over > a week. > > I know there are tools that let you restart an interrupted download, but > even then it is a real chore getting a download completed. I much > prefer to buy the CD. > I fully support the option of being able to buy the CD - even for those of us with reliable internet connections, there are times where a single CD in the post can be more convenient. And I agree that reliability is the main factor for the internet connection - a 57kbaud modem can download 150 MB overnight, but only if it is reliable enough! But is it really that hard or that expensive to get a solid line? I find it is an essential requirement for my work - speed is not critical (we have a 386 kbit ADSL line for the office), but reliability is. Incidently, you might like to try NetAnts for downloading over a dodgy line, although I'm sure everyone has there favourite download utility.Article: 57623
Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3F0319FA.8D327A@xilinx.com>... > Hi Santi, > > Since 5.x version, FPGA Editor no longer support hard macro containing Vcc comps. What you'll have to do is > declear pins that connects to Vcc as external macro pin and connect the pin to Vcc or '1' in your source > code. > > Regards, Wei > Hi Wei, The problem is the VCC/GND are inferred by the synthesis tool, therefore I can't get rid of them unless there is a way of telling to Synplify not to use them. I find pretty ackward that the former versions of the ISE supported it and not the newers. Thanks, SantiArticle: 57624
Petter Gustad wrote: > Rene Tschaggelar <tschaggelar@dplanet.ch> writes: > >>I'm trying to follow the NIOS tutorial for the Stratix1S10. >>At one point, page 16 of the 'tt_nios_hw_stratix_1s10.pdf' >>I should start the SOPC builder. A quick console window opens, >>to fast to recognize anything, and vanishes. > > It appears that you have a problem with your installation. > >>There is no error message, nowhere. > > Not even in the message window? View->Utility Windows->Messages if you > don't have it visible. > Not even there. > >> From this FAQ I could gleam that the SOPC builder has to >>be installed. How can I check whether it was installed, and if >>not, where is this SOPC Builder to be found ? > > There should be a directory containing a bin directory which contains > a file called sopc_builder (which is a perl script). I don't know how > Quartus will search for sopc_builder because both under Windows and > Solaris I have multiple revisions of sopc builder and Quartus is using > the most recent one. > > You should have received a CD containing the NIOS 3.0 release with > SOPC Builder (version 2.8) and Quartus II. There indeed is a directory named 'C:\altera\excalibur\sopc_builder\bin' and it contains a lot of stuff. Some files passing the mask 'sopc_builder.*' From this all I take, that SOPC builder is installed. <complain> Notice the not-Win2k conforming 'C:\altera'. I tried it first with : 'c:\program files\altera\...' to no avail. When I'm forced to use a Win2k machine for the USB, I'd at least expect the software to be Win2k conform. </complain> Rene
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