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"Gian" <voxel@blueyonder.co.uk> asked "Is it possible to simulate a VLIW multiprocessor using a FPGA devise ?" You may find useful the postings at FPGA CPU News on and around this topic: http://www.fpgacpu.org/log/mar02.html#020311. Jan Gray, Gray Research LLCArticle: 57651
juice28 wrote: > Hi all, > > I am an extreme newbe to the xilinx CPLD's. I will try to explain what I > have and what I am having problems with. If someone can help out that would > be great. > > After trying to download most of the versions of webpack I finally got > version 3.8 to work on my windows 98 setup. What version is that? I have just installed 5.2i. Are you getting the software from Xilinx? > I am using the schematic entry and using a xilinx xc9572 in plcc44. I am not > sure if you need to use verlog or what, but I pick one and then use the > schematic entry. Don't need Verilog or any HDL, if you want to do a schematic. > My questions are when you make a schematic is it mandatory to use ibuf and > obuf on your inputs and outputs. I think so, I do it. I would be surprized if it will compile without using IO buffers. (Pardon my lack of knowing if the right term is "synthesize", "translate", "fit", or some combination of the above). I will await hearing what the experts have to say on this one as well. >Also none of the flip flops have a /Q > output. Do you simply use an inverter on the Q output for Q/ ? I have made > a couple of schematics and programmed the chip, but they do not function as > I would expect. When that happened to me in the beginning, it was because the software was not using my pin assignment constraints. You should have ran a module called "assign package pins" or something like that. I am currently puzzled by the convoluted approach to this in Xilinx software, which I will likely post about in a few minutes. But basically, you need to have created a .ucf user constraints file, through one means or another. There are GUI programs to do it, or you can edit text. This file associates net names (signals) in your design (schematic) with physical chip pins. Now on older software, it was my experience that the software would not obey my selections unless I also checked a box in the "synthesize" propoerties (right click on "synthesize" part of the project navigator), which was something like "use user contraints file" in the old software. Now things are different, and even more confusing overall, but works better by default. You really need to use 5.2, unless it doesn't support the old CPLD you are using? > I think that you must have to be a rocket scientist to > figure this stuff out :) Yes, that is correct. Enroll in a rocket scientist course immediately! ;-) -- _______________________________________________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.Article: 57652
Stifler wrote: > check check one twoo You're supposed to say that into a microphone. Here it goes like this: "this is a test, please ignore." -- _______________________________________________________________________ Christopher R. Carlen Principal Laser/Optical Technologist Sandia National Laboratories CA USA crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply.Article: 57653
Manfred, XC3S50 are available (I inadvertently posted publicly that I have some in my drawer). The only 3S50 available for several months in the near future are the ones without BlockRAM and DLL. It's not a defect problem: The original decision had been to leave out BRAM and DLL, for cost reasons, on this smallest member of the family. I think there also is a question of how many pins are 3.3V tolerant on these Early Silicon parts.This was later changed, and the "real" 3S50 will have BRAM and DCM and be 3.3V tolerant, but it isn't here yet. The ES devices are therefore marked with a trailing J, to distinguish them from the later "real" part. All ES parts, by definition, come with an errata sheet, and distributors prefer not to deal with all this complexity and confusion. Contact your local FAE. I hope this explains the situation. Peter Alfke, Xilinx Applications ================================= Manfred Kraus wrote: > > My distributor (Insight, Germany) told me, there are no Spartan-3 > engineering samples available or orderable yet. Also, there are no > prices available. All they can say is that parts and samples can be > ordered by the end of the year. > > Is this also true for other countries ? I urgently need some samples > of the XC3S50-4PQ208C part. Can someone help me to get them ? > > Does Xilinx really advertise parts, that are not available, or is there > another reason that Insight cant order parts for me up to now ? > > -Manfred Kraus > mkraus_at_cesys_dot_comArticle: 57654
Rainer Buchty wrote: >In article <3f042929$0$23100$5a62ac22@freenews.iinet.net.au>, > hamish@cloud.net.au writes: >|> I don't think dropping support for old devices is too unreasonable. >|> Otherwise the QA effort for each new software version (major, minor, >|> even service pack) just grows bigger and bigger, and the design of >|> the software gets more complex and messier etc. > >Why would this be so? If the software is modularized, e.g. the fitter >(placer/router) is its very own piece of command-line software there is >no need to touch that code again (plus, doing so eases portability). > Our software is modular, but each module is not self contained. There are common routines we use for constraint parsing, command line handling, IO interfaces, database management, base level mappers, etc. Making changes to these common utilities can have unexpected effects on older software. This was a bigger issue for us with the pre-Virtex architectures. Like I said, since all FPGAs in the software are based on the Virtex architecture, there is no reason for us to drop any more families. Right now, our software is over 20 million lines of code. If each architecture's software was self contained, my guess is, that would double. I would think that most of you would rather we put our testing effort into the more recent architectures. Again, the 4K and Spartan/XL software is available, fully supported, and free. Steve > >If integration of the necessary calls into the GUI is an issue, well, then >just leave it out. From what I read in this and other "tech" groups, >developers seem to prefer to write their own batch scripts anyway. (If >the shared development machines sit "two networks further", you don't >want to wait for GUI updates anyway.) > >Just my $0.02, > Rainer > > > > >Article: 57655
> > I'm not saying that you should or shouldn't use the Spartan chips. But > I am curious as to why you would use such an old technology. Certainly > there are cheaper, faster, bigger chips available. > In our case, the designs are done. In are market we are not that sensitive to part costs. The real cost is qualifying a new design just to phase out a part the is still being sold. New designs, no problem.Article: 57656
> I'm driving the ship and like I said, we have no plans to drop any other > architectures from our > software. All the FPGAs we have in the software now are derivatives of > the Virtex arcitecture > so keeping them in the release is not difficult. > > Steve Lass > Director, Software Product Marketing > Xilinx, Inc. Steve, you have a tough job making these calls, and I am sure you are guiding Xilinx in a maner that is best suited for them. I believe you when you made the statement "..we have no plans to drop ...". I am sure there were no plans to drop any parts from the tools at a given time. Fool me once, shame on me. (3.x drops 3xxx parts) Fool me twice (5.x drops Spartan +), ..... Our company has been using Xilinx exclusively. This latest move from Xilinx has caused us to re-think our stratagy. All of the tools we use to interface with Xilinx will support both companies and we mostly deal with strick VHDL. Supporting both Altera and Xilinx is not a problem. Xilinx is sending someone next week to talk with us. Should be interesting.Article: 57657
Version 5.2 only works on windows 2000. I am using 3.2 as it seems to be the only one that works on my setup. I have also assigned the input and outputs to pins using the user constraints, but I did not use the ibuf and obuf (it seemed to compile alright though) so maybe that is my problem. Still wondering what is up with Q/ on the flip flops too. Thanks, Fred "Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message news:be1i2j$h77$1@sass2141.sandia.gov... > juice28 wrote: > > Hi all, > > > > I am an extreme newbe to the xilinx CPLD's. I will try to explain what I > > have and what I am having problems with. If someone can help out that would > > be great. > > > > After trying to download most of the versions of webpack I finally got > > version 3.8 to work on my windows 98 setup. > > What version is that? I have just installed 5.2i. Are you getting the > software from Xilinx? > > > I am using the schematic entry and using a xilinx xc9572 in plcc44. I am not > > sure if you need to use verlog or what, but I pick one and then use the > > schematic entry. > > Don't need Verilog or any HDL, if you want to do a schematic. > > > My questions are when you make a schematic is it mandatory to use ibuf and > > obuf on your inputs and outputs. > > I think so, I do it. I would be surprized if it will compile without > using IO buffers. (Pardon my lack of knowing if the right term is > "synthesize", "translate", "fit", or some combination of the above). > > I will await hearing what the experts have to say on this one as well. > > >Also none of the flip flops have a /Q > > output. Do you simply use an inverter on the Q output for Q/ ? I have made > > a couple of schematics and programmed the chip, but they do not function as > > I would expect. > > When that happened to me in the beginning, it was because the software > was not using my pin assignment constraints. You should have ran a > module called "assign package pins" or something like that. I am > currently puzzled by the convoluted approach to this in Xilinx software, > which I will likely post about in a few minutes. > > But basically, you need to have created a .ucf user constraints file, > through one means or another. There are GUI programs to do it, or you > can edit text. This file associates net names (signals) in your design > (schematic) with physical chip pins. > > Now on older software, it was my experience that the software would not > obey my selections unless I also checked a box in the "synthesize" > propoerties (right click on "synthesize" part of the project navigator), > which was something like "use user contraints file" in the old software. > > Now things are different, and even more confusing overall, but works > better by default. > > You really need to use 5.2, unless it doesn't support the old CPLD you > are using? > > > > I think that you must have to be a rocket scientist to > > figure this stuff out :) > > Yes, that is correct. Enroll in a rocket scientist course immediately! > > ;-) > > > > > > -- > _______________________________________________________________________ > Christopher R. Carlen > Principal Laser/Optical Technologist > Sandia National Laboratories CA USA > crcarle@sandia.gov -- NOTE: Remove "BOGUS" from email address to reply. >Article: 57658
Chris_S <nospam@nospam.com> wrote: :> XC2 (Coolrunner II) is 3.3 Volt in and out, if you provide that IO : voltage. : Yeh I guess you are right, but not with a single supply of course. I would : have to add regulators everywhere for the 1.8V cores and that might become a : pain. A small SOT23 regulator fits nicely below the Coolrunner (Coolrunner on top, regulator on botton). So no need for an extra supply layer. XC2C is not sensitive to power sequencing, so no problem their neither. The Xetex XC6204 goes for about 0.77 EuroCent at Farnell. : Based on what the FAE told me the CR2 may go away. Apparently what they are : coming out with next will be the successor to that family. Don't know if : the pinouts will change. Even XC95XV(L) and XC2C have very similar pinout. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57659
Stifler wrote: > > Who makes the best FPGA? Lattice or Cypress? No. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57660
Here are some tutorial notes, to calm the waves: The physical life-length of typical FPGAs is >>10 years continuously at the max allowed stress. In practical terms this means they work and are reliable for 50 years or even longer, effectively forever. "Old FPGAs never die, they just get obsolete". The commercial availability of popular parts is well beyond 10 years after introduction. Unpopular sleepers may be discontinued earlier. Any responsible manufacturer gives you 1 to 2 years of warning and "last buy" opportunities, and sometimes transfers the die inventory to an "afterlife" supplier. Software support in the most current releases can be a problem, and has been discussed here. For Xilinx, the architectural commonality of all Virtex and Sparten-II ( and later) devices makes it easier to maintain support for all these families. Old software is available for free, but may require an old computer OS. Design-in life is much shorter, since newer devices make the older devices appear slow and expensive. "One year in the life of an FPGA equals 15 years of human life" means that a device introduced 2 years ago is in its prime, a device introduced 4 years ago is now a senior citizen, fully capable but not to be raced against the newer parts. (There are special cases: Spartan-XL, with its roots in XC4000, is today the last really low idle-power FPGA family, and is 5-V tolerant and -compatible.) Freshly announced parts are exciting, but the user must ascertain their availability. The manufacturer should not be criticized for releasing product details ahead of availability. That gives the user a chance to plan and evaluate. And finally, we all know and understand that the frentic pace of FPGA innovation is at odds with the long design cycle time of miltary and aerospace projects. Just some common thoughts... Peter Alfke ==========================Article: 57661
David Brown wrote: > > > > > > > > > > > Personally, I agree with your statement and have been trying to > convince > > > the > > > > > powers that be to add additional Spartan-3 devices to WebPack. The > > > folks > > > > > responsible for WebPack are concerned about the total download size. > > > The > > > > > larger devices have multi-MB support files. > > > > > > > > If the size of the download is the issue, there are very simple ways > to > > > > address that. One is to split the download into two parts, one for > the > > > > current configuration and one for the added support for the larger > > > > devices. The other is just to ship the CD as you already do. I don't > > > > think adding all the chips will blow away a CD will it? As it is, I > > > > don't think it is very practical to ask a user to download a 150 MB > > > > file. At least it is not practical for me to download it. > > > > > > > > > > There's little doubt that multiple optional download parts is the most > > > elegant solution - along with the possiblity of getting everything on CD > for > > > those that want that. However, the current WebPack is so large that a > few > > > extra megabytes for extra part support would not make a significant > > > difference. And anyway, are there many companies with the resources to > be > > > involved in fpga design, but without a permanent internet connection? > Even > > > if it's a bit slow, you can always leave a download running overnight. > > > > Overnight does not cut it. As for the resources, it really does not > > take a lot and a high speed internet connection is not even on the list > > other than for this sort of download. These files are so large that the > > reliability of the connection becomes a significant factor. The last > > time I actually downloaded webpack, it took me about five trys and over > > a week. > > > > I know there are tools that let you restart an interrupted download, but > > even then it is a real chore getting a download completed. I much > > prefer to buy the CD. > > > > I fully support the option of being able to buy the CD - even for those of > us with reliable internet connections, there are times where a single CD in > the post can be more convenient. And I agree that reliability is the main > factor for the internet connection - a 57kbaud modem can download 150 MB > overnight, but only if it is reliable enough! But is it really that hard or > that expensive to get a solid line? I find it is an essential requirement > for my work - speed is not critical (we have a 386 kbit ADSL line for the > office), but reliability is. > > Incidently, you might like to try NetAnts for downloading over a dodgy line, > although I'm sure everyone has there favourite download utility. I don't know about my line being "dodgy". I just know that the combination of ISP, phone line, modem, OS and browser software makes it hard to get a 17 hour download to complete without error. It is also a PITA tying up the modem connection for a day while this is going on. It makes it very slow to browse or even get emails. As to the effort required to get a solid data line, there is virtually *nothing* you can do if your voice capability is not affected. I have talked to the phone company before and they have made it clear that a phone line is not a data line. They guarantee no specific data rate. DSL is not available in the second largest city in Maryland and Cable Modem is a fixed installation, it can not be easily moved from one computer to another. Cable Modem also goes out in nearly every storm along with the TV. I only wish I could get connected at 57 kbps! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57662
Chris_S wrote: > > So both of you are suggesting going a different direction than Altera. > > I have been burned twice before by prog logic parts going away. That's why > I am only going to consider designing in something that is in widespread > use - either Altera or Xilinix. Its got to be around for >10 years. Wow, you don't ask for much. I suggest that you check around and see how many PLDs, other than the 20V10s or smaller, have been available for 10 years. I expect you will not find one! This is just not the way of very many semiconductors. > The Xilinx XPLA3 are better parts than the MAX3000. Even the Altera FAE > here admits it. But are they going to be around in the future? I know > MAX3000 will be around because there are tons of people using them. I just > don't know how many XPLA3 are in use. There are plenty enough to keep the family in production for a normal lifetime of 5 or 6 years. > Won't touch Atmel, Lattice or anything else. Too risky, too little market > share. You should take another look at both Atmel and Lattice. Don't go by some silly number like "market share". Check out the longevity of the parts they made 5 or more years ago. > My requirement is full 3.3V in and out. So XC2 is no good (2.5V). If you are talking about power supply, then you can't use *any* of the newer parts. If you are talking about IO standards, then you can use LVTTL with nearly *any* family out there. > The Altera people told me that a new CPLD family is coming out soon. It > will be lower power. Sounds like Altera has gotten very sick of hearing > their parts are current hogs. Did they give you a schedule by any chance? If they don't have a schedule then you shouldn't expect it within the year. Oh, yeah, don't expect it to be 5 volt tolerant. If you only need LVTTL, then you should be ok, but all newer devices are 5 volt phobic. > Xilinx says that they also have a new CR (2.5V) part coming out, but it will > probably replace the XC2 line, not XPLA3. They say XPLA3 is not going to be > obsolete. I very seriously doubt that Xilinx is going to replace the XC2 line. It is not very old at all. The XPLA3 line is 5 volt tolerant (sort of) and no new process can replace that. Where did you hear this new line? > Does not sound like either of you are using the XPLA3. That concerns me. > > Chris. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57663
Hey, a Lattice guy. What you say makes a lot of sense, and the market share numbers are interesting. Yes, I am in Portland right by you. I'll give the rep a call. You are right I should probably take a look at Lattice before I decide. They are the 3rd big player. Thanks, Chris. "Mikeandmax" <mikeandmax@aol.com> wrote in message news:20030703100942.13330.00000034@mb-m13.aol.com... > >So both of you are suggesting going a different direction than Altera. > > > >I have been burned twice before by prog logic parts going away. That's why > >I am only going to consider designing in something that is in widespread > >use - either Altera or Xilinix. Its got to be around for >10 years. > > > >The Xilinx XPLA3 are better parts than the MAX3000. Even the Altera FAE > >here admits it. But are they going to be around in the future? I know > >MAX3000 will be around because there are tons of people using them. I just > >don't know how many XPLA3 are in use. > > > >Won't touch Atmel, Lattice or anything else. Too risky, too little market > >share. > > > > Hi gang - sorry for the marketing blitz below :) > > Hi Chris - > Lattice has over 40% marketshare in CPLD, ALtera has over 40% market share in > CPLD, Xilinx is ~10% in CPLD. Lattice has obsoleted very few of the CPLD > device families introduced over the past 11 years ( some older MACH devices > from the Vantis acquisition, mainly). Lattice offers multiple different > architectures in CPLD, from 32 macrocells to 1024 macrocells, in 1.8v, 2.5v > ,3.3v, and 5v. I would strongly recommend Lattice at least be given a close > look.(of course I am a bit biased :) ) > I am not sure where "nospam.com" is located, but I am willing to bet we have > resources neardby! A local FAE would be happy to talk with you. > > Our downloadable LEVER3 starter software includes Synplicity for VHDL/VERILOG > synthesis, ABEL and Schematic capture, funtcional and timing simulation. > Supports all product families. > > Michael Thomas > LSC SFAE > New York/New Jersey > 631-874-4968 fax 631-874-4977 > michael.thomas@latticesemi.com > for the latest info on Lattice products - http://www.latticesemi.com > LATTICE - BRINGING THE BEST TOGETHER >Article: 57664
guest wrote: > > Dear Falk & Peter, > Thanks for replying, As Iam basic to this information, Please > correct me if iam wromg > > NRZ coding say it doesn't return to 0v. For transmitting '1' +V is > used > and for transmitting '0' -V volt is used. > > we have signalling standards like LVTTL, TTL, CMOS they represent '1' > as +V and '0' as 0V > > What do i say the chip, which provides the NRZ interface, > 1) Its signalling varies from +v to -v doesn't return to 0V > 2) Or it has used NRZ coding over Some (say CMOS) signalling > standard then one is represented by + Vdd and zero is represented by > 0V, am I wright..? > > 3) what is NRZ, is it not an line coding, i.e how to represent the 1 > and 0 across the physical link ? > > Thanks in Advance You need to do some web searches and learn what NRZ really is. First of all, NRZ is not one coding style, but it is several which have one common feature, "the signal does not have to return to zero for each bit". This refers to the way that the two voltage levels are used to indicate if a bit is a 1 or a 0, not what the voltage levels are. So you can use NRZ with TTL signals of 0 volts and 5 volts or you can use NRZ with RS-232 voltage levels which are +12 volts and -12 volts. It has been too long since I worked with NRZ and the many variations to explain it without making an error. So you need to do a little digging on your own. Do a search on NRZ and possibly also Manchester and any others that you can think of. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57665
gilad_coh@walla.co.il (Gilad Cohen) wrote in message news:<8f9a8978.0307021109.42915dc8@posting.google.com>... > ecarvalho@inf.pucrs.br (Ewerson Carvalho) wrote in message news:<1d281733.0307011401.2740faa4@posting.google.com>... > > Hi, > Take a look at: http://www.xilinx.com/xapp/xapp290.pdf > The flow described there recommends no more than one reconfigurable > module, but allows more than one. > They also have a flow for minor changes - such as RAM contents and > things like that. > Gilad. Hi, I have already developed sytems according to Modular Design based on xapp290 with only one reconfigurable module, using Bus Macros. My doubt is how can I relocate bitstreams on FPGAs? The difference between two bitstrems with the same logic and designed to different places is only CRC, FAR and FDR (bitstreams registers)? I don't know if this is true. Thanks in advance for any help. Ewerson L. S. Carvalho, Master Student - Informatics Institute, PUCRS Mail Address: Av Ipiranga, 6681, Prédio 16. Porto Alegre, RS, Brazil CEP:90619-900 - Phone:+55 51 3320 3611 - Fax:+55 51 3320 3758 e-mail: ecarvalho@inf.pucrs.br - URL: http://www.inf.pucrs.br/~ecarvalhoArticle: 57666
> I'm using XPLA3, about 20 or so a year :-D > But they are very nice. The only thing I hate is the schematic editor, > which sucks real bad, and the ISE Webpack software, which overall gets a > C- . Ahhh, someone else is using XPLA3. Very good. I write everything in Verilog and use Synplicity to compile, so I only plan on using the Xilinix tools to fit/route the part. I think the XPLA3 is a really fantastic family, and what you say confirms this again. What bothers me is how many people are using it. I looked on the Xilinx site on the "success stories" and they have a section for every type of FPGA and CPLD they make except for the XPLA3! I really can't tell if Xilinix is truely behind this family or not. I'll be talking to the rep today. Chris.Article: 57667
Phil Hays <SpamPostmaster@attbi.com> wrote in message news:<3F0251F7.C10AA8D5@attbi.com>... > Jon Terje Haugland wrote: > > > I am designing a DDR SDRAM controller in a Virtex-II 1500 -5 FFA896. > > It should operate at 166 MHz towrads the DDR SDRAM. I have used > > XAPP266 as reference regarding the timing analysis towards the DDR > > SDRAM. In XAPP266 one of the "results" is: > > 0.503ns<tDQS-tDQ<1.025 (midpoint at 0.76ns). This delay is introduced > > by routing? If the PCB delay is 180ps pr. inch. it would require a DQS > > net that is 4.2 inches? Is this correct??? > > Yes, this is correct. This delay is the difference between the DQ line > length on the PCB and the DQS line length on the PCB. If the DQ lines > are 1.5 inches, the DQS lines need to be 1.5 inches + 4.2 inches = 5.7 > inches, assuming 180ps/inch. The delay of the PCB varies with stackup, > use care. Delay of vias can be significant, make sure the number and > placement of vias match or that this delay is included in the > calculation. Why don't use a phase shifted DDR clock instead of DQS to latch the reading data? The delay is more manageable I guess. JunArticle: 57668
Ah, yes, thanks. I actually did that at the same time as I posted here. There it is running under user firstname/secondname = A/A. The N-th re-log-on is shorter than the first. Rene Subroto Datta wrote: > Rene, please use mysupport.altera.com or the hotline. I have also forwarded > this to the relevant group inside Altera. > > - Subroto Datta > Altera Corp. > > "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message > news:270bd5f9eee3e76944507a61ff1c81ea@free.teranews.com... > >>I'm trying to follow the NIOS tutorial for the Stratix1S10. >>At one point, page 16 of the 'tt_nios_hw_stratix_1s10.pdf' >>I should start the SOPC builder. A quick console window opens, >>to fast to recognize anything, and vanishes. >>There is no error message, nowhere. >>There is no SOPCBuilder as it should be according to the pdf. >>I browswed the SOPC Builder solutions in the knowledge base. >> >> From this FAQ I could gleam that the SOPC builder has to >>be installed. How can I check whether it was installed, and if >>not, where is this SOPC Builder to be found ? >> >>I'm using Quartus2 Build 176 02/04/2003 SJ Full Version >>plus the SP1Article: 57669
Manfred Kraus wrote: > > I found this on the XILINX Website > located in document: http://www.xilinx.com/products/spartan3/faq105_s3.pdf > > 13. When will Spartan-3 devices be available? > Spartan-3 samples began shipping in March. First available devices are the > XC3S1000 and XC3S50. > > 14. How much will Spartan-3 devices cost? > Volume pricing at the end of 2004 will be under $3.50 for the XC3S50 and > under $20 for the XC3S1000, and under $100 for the XCS4000 (based on > 250K unit quantities). The XC3S50 and XC3S1000 parts have been sampling, but you have to be a major customer to get them for the most part. Also, there are significant errata with these parts so that the production date has changed from 2Q03 to 1Q04. The XC3S200, 400 and 1500 are slated to be in production in 4Q03. You should be able to get samples in Q3 (any time now). So you might want to bump your design up to the XC3S200, at least for prototyping. As for the idea that they advertised a new family before it was available, yes, that is actually very, very common in the semiconductor market. Everyone does it. The question is how much in advance do they advertise and how good is their track record in getting the parts out on time? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57670
> XC2 (Coolrunner II) is 3.3 Volt in and out, if you provide that IO voltage. Yeh I guess you are right, but not with a single supply of course. I would have to add regulators everywhere for the 1.8V cores and that might become a pain. Based on what the FAE told me the CR2 may go away. Apparently what they are coming out with next will be the successor to that family. Don't know if the pinouts will change. Chris.Article: 57671
Matt wrote: > seeming to update right away) this UART also seems to have the quirk of > occasionally letting two of the same received byte slip thru when data > is constantly streaming in. Quirks like this smell like a synchronization problem. Consider using the synchronous template for all synth code. > > Unfortunatly this system contains two seperate clocks - one which is > devided down to run the UART at standard baud rates, and another which > drives the main chunk of the system which reads the recived bytes from > the UART. It seems that on occasion (and this is verifiable on a logic > analyzer) the clocks seem to line up such that status data is not read > correctly, and the UART is somehow being read twice in quick succession. You have identified and verified a synchronization problem. > Do I need to include a higher-level syncronization method to ensure > the two clocks don't cause issues when inevitably lining up such that > one is reading data controlled by the other, whilst the data is in the > middle of a transition? No. Use only only the faster clock as a clock. Inputs including former clocks are all synched with two dflops and become inputs that never appear in a sensitivity list. > RxProc : process(Clk,Reset,Enable,RxD,ReadS) Change to RxProc : process(Clk,Reset) and watch the other inputs events synchronously. -- Mike TreselerArticle: 57672
"Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:<M7JMa.30912$a51.1242@news02.bloor.is.net.cable.rogers.com>... > Hi Dennis, > > > for the new multichannel filter design I have a choice - > > Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???) > > Here are a few key advantages for Cyclone that I can think of off the top of > my head: > > - Availability. The 1C12 is in full production on a 130 um process that > we've used to manufacture 10+ different devices (including 7 Stratix > members, 4 Cyclone members, and some Apex II members) > > - Performance. The _slowest_ Cyclone speed grade is 20% faster (geometric > average of fmax over many real user designs) than Spartan-3, which is > currently offered in only one speed-grade. If you need greater performance, > there are two more Cyclone speed grades available, giving you an additional > 30% performance advantage. Howdy Paul, I love competitive comparisons, and I love Altera for continuing to push the level of competition higher, but PLEASE, could you keep this FUD free? Xilinx tells everybody that the speed files that are released for the Spartan-3 are very preliminary and quite conservative, and I'm sure your tech people know that. This is bordering on the same level of FUD that I got from my Altera rep about some Virtex II availability or yield or some such nonsense early this year. > - 3.3V Tolerance. Cyclone is 3.3V tolerant, in today's silicon. PCI? No > problem. Not quite as misleading since you put "in today's silicon", but many would still walk away with the incorrect impression that the Spartan-3 will not be 3.3V tolerant. The truth is that it will be 3.3V by the time most people get their hands on them (due to the current limited availability of S3 ES silicon). > - Bitstream Compression. Regardless of your data source, you can compress > your bitstream (~2:1 ratio) to reduce the cost of your non-volatile storage > device, whether that is our low-cost, low-footprint serial configuration > devices or something else. Especially for larger devices, this is an excellent feature. We have a considerable amount of flash memory on our systems to hold all the FPGA loads, and it adds up quickly. I sure wish Xilinx had it. What about high speed I/O? Seems like you all don't push that nearly has hard as you should. What about listing a few of the major advantages of a non-digital PLL? Or perhaps you all have better clock to out on block ram's? Not to mention multiple sizes of them. All of these would be better talking points than some nebulous claim of being 30% faster than a part that is nowhere near released and whose claimed speed is known to be artificially low. Have fun, MarcArticle: 57673
Try http://www.Google.com SP <nowhere@nowhere.com> wrote in message news:<Xns93ADB437CEF1nowherenowherecom@216.109.160.14>... > Hello, > > I am looking for an ARM (preferably StrongARM) w/ FPGA development board. > StrongARM preference is for mainly for Linux. Any other supported processor > will do as well. > > Thanks a lot! > -SumeetArticle: 57674
In article <3F04660E.33F1EF2@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: > Cable Modem is a fixed installation, it can not be easily moved from > one computer to another. Cable Modem also goes out in nearly every > storm along with the TV. Which company? Our cable modem just gives an ethernet out which we plug into a simple NATing hub. -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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