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Messages from 57725

Article: 57725
Subject: Re: cyclone on pci?
From: Sander Vesik <sander@haldjas.folklore.ee>
Date: Fri, 4 Jul 2003 21:38:00 +0000 (UTC)
Links: << >>  << T >>  << A >>
Vaughn Betz <vbetz@altera.com> wrote:
> Sander Vesik <sander@haldjas.folklore.ee> wrote in message news:<1054761767.988243@haldjas.folklore.ee>...
>> Anybody know of Cyclone EP1C12 (preferably) or EP1C20 
>> (also ok) based PCI development boards? Do such things
>> even exist - or in other words, what is the approximate
>> timline after chip availability that one can expect such
>> to be around?
> 
> Altera will be shipping a Cyclone, 1C20-based PCI development kit
> soon.  Introduction is slated for late August.  Cost will be under
> $1000, and it will include DDR ram and be in a short board form
> factor.  Watch the Altera development kits page
> (http://www.altera.com/products/devkits/kit-dev_platforms.jsp) for
> details.

yay! cool! 8-) thanx.

> 
> Vaughn

-- 
	Sander

+++ Out of cheese error +++

Article: 57726
Subject: Re: Regarding NRZ
From: H. Peter Anvin <hpa@zytor.com>
Date: 4 Jul 2003 17:59:50 -0700
Links: << >>  << T >>  << A >>
Followup to:  <be2jpo$gtp$1@naig.caltech.edu>
By author:    "Daniel Lang" <dblx@xtyrvos.caltech.edu>
In newsgroup: comp.arch.fpga
>
> Hello,
> 
> NRZ (Non-Return to Zero) has only two signalling levels.  NRZI is a
> non-return to zero code where a 0 is represented by a transition in
> the signal and a 1 is represented by no transition.  Note that the
> NRZ codes are not inherently self clocking, either an external clock
> or some method of limiting the number of bit intervals with no
> transitions is needed.  See
> 

My apologies; I was confusing it with AMI (Alternate Mark Inversion).

	-hpa
-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64

Article: 57727
Subject: Re: NIOS tutorial for the Stratix1S10
From: Karsten Becker <KB@Karsten-Becker.de>
Date: Sat, 05 Jul 2003 04:12:30 +0200
Links: << >>  << T >>  << A >>
Hi,
As I did have some strange experiences with SOPC_BUILDER that look like 
a problem you actually have.
My first mistake was to place the SOPC_BUILDER at some place where it 
would have make sence. Don't do that. Keep the suggested directory.
Second mistake was, I uninstalled the SOPC_BUILDER and reinstalled it to 
different directories... There ist somewhere a file where the path to 
SOPC_BUILDER must be set correctly. Unfortunatly I don't rember which 
file it was.
Third mistake, Cygwin was not installed. There is an cygwin enviroment 
delivered with SOPC_BUILDER but it did not work for some reason on my 
computer.
Fourth mistake, I did not install the perl program delivered with 
cygwin. The one delivered with SOPC_BUILDER was not working.
Fifth mistake, when installing cygwin, always select that your files are 
in DOS LF mode. Otherwise you'll get compilation errors... I did get 
them anyway but that's a different story.
Last hint, make sure your enviroment variables are all correctly set.

Good luck,
Karsten


Article: 57728
Subject: Re: NIOS tutorial for the Stratix1S10
From: Karsten Becker <KB@Karsten-Becker.de>
Date: Sat, 05 Jul 2003 04:17:52 +0200
Links: << >>  << T >>  << A >>
Karsten Becker wrote:
> Second mistake was, I uninstalled the SOPC_BUILDER and reinstalled it to 
> different directories... There ist somewhere a file where the path to 
> SOPC_BUILDER must be set correctly. Unfortunatly I don't rember which 
> file it was.

I found the file. It is 
C:\altera\excalibur\sopc_builder\sopc_builder_2_7_wizard.lst


Article: 57729
Subject: Re: ACEX (EP1K) Power-Up Current
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 04 Jul 2003 23:33:19 -0400
Links: << >>  << T >>  << A >>
Greg Steinke wrote:
> 
> Rick,
> On your question on startup current - I don't know this offhand but
> will track this down with the hotline guy, as we don't want to
> duplicate effort.

I appreciate the effort.  I hope I can count on an answer from someone. 
I don't remember exactly when I called about this question, but it was
over a week ago I am pretty sure and may have been two.  

BTW, the only options for support are the web page which requires the
use of a form and agreement to a very long and difficult to read (on the
web) terms and conditions.  Is there some reason that Altera can't
provide a simple email address for support?  The web page does not allow
me to track the issue on my system as I can with email.  To be honest,
it is unlikely that I will sign up for the online support given the way
it works and the long agreement form.  So instead of using email, I will
be using the phone which I am sure is not Altera's favorite choice.  


> The other question about quiescent current:
> Your interpretation is correct. The 5 mA value applies to -2 and -3
> commercial-temp devices and -3 industrial/extended-temp devices, while
> the 10 mA value applies to -1 commercial-temp devices and -2, -3
> industrial/extended-temp devices. The spec applies to a configured
> part with no toggling inputs. We do not have a spec for the
> unconfigured part. In reality it may be slightly higher, but not much
> more.

Thanks for the answer, but you listed the -3 indust/extended devices in
both camps.  The -3 parts are all 5 mA, right?  Not that it matters a
lot.  The -3 parts don't provide fully functioning PLLs so I am specing
the -2 parts even though I don't need the speed.  

Thinking about how they are specing this parameter, I realized that
there are likely no EP1Kx-1 industrial parts or they would likely be 10
mA parts as well.  

BTW, I tried looking this up on the web page,
http://www.altera.com/products/devices/common/dev-avail_device_search.html

But it returned a .pl file type which the current version of Netscape
does not understand.  Is this a bug in the web page or a bug in the
browser?  

When I looked this up in IE, I found that there are *no* EP1K extended
temp parts and the EP1K industrial parts only come in -2 speed grade. 
Is this right?  I guess that is another reason to not use the -3 parts.  


> rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F047811.D824824C@yahoo.com>...
> > Since Altera seems to be active in this group, I will ask the question
> > here.  I have finally gotten an acceptable price on the EP1K30 part (5
> > volt tolerant) and will be using it in my design provided I don't step
> > on any landmines looking at the data sheet in fine detail.  One item
> > that is missing is the startup current.  I called support and got a
> > number of 194 mA.  But I asked if this was over temp and voltage and he
> > didn't know.  He said he would dig up the answer and get back to me
> > which never happened.
> >
> > So who can tell me the power-up current for the EP1K10, EP1K30, EP1K50
> > and EP1K100 in both commercial and industrial temp grade over
> > temperature and voltage?
> >
> > Also, I am not certain I understand the quiescent current spec on this
> > part.  There are two values, one has a footnote...
> >
> > ICC0 VCC supply current (standby)
> >
> > (12) This parameter applies to -1 speed grade commercial temperature
> > devices and -2 speed grade industrial and extended temperature devices.
> >
> > Does this mean the lower value (5 mA) without the footnote applies to
> > all other devices?
> >
> > Am I correct in assuming that this spec is for a configured part with no
> > clock as well as an unconfigured part?

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57730
Subject: Re: XPLA3 vs. MAX3000A
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 04 Jul 2003 23:42:42 -0400
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> 
> rickman wrote:
> >
> > Chris_S wrote:
> <snip> > The Altera people told me that a new CPLD family is coming out
> soon.  It
> > > will be lower power.  Sounds like Altera has gotten very sick of hearing
> > > their parts are current hogs.
> >
> > Did they give you a schedule by any chance?  If they don't have a
> > schedule then you shouldn't expect it within the year.  Oh, yeah, don't
> > expect it to be 5 volt tolerant.  If you only need LVTTL, then you
> > should be ok, but all newer devices are 5 volt phobic.
> 
>  Not entirely - the new Lattice devices offer 5V tolerance, but they
> also spec 'no more than 32 IO' at a time.
>  Strange spec, how does one IO 'know' the state of another ?!

That is 64 IOs at once and each one sinks current.  Seems the total
current sets the limit.  I tried to get more detail on this to find a
way to use it with the PC/104 bus, but they kept telling me to consider
a different family.  Oh, well, I guess I have found another family, it
is not a Lattice one however.  


>  On some devices the IO tolerance is spec'd also CORE relative, so
> you can get caught if your IO power is present, and the core
> voltage is not!

On both the Lattice LCxxxx lines and the Xilinx XCR3xxxXL parts the 5
volt tolerance is not there when the voltage is not there (Vio in the
case of Lattice, IIRC).  So don't consider using either in hot swap
apps.  


>  Lattice appear to be using on-chip regulators, so the multi-rail dance
> is showing signs of simplifying. The regulator is a bit 'ordinary', so
> the
> Icc goes up on those variants.
>  There are uC being released with regulated core voltages (eg
> AT89C51ED2)
> so that is a sensible solution, esp for the smaller CPLD's

Depends on your app.  If you are running on batteries, then the internal
LDO is not a good option.  In the case of the Lattice parts your static
current is much higher with the internal regulated parts.  If I want to
use an LDO, I can get a unit with <100 uA of standby current, a major
improvement over the mAs of the internal versions.  I was going to use
the 2.5 volt version since I have a switcher generated voltage available
and this would improve my efficiency over the 3.3 volt version.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57731
Subject: Re: XPLA3 vs. MAX3000A
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 04 Jul 2003 23:49:31 -0400
Links: << >>  << T >>  << A >>
Chris_S wrote:
> 
> Looking at the Lattice parts,  the Mach 4A3 or Mach 4000 would be
> candidates.  I like the 4000, but there is almost no stock in the supply
> chain yet.  Arrow has only a couple parts moving and Avnet has virtually
> none.  Does not seem to have many designs going with it yet.
> 
> Another problem with the 4000 is lack of packages.  I really need a PQ208
> but there are none in the 4000 at all.  Very few choices and little or no
> stock even on those.
> 
> The 4A3 is a possibility. There are 10 times as many parts moving through
> the dists and the family has 8 different devices with lots of packages.  But
> the Icc is much higher on that series than the 4000.  The factory tells me
> that the 4000 will be more expensive than the 4A as well.
> 
> I guess if you want to design for the long term future it's probably best to
> pick a new family like the 4000.  But you never know until later if that new
> family makes it or not in the market.

Exactly which new families did not "make it" in the market?  I don't see
any reason to expect the LC4000 (which is what I believe you are calling
Mach 4000) will not be here as long as any other PLD family.  This is a
sound part and has some very good features.  As to price, I have gotten
much better pricing on the Lattice parts than I have on the Xilinx CR
ones.  Once the size gets up a bit, the CR parts get very, very
expensive.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57732
Subject: Re: Xilinx ISE drops support for more parts
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 04 Jul 2003 23:51:56 -0400
Links: << >>  << T >>  << A >>
Thomas Heller wrote:
> 
> Steve Lass <lass@xilinx.com> writes:
> 
> > Jim Granville wrote:
> >
> >> Can we get a quick summary of what's removed, and what legacy
> >> versions of SW are needed to support which family ?
> >>
> > The current software (version 5.1i, 5.2i, 6.1i) supports Virtex,
> > Virtex-E, Virtex-II, Virtex-II Pro, Spartan II, Spartan IIE, and
> > Spartan-3.
> > ISE Classics (version 4.2i) supports XC4000E, XC4000L, XC4000EX,
> > XC4000XL, XC4000XLA, Spartan, and SpartanXL.
> >
> > Contact the hotline if you need software for:
> > 3.1i supporting XC3000A, XC3000L and XC5200.
> > XACT 6 supporting XC2000, XC3000, and XC4000, XC4000A and XC5200.
> 
> This sounds like I better terminate my Xilinx software subscription, and
> use the free versions instead.
> 
> I recently changed my PC to a new one, and tried to install the licensed
> version of ISE 4.2, because I need Spartan and Spartan XL.  It was a
> pain to make it work again because one design uses FPGA express, and it
> always complained about the license being invalid.
> 
> The only solution was, as a Xilinx FAE told me, to use use tool to
> change the volume serial number of my hard disk to the one that the old
> PC had. Fortunately I didn' have to reregister Windows XP again.

Which tool did you find that would let you change the disk serial
number?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57733
Subject: Re: Spartan-3 availability
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 04 Jul 2003 23:56:47 -0400
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:
> 
> Manfred Kraus <news@cesys.com> wrote:
> : I got a call from Insight. Of course I can get samples of the ESJ-part
> : immediately.
> : The Problem was, that I didn't ask for ESJ-Parts. They assumed I know what
> : to ask for.
> 
> The problem is also, that distributors often ask for an exact number, while
> the user mostly needs _any_ part with only few constraints. That way, you
> have to prepare a lot of fallback fits, and ask the distributor for each.
> 
> If they could cope with wildcards in the part number, things would be
> easier...

You are looking at using some 30 to 100 parts on your board.  The distis
have to deal with thousands of parts every day.  It is very hard for
them to keep up with what means what in the part numbers.  It is much
better if you tell them the variations in part numbers that you can work
with.  Normally the only option you have is a faster speed or a wider
temperature (which often does not make a part *more* available).  I have
been able to give them a starting part number and tell them that this
letter is a don't care and they can tell me what is up with inventory
and product volume.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57734
Subject: Re: XPLA3 vs. MAX3000A
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Sat, 05 Jul 2003 16:50:25 +1200
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> Jim Granville wrote:
> >
> >  Not entirely - the new Lattice devices offer 5V tolerance, but they
> > also spec 'no more than 32 IO' at a time.
> >  Strange spec, how does one IO 'know' the state of another ?!
> 
> That is 64 IOs at once and each one sinks current.  Seems the total
> current sets the limit.  I tried to get more detail on this to find a
> way to use it with the PC/104 bus, but they kept telling me to consider
> a different family.
<snip>

 Where did you find the sink current info/value - from the FAE ?

I get this info from their Data:

#5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
#
#IIH  2 Input High Leakage Current
#    3.6V < VIN = 5.5V, Tj = 105C      <= 20 A
#    3.6V < VIN = 5.5V, Tj = 130C      <= 50 A

 So that does not look to me like a clamping diode, which is how
some others get their '5V tolerance'  (just add a resistor :)

 Still leaves open the question of why a finite limit on the 
NUMBER of IO's that can have > 3.6V applied.

 It sounds tempting to get a device, and take 65 IO's to > 3.6V, and 
watch what happens :)) 

 -jg

Article: 57735
Subject: division
From: ketone007sa@yahoo.com (Ketan)
Date: 4 Jul 2003 22:30:54 -0700
Links: << >>  << T >>  << A >>
hello there
i am relatively new to VHDL..this might sound simple
any ideas how to carry out division (floating point) in VHDL??

Article: 57736
Subject: Re: information required
From: Guest <>
Date: Fri, 4 Jul 2003 23:36:03 -0700
Links: << >>  << T >>  << A >>
Dear Mr.Avrum, 

Thanks, Iam using xilinx FPGA and 155.55HMz for communication. 

I have connected as like below 

Xilinx FPGA (transmitter) ----> (connector & Back plane trace) ----) connector --> xilinx FPGA (receiver) 

I have not used any capacitor in between the path, i have used the xilinx recommended termination tequnique
bwteen them, I have used a data recover block as said in Xilinx application note at the receiver. 

Still do i need to use 8B/10 b or scrambling to remove DC offset tdue to the capacitance
effect of the transmission line (copper trace through backplane) ? 

Thanks in Advance,

Article: 57737
Subject: hidden remap failed
From: Thomas <tom3@_nostupidspam_protectedfromreality.com>
Date: Sat, 05 Jul 2003 08:54:57 GMT
Links: << >>  << T >>  << A >>

when trying to do a simulation, I get this:

Completed process "Generate Post-Translate Simulation Model".

ERROR: Hidden remap failed
Reason:

Launching Application for process "Simulate Post-Translate VHDL Model".

not only it doesn't display a reason, but the program's so stupid it still 
runs the simulator;
has anybody gotten a similar error?


the generate expected result simulation didn't fare much better as HDL 
bencher generates an invalid script.

this happened when I started to introduce new types in the code


note to xilinx: your software guys should be locked away from computers; 
just outsource the tools to people that know how to write software...





Article: 57738
Subject: Re: hidden remap failed
From: Thomas <tom3@_nostupidspam_protectedfromreality.com>
Date: Sat, 05 Jul 2003 09:17:29 GMT
Links: << >>  << T >>  << A >>
I did some more tests and realized that hdl bencher doesn't generate proper 
scripts when I use custom types;
has anybody found a workaround?


On Sat, 05 Jul 2003 08:54:57 GMT, Thomas 
<tom3@_nostupidspam_protectedfromreality.com> wrote:

>
> when trying to do a simulation, I get this:
>
> Completed process "Generate Post-Translate Simulation Model".
>
> ERROR: Hidden remap failed
> Reason:
>
> Launching Application for process "Simulate Post-Translate VHDL Model".
>
> not only it doesn't display a reason, but the program's so stupid it 
> still runs the simulator;
> has anybody gotten a similar error?
>
>
> the generate expected result simulation didn't fare much better as HDL 
> bencher generates an invalid script.
>
> this happened when I started to introduce new types in the code
>
>
> note to xilinx: your software guys should be locked away from computers; 
> just outsource the tools to people that know how to write software...
>
>
>
>
>



Article: 57739
Subject: Re: Xilinx ISE drops support for more parts
From: hamish@cloud.net.au
Date: 05 Jul 2003 10:28:19 GMT
Links: << >>  << T >>  << A >>
Rainer Buchty <buchty@atbode100.informatik.tu-muenchen.de> wrote:
> In article <3f042929$0$23100$5a62ac22@freenews.iinet.net.au>,
> hamish@cloud.net.au writes:
> |> I don't think dropping support for old devices is too unreasonable.
> |> Otherwise the QA effort for each new software version (major, minor,
> |> even service pack) just grows bigger and bigger, and the design of
> |> the software gets more complex and messier etc.
> 
> Why would this be so? If the software is modularized, e.g. the fitter
> (placer/router) is its very own piece of command-line software there is
> no need to touch that code again (plus, doing so eases portability).

But can you be sure that it's completely standalone and won't need any
QA? Have you changed any of the toolchain used to build the tools
themselves? There's lots of things that could go wrong, requiring QA,
which is expensive.

> If integration of the necessary calls into the GUI is an issue, well, then
> just leave it out. From what I read in this and other "tech" groups, 
> developers seem to prefer to write their own batch scripts anyway. (If 
> the shared development machines sit "two networks further", you don't
> want to wait for GUI updates anyway.)

But the same people who can write those scripts can make multiple ISE
versions co-exist; it's trivial. I suspect it's the GUI users
complaining about old tools being dropped.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 57740
Subject: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
From: antti@case2000.com (Antti Lukats)
Date: 5 Jul 2003 04:19:49 -0700
Links: << >>  << T >>  << A >>
"tk" <tokwok@hotmail.com> wrote in message news:<be454t$62s$1@www.csis.hku.hk>...
> so good that Xilinx sent you the example
> i'm interested in it, can u send me (email: h0013252@eee.hku.hk) a copy ?
I will forward your request to the person I got it from (at least)
 
> i'm now finding out how to build (glue all the IP cores needed) an embedded
> system environment for the MontaVista Linx (Pro 3.0) to work on, do you
> know any reference about that (so as to build an embedded Linux similar
> to the one on ML300) ?

just ask (again) xilinx support, there have been promises that a EDK 3.2
project capable to boot linux will be made available, maybe its wiser to
wait :)

FYI I glued the obsoleted (in EDK) LCD TFT core to the DDR example and
well I think I get it working well I had wrong clock (100MHz!) , wrong
start address (0) and wasnt yet able to compile use the tft library,
but after fixinf those problems I think it does work - with memory
test i did see 'visual picture of memory fill' :)

> in Linux by mounting the FAT partition (it's "/dev/xsysace/disc0/part1" in

tnx, it would have taken me long tofigure this out !!!!

Article: 57741
Subject: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
From: "tk" <tokwok@hotmail.com>
Date: Sat, 5 Jul 2003 20:35:13 +0800
Links: << >>  << T >>  << A >>
thx a lot for your help !!!

tk

"Antti Lukats" <antti@case2000.com> ?????
news:80a3aea5.0307050319.6eaabe59@posting.google.com...
> "tk" <tokwok@hotmail.com> wrote in message
news:<be454t$62s$1@www.csis.hku.hk>...
> > so good that Xilinx sent you the example
> > i'm interested in it, can u send me (email: h0013252@eee.hku.hk) a copy
?
> I will forward your request to the person I got it from (at least)
>
> > i'm now finding out how to build (glue all the IP cores needed) an
embedded
> > system environment for the MontaVista Linx (Pro 3.0) to work on, do you
> > know any reference about that (so as to build an embedded Linux similar
> > to the one on ML300) ?
>
> just ask (again) xilinx support, there have been promises that a EDK 3.2
> project capable to boot linux will be made available, maybe its wiser to
> wait :)
>
> FYI I glued the obsoleted (in EDK) LCD TFT core to the DDR example and
> well I think I get it working well I had wrong clock (100MHz!) , wrong
> start address (0) and wasnt yet able to compile use the tft library,
> but after fixinf those problems I think it does work - with memory
> test i did see 'visual picture of memory fill' :)
>
> > in Linux by mounting the FAT partition (it's "/dev/xsysace/disc0/part1"
in
>
> tnx, it would have taken me long tofigure this out !!!!



Article: 57742
Subject: Re: Why not DDR in FPGAs?
From: hamish@cloud.net.au
Date: 05 Jul 2003 14:29:52 GMT
Links: << >>  << T >>  << A >>
Steven K. Knapp <steve.knappNO#SPAM@xilinx.com> wrote:
> For high-performance applications, you would want to use two outputs from
> the Digital Clock Manager, one being the de-skewed, non-shifted clock output
> and the de-skewed, 180 degrees phase-shifted clock output.  This technique
> minimizes any potential duty-cycle distortion and gives you most of the
> entire half-period for your logic application.

... but takes twice as many BUFGs.

Feature request: more BUFGs.

Grip: differential clocks take two global clock pins. It would be better
if they took one global clock pin and the other pin in the differential
pair was a standard I/O pin. I don't know if that is feasible, but
differential clocks chew IBUFGs quickly.

On the project I'm currently working on we ran out of global clock pins
this way and put one of our clocks on a non-global pin. Works fine.
Our experience shows that it's preferable to have differential clocks
even on non-clock pins than to use single-ended clocks.


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 57743
Subject: Re: Excel and FPGA's
From: hamish@cloud.net.au
Date: 05 Jul 2003 14:34:48 GMT
Links: << >>  << T >>  << A >>
In comp.arch.fpga enrique.laserna@web.de wrote:
> You guys should also look into Innoveda's Visual hdl (Now bought by 

Why should we?


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 57744
Subject: Re: Excel and FPGA's
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Sat, 05 Jul 2003 15:18:59 GMT
Links: << >>  << T >>  << A >>
Hi - 

On 03 Jul 2003 13:54:21 GMT, enrique.laserna@web.de wrote:

>You guys should also look into Innoveda's Visual hdl (Now bought by 
>Mentor, I think). It translates State Machines, Flow Diagrams, FSM into 
>Verilog, vhdl and SystemC. All ready for synthesys.

Well, maybe.  But I've felt for years that my chances of getting a
design to work are inversely proportional to the number of tools
between me and the target device.

Bob Perlman
Cambrian Design Works 

Article: 57745
Subject: Re: Quartus II 3.0 Release & Web Edition Download Links
From: "Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl>
Date: Sat, 05 Jul 2003 15:56:41 GMT
Links: << >>  << T >>  << A >>
Hi Valeria,

> Windows9x is no more supported?

Nope. Then again, if you're doing any serious development, W98 is not really
the right platform.

Best regards,


Ben



Article: 57746
Subject: Re: Quartus II 3.0 Release & Web Edition Download Links
From: "Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl>
Date: Sat, 05 Jul 2003 16:01:33 GMT
Links: << >>  << T >>  << A >>
Hi Leon,

> why altera doesn't provid QuartusII Web Edition for Linux?

I wouldn't mind either, but they are licensing the GUI libraries from
another company and they have to pay a substantial sum of money per copy of
Quartus [whatever edition] running at a customer, so they won't be giving a
Linux GUI for free.

Once the documentation for it is out you may want to learn about Quartus
scripting, and then start asking for free Linux Web Edition command-line
tools. At least those do not share this third-party stuff.

Best regards,


Ben




Article: 57747
Subject: Re: XPLA3 vs. MAX3000A
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 05 Jul 2003 12:02:57 -0400
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> 
> rickman wrote:
> >
> > Jim Granville wrote:
> > >
> > >  Not entirely - the new Lattice devices offer 5V tolerance, but they
> > > also spec 'no more than 32 IO' at a time.
> > >  Strange spec, how does one IO 'know' the state of another ?!
> >
> > That is 64 IOs at once and each one sinks current.  Seems the total
> > current sets the limit.  I tried to get more detail on this to find a
> > way to use it with the PC/104 bus, but they kept telling me to consider
> > a different family.
> <snip>
> 
>  Where did you find the sink current info/value - from the FAE ?
> 
> I get this info from their Data:
> 
> #5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
> #
> #IIH  2 Input High Leakage Current
> #    3.6V < VIN = 5.5V, Tj = 105C      <= 20 A
> #    3.6V < VIN = 5.5V, Tj = 130C      <= 50 A
> 
>  So that does not look to me like a clamping diode, which is how
> some others get their '5V tolerance'  (just add a resistor :)
> 
>  Still leaves open the question of why a finite limit on the
> NUMBER of IO's that can have > 3.6V applied.
> 
>  It sounds tempting to get a device, and take 65 IO's to > 3.6V, and
> watch what happens :))

I was told this by both an FAE and support by email.  I am sure both are
just parroting whatever is the original source of the info.  I could not
get them to give me any more detail, such as what effect a series
resistance or other source impedance would have on the spec.  


From the FAE...
"You are correct, the 5512MB does have a limit of 64 IOs that can be
driven above 3.6V.  This is due to the leakage current that appears when
an input is biased above VCCio.  They need to keep the total amount of
this leakage current below a certain number and that worked out to 64
IOs."

From support...
"The 64 IOs 5V restriction is a reliability requirement for EE9
technology to ensure that we meet oxide FIT rate requirement."


You could do your own testing on a device, but how would you know that
this will be consistant across future versions of the device?  It is not
at all uncommon for a company to alter their process while keeping the
original published spec.  Xilinx has discussed this recently on the
SpartanXL.  While they maintained all the publised specs (and improved
some), anything that you have tested in the past may no longer function
that way. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 57748
Subject: Xilinx:CAM
From: Alex <luwork@hotmail.com>
Date: Sat, 5 Jul 2003 09:22:26 -0700
Links: << >>  << T >>  << A >>
Hi, all, I am implementing an on-chip 16*32 CAM using Xilinx Select 
RAM(applicatin notes 204 or 260). I am wondering why a register is added 
to each of the input and output. When I simulate the design in Modelsim, 
there  is always two clock cycles' delay, one for the input register and one 
for the output register, I guess. So if I specify the data to match, the 
match output signal will appear after two clock cycles. I don't think it 
is a correct implementation. Any one has idea about this? 

Thanks for your answers! 

regards, 

Alex

Article: 57749
Subject: QuartusII software licencing
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 05 Jul 2003 12:44:59 -0400
Links: << >>  << T >>  << A >>
I just tried to install the Quartus II web edition software and I see
that to get a license I need to have an Ethernet card.  Does Altera
provide for any other sort of license?  It seems silly to require me to
buy and install an Ethernet interface just so they can key a license for
*free* software.  

Also, I noticed that they have version 3.0 out.  I ordered version 2.2
on a CD, but I can't find the link on the Altera web site to order the
new version on CD.  Anyone know where that is?  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



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