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>>If there is an Ethernet card in the machine, I can't assure my customers >>that it will not be connected in a forgetful manner. > >Why not take the ethernet card and attack the connector with >wirecutters? You get a MAC address but the net don't work. :) I was going to suggest bubble gum. Might need epoxy for govt work. :) How does not having an ethernet card solve anything interesting about the integrity of the system? Have virus writers given up on floppies now? How does a good anti-virus (with auto-updates) compare to a no-network machine? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 57926
Fred, It's more than just the software, you also have to understand the hardware... :-) There is only a Q output from the flip-flop. Just use an inverter. You can clock and reset the flip-flops from either dedicated signals or from global nets. There are restrictions on the global reset net. I don't know about schematics, but in VHDL if you use *any* asynchronous clear in your design, ISE will use the normal routing resources for the reset. If you have *no* asynchronous resets, the global reset net will be used. The best pin to use for the clock is the dedicated clock pin. The best (and only) pin to use for the global reset net is the dedicated global set/reset pin. Marc juice28 wrote: > Could someone please let me in on how the Flip Flops work in ISE Webpack > schematics. Where is the Q/ . Do I simply run an inverter off from Q or > what. Are these also global clk and rst or only if you assign them that way. > When running a clock into the chip for a design (say 6mhz) which pin is best > to use? Sorry for all the Newbe questions but this stuff is hurting my > head.... Man why can't they just use easy software like Palasm :) > > Thanks, > > Fred > > > -- Marc Guardiani To reply directly to me, use the address given below. The domain name is phonetic. fpgaee81-at-eff-why-eye-dot-netArticle: 57927
On Tue, 8 Jul 2003 14:33:20 +0200, "Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote: >Hello, > >I want to make a phase measurement at 100MHz with a NCO at 200+ MHz >This NCO will have a 32 bit phase accumulator and a 32 bits phase offset. The >output will be only one bit. >I will use a phase comparator followed by an integrator (digital or analogic >if needed). >At 100MHz the NCO output will be very very noisy but if I integrate it for a >rather long time (10ms) will it have a 0 mean ? >Can I implement this in an FPGA or should I use a DDS chip (AD9854) ? >Where can I find some maths on this subject ? > >Thanks > >Marc Battyani > I've used the Ad9954 DDS and the phase noise is about -140dBc/Hz @ 10KHz 0ffset. Your clk ref needs to be better than that if you want an accurae measurement. I used a DRO for the reference and an Agilent E5500 phase noise test set to measure it. Download the Analog Devices dds tutorial for all the math involved.Article: 57928
John wrote: > > Rick, > > In article <3F0C25FB.7BC1C0C9@yahoo.com>, spamgoeshere4@yahoo.com > says... > > Falk Brunner wrote: > > > Get a download manager like Gozilla or something. The can resume a aboarded > > > download. > > > > My concern is that once installed, I will have no way to control it if I > > don't want to use it for some files. I remember Netscape adding > > something like this (or I added some download, I can't remember which). > > There were times I did not want it to pop up and could not find a way to > > turn it off. It also showed ads while running. > > > > Anyone know of a review of download utilities that would help me pick > > one? > > WGET! > > Wget does it all and it's open source, doesn't include spyware, works > really really well (hey, some of us HAVE been on dial-up too). Thanks. A couple of others have suggested WGET. I'll take a look. Is this available for Windows without having to use Cygwin? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57929
I need to select a Configuration solution for programming the Spartan XL XCS10XL device. I have chosen to use the Master Serial Mode configuration using the PROM XC17S10XL, which is OTP. I havent found any reference to ISP (EPROM) solutions for the Spartan XL and hence need some advice on this. I know there is this device XC18V256PC20C, but Xilinx mentions that this is not supported anymore. Thanks and regards Anup --Article: 57930
Hal Murray wrote: > > >>If there is an Ethernet card in the machine, I can't assure my customers > >>that it will not be connected in a forgetful manner. > > > >Why not take the ethernet card and attack the connector with > >wirecutters? You get a MAC address but the net don't work. :) > > I was going to suggest bubble gum. Might need epoxy for govt work. :) > > How does not having an ethernet card solve anything interesting > about the integrity of the system? Have virus writers given up on > floppies now? How does a good anti-virus (with auto-updates) > compare to a no-network machine? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. I should have used the term "security" rather than just virus. Virus attack is just one way to mess with a system. But if the machine gets connected to a network that is connected to the outside, any number of things can happen. Sure, there is software available that can help minimize or prevent damage, but it is *never* foolproof. Making sure the machine is not connected to a network is a *much* more sure way of stopping such problems. Of course anytime you insert a data disk you need to verify that it does not contain a virus. But that is a much smaller job if you are not connected to a network. Also, no anti-virus software is ever up to date, by definition. Any *new* virus will not be addressed by the software no matter how often you update. But then I am not trying to achive 100% protection. I am just trying to take a few simple measures that get very close to 100%. Certainly not having an Ethernet card in a computer should not make the machine worthless for running free CAD software. In any event, the issue is moot. Altera has already provided for disk serial number keying, they just have not put it on the web site (or even told their support people about it). Seems it was not availble before because some of the synthesis software required a NIC keyed license file due to contractual reasons. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57931
Google is your friend: http://vertigo.hsrl.rutgers.edu/ug/make_help.html Ciao, Peter K. -- Peter J. Kootsookos "Na, na na na na na na, na na na na" - 'Hey Jude', Lennon/McCartneyArticle: 57932
Hi every body, I want to have any suggestion from somebody who designed a kind of soft-decision decoding algorithm. I have a little problem with some notions. I'm trying to design a new codec with soft-decision,i'll use this example: 011 is the most significant 0 in my design, and 010 is less significant and so on till 000 who is the worst 0. Same thing for 1, 111 is the most confident one, and then whe have 110,101,100. The problem is that i'm using an addition to have a weighed evaluation of ny symbol. I have to add 4 symbols that are over 3 bits so to avoid the overflow my output is over 5 bits. In some case i can have a zero at the end of my adder and i have to feed it back to my input so i have to resize it over 3 bits (kind of saturation will work) but how can i deal with the zero that i don't use in my symbols and that i can't use ( both 100 and 000 are in decimal -1 and +1 so ...:(_ ) Any suggestion or question? thanks for any help -- Composed with Newz Crawler 1.4 http://www.newzcrawler.com/Article: 57933
Prashant wrote: > Hi, > > I have been using Quartus II 2.0 for all my synthesis and fitting > needs for the APEX20KE device I have on my prototype board. I hear > that Quartus is not an efficient synthesizer compared to Synplicity's > Synplify. Now, I have had trouble trying to fit my design on the FPGA > and I have tried various methods to achieve successful fits > (Logiclock, design change, etc.). > > Would there be a discernible advantage (in terms of achieving the > required performance and fitting the design on the device) to using > Synplify for synthesis and then using Quartus II 2.0 for placement and > routing ? Can this process really solve my fitting problems ? The answer to your question is yes. It's our business to give better results more easily and we put a lot of effort into it. The hierarchical routing structure of the APEX20KE can make delays very sensitive to the amount of area consumed in critical parts of your design. Being area efficient while optimizing the critical path can make a big difference. If things are really tight then you can use our physical synthesis tool Amplify. We can usually get an additional 15-25% improvement in frequency with Amplify. (The critical path has to go through logic we can optimize. Sometimes the critical path is mostly inside an IP block.) Another part of our tools is being able to show you performance problems in terms of your RTL. You may be a small change away from solving your problem, but it may be hard to figure out what needs changing. Our HDL Analyst and Timing Analyst features can be quite useful for this. It is easy to try an eval license. Just download, install and send in the license request. http://www.synplicity.com/downloads/index.html > > Thanks, > Prashant >Article: 57934
Jon wrote: > Hi Khan, > If you declare a signal in a package and you include the package > then the signal can be globally used by all architectures that > reference that package. This is for simulation only and will not > work for synthesis. This will work for synthesis in Synplify Pro 7.3. > > Jon > > > kalimuddin@hotmail.com (Muhammad Khan) wrote in message news:<7d350237.0307090951.775cbfe9@posting.google.com>... > >>Hello everybody, >> >>I want to use the signal defined in one architecture in VHDL to >>another architecture. I have two architecture in the same .vhd file >>and I am using Component mapping. I required the result of calculation >>of a signal to be used in second architecture. Can any one tell how to >>defined signal so that it is globally visible to other architectures. >> >>Regards >> >>Khan >>Article: 57935
Marc, Thanks for taking the time to reply. I have a pretty good understanding of digital design, but this stuff is a bit foreign to me. I am starting to grasp the idea of how they work and how to design a circuit in the schematics editor and burn it, but the vhdl part I fear I will never understand. It also seems that the Xilinx software is very picky and buggy. I am unfortunatly using a old version as its the only one I could get running on my win 98 computer. I think its version 3.1 The Flip flops in the schematics don't tell you if they clock on pos or neg clock cycle or if the enable is pos or neg. I assum the logic such as ands and ors are positive logic. Any ideas on this. Thanks again for your help. Fred "Marc Guardiani" <marc@guardiani.com> wrote in message news:7IycncIHnbQcJZGiRTvUqA@fyi.net... > Fred, > > It's more than just the software, you also have to understand the > hardware... :-) > > There is only a Q output from the flip-flop. Just use an inverter. > > You can clock and reset the flip-flops from either dedicated signals or > from global nets. There are restrictions on the global reset net. I > don't know about schematics, but in VHDL if you use *any* asynchronous > clear in your design, ISE will use the normal routing resources for the > reset. If you have *no* asynchronous resets, the global reset net will > be used. > > The best pin to use for the clock is the dedicated clock pin. > > The best (and only) pin to use for the global reset net is the dedicated > global set/reset pin. > > Marc > > juice28 wrote: > > Could someone please let me in on how the Flip Flops work in ISE Webpack > > schematics. Where is the Q/ . Do I simply run an inverter off from Q or > > what. Are these also global clk and rst or only if you assign them that way. > > When running a clock into the chip for a design (say 6mhz) which pin is best > > to use? Sorry for all the Newbe questions but this stuff is hurting my > > head.... Man why can't they just use easy software like Palasm :) > > > > Thanks, > > > > Fred > > > > > > > > -- > > > Marc Guardiani > > To reply directly to me, use the address given below. The domain name is > phonetic. > fpgaee81-at-eff-why-eye-dot-net >Article: 57936
vhdl_uk@yahoo.co.uk (MACEI'S) wrote in message news:<fdfcada5.0307090919.268c6b17@posting.google.com>... > Hi Fellows, > > How can I synthesize multiple file one by one using xilinx compiler in > MAKEFILE script. I have done using only one file but when I enter > multiple files in "VHDL= ....." field thenI get the following error. > > make: *** No rule to make target `VIR3.vhd,VIR3_1.vhd,VIR3_2.vhd > > Rgds > > MACEI Well, you should definitely get the makefile hand book - it has to many options ... But, to summarize, you probably want something like this: VHDL=VIR3.vhd VIR3_1.vhd VIR3_2.vhd # no commas ! $(VHDL): synthesis_command $@ replace "synthesis command" with the name of your synthesis tool. The "$@" will be automatically replaced with the vhdl file names. Regards, rudi -------------------------------------------------------- www.asics.ws --- Solutions for your ASIC/FPGA needs --- ----------------- FPGAs * Full Custom ICs * IP Cores --- FREE IP Cores --> http://www.asics.ws/ <-- FREE IP CoresArticle: 57937
Dear Sir, Thanks, is it ok if i designed with DC coupling for 155.54 MHz serial LVDS link or do i need to use AC coupling. I have used Xilinx termination technique (resistor network) at both transmitter (SpartanIIE FPGA used) and receiver (spartanIIE FPGA used). Is the design will work for above configuration, Thanks in Advance, Regards, KarthikArticle: 57938
"juice28" <arcadexpo@mchsi.com> wrote: > Thanks for taking the time to reply. I have a pretty good understanding of > digital design, but this stuff is a bit foreign to me. I am starting to > grasp the idea of how they work and how to design a circuit in the > schematics editor and burn it, but the vhdl part I fear I will never > understand. It also seems that the Xilinx software is very picky and buggy. > I am unfortunatly using a old version as its the only one I could get > running on my win 98 computer. I think its version 3.1 Having only about 18 months experience with FPGA's I can certainly understand what you are going through. Once your brain snaps into the whole concept and you become comfortable with the tools and IF (and only if) you know pre-FPGA digital design, very soon you find youself thinking in terms of hardware constructs as opposed to a confusing no-man's land of software that actually means hardware. I don't think schematic entry is useful for but a very narrow family of designs. I just couldn't see designing and maintaining (perhaps more important) a complex state machine with schematic entry. An HDL description, for me, is a significant improvement. I spent hundreds of dollars on books in the begining to try to learn about both Verilog and VHDL. In the end, I chose Verilog because my barrier to entry (intellectual, that is) was practically nil. It felt like C and I could dive right in. It also seemed like every VHDL example or app note out there was twice as long as the corresponding Verilog code. At the point of decision, and from my vantage point, I truly had no time/energy to deal with this. These are personal choices, I don't want to start a Verilog vs. VHDL war here. Anyhow, if you know C I'd recommend you start with Verilog. I've acually noticed that I've been picking up VHDL as I go because of things like reading this NG every day as well as both the VHDL and Verilog NG's. Once you understand the "standard" constructs it is relatively simple. In terms of books, I'd recommend "Real World FPGA Design with Verilog" by Ken Coffman; "Verilog Designer's Library" by Bob Zeidman and "Verilog HDL Synthesis" by J. Bhasker. My approach was to concentrate on the synthesizable part of the language almost exclusively from the start. Get a simple little evaluation board (Avnet and Memec have interesting oferings) and play with the most basic circuits you can think of. It was a natural transition to add the simulation arsenal to what is learned in synthesis. Simulation is invaluable. A very important tool. That's another thing that might be hard to get used to if you come from old-school design. Now you get to write software to simulate your hardware and software to simulate what your hardware should do. Marry both of those pieces in simulation runs to figure out where the bugs might be. Regarding such things as where to run clocks into, etc. You really need to spend time reading through the data sheets and manuals for the parts you are using. It is spelled out in great detail there. You also need to familiarize yourself with the chip's infrastructure and logic resources. You can damage a design (performance/space-wise) by not knowing how to take advantage of the resources intelligently. Treat FPGA documentation like you used to treat data books for non-programmable technologies. Make them a part of your life. It is not impossible if you apply yourself. It took me six months to design my first FPGA-equipped board. The first article ($30,000) worked right off the assembly line with multiple clock domains running upwards of 160MHz. Realize that the frustration is due to being in unfamiliar territory. Finally, in terms of learning, there are tons of resources on the Web. Explore the Xilinx site. In terms of ease of use it is one of my least-liked sites on the 'net, convoluted, confusing. It can be a chore to find what you are looking for ... but there's a lot there. Their university program/site (http://xup.msu.edu/index.htm) is a good resource for beginners. If you can find it, somewhere in the Xilinx site there's a tutorial titled "Programmable Logic Design Quickstart Handbook", it is a good newbie-read. Also, check out the Aldec tutorials: www.aldec.com ... and one day you'll have the pleasure of burning three weeks trying to figure out why "perfectly good code" isn't working and, all of a sudden you'll realize METASTABILITY!!! And you'll remember that after the smoke and BS clears out you are still dealing with high-gain amplifiers ... millions of them. Enjoy the ride. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 57939
Hey thanks for the encouragement. I think you are right it just takes time to get intimate with this new type of device. I am getting older and forgetting many a night falling alseep with datasheets stuck to my forehead :) I better get unboard before this old dog can't learn any new tricks.... haha Thanks again, Fred "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:Ut7Pa.159$ET6.13689029@newssvr14.news.prodigy.com... > "juice28" <arcadexpo@mchsi.com> wrote: > > > Thanks for taking the time to reply. I have a pretty good understanding of > > digital design, but this stuff is a bit foreign to me. I am starting to > > grasp the idea of how they work and how to design a circuit in the > > schematics editor and burn it, but the vhdl part I fear I will never > > understand. It also seems that the Xilinx software is very picky and > buggy. > > I am unfortunatly using a old version as its the only one I could get > > running on my win 98 computer. I think its version 3.1 > > Having only about 18 months experience with FPGA's I can certainly > understand what you are going through. Once your brain snaps into the whole > concept and you become comfortable with the tools and IF (and only if) you > know pre-FPGA digital design, very soon you find youself thinking in terms > of hardware constructs as opposed to a confusing no-man's land of software > that actually means hardware. > > I don't think schematic entry is useful for but a very narrow family of > designs. I just couldn't see designing and maintaining (perhaps more > important) a complex state machine with schematic entry. An HDL > description, for me, is a significant improvement. > > I spent hundreds of dollars on books in the begining to try to learn about > both Verilog and VHDL. In the end, I chose Verilog because my barrier to > entry (intellectual, that is) was practically nil. It felt like C and I > could dive right in. It also seemed like every VHDL example or app note out > there was twice as long as the corresponding Verilog code. At the point of > decision, and from my vantage point, I truly had no time/energy to deal with > this. These are personal choices, I don't want to start a Verilog vs. VHDL > war here. > > Anyhow, if you know C I'd recommend you start with Verilog. I've acually > noticed that I've been picking up VHDL as I go because of things like > reading this NG every day as well as both the VHDL and Verilog NG's. Once > you understand the "standard" constructs it is relatively simple. In terms > of books, I'd recommend "Real World FPGA Design with Verilog" by Ken > Coffman; "Verilog Designer's Library" by Bob Zeidman and "Verilog HDL > Synthesis" by J. Bhasker. > > My approach was to concentrate on the synthesizable part of the language > almost exclusively from the start. Get a simple little evaluation board > (Avnet and Memec have interesting oferings) and play with the most basic > circuits you can think of. It was a natural transition to add the > simulation arsenal to what is learned in synthesis. Simulation is > invaluable. A very important tool. That's another thing that might be hard > to get used to if you come from old-school design. Now you get to write > software to simulate your hardware and software to simulate what your > hardware should do. Marry both of those pieces in simulation runs to figure > out where the bugs might be. > > Regarding such things as where to run clocks into, etc. You really need to > spend time reading through the data sheets and manuals for the parts you are > using. It is spelled out in great detail there. You also need to > familiarize yourself with the chip's infrastructure and logic resources. > You can damage a design (performance/space-wise) by not knowing how to take > advantage of the resources intelligently. Treat FPGA documentation like you > used to treat data books for non-programmable technologies. Make them a > part of your life. It is not impossible if you apply yourself. It took m e > six months to design my first FPGA-equipped board. The first article > ($30,000) worked right off the assembly line with multiple clock domains > running upwards of 160MHz. Realize that the frustration is due to being in > unfamiliar territory. > > Finally, in terms of learning, there are tons of resources on the Web. > Explore the Xilinx site. In terms of ease of use it is one of my > least-liked sites on the 'net, convoluted, confusing. It can be a chore to > find what you are looking for ... but there's a lot there. > > Their university program/site (http://xup.msu.edu/index.htm) is a good > resource for beginners. If you can find it, somewhere in the Xilinx site > there's a tutorial titled "Programmable Logic Design Quickstart Handbook", > it is a good newbie-read. Also, check out the Aldec tutorials: > www.aldec.com > > ... and one day you'll have the pleasure of burning three weeks trying to > figure out why "perfectly good code" isn't working and, all of a sudden > you'll realize METASTABILITY!!! And you'll remember that after the smoke > and BS clears out you are still dealing with high-gain amplifiers ... > millions of them. > > Enjoy the ride. > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > >Article: 57940
Hello, I want to create a dynamically reconfigurable design, that consist of modules that do not span the full height of the device. To make it efficiently work a partial bitsream that only comprises configuration bits of specific columns would be necessary. Is any information available that provides an insight into the addressing scheme of Virtex-II, Virtex-II PRO (alike xapp151 for Virtex(-E)) or a tool alike Parbit for Virtex-II (PRO)? Maybe BitGen has any hidden options to carry it out? (like the undocumented "-r") Did anybody try out to use the Small-Bit Manipulations flow of xapp290 to produce a partial bitstream for large modules? (e. g. eliminate columns that don't belong to the required module + run BitGen with the "-r" option) Thanks for the time that you spent on reading this post. + Thanks for replies. ChristianArticle: 57941
Hi, I have a question on Spartan-3 devices. Does anybody know if there is a possibility to request some free samples if those devices. regards, millimArticle: 57942
On 9 Jul 2003 11:00:32 -0700, fpga_uk@yahoo.co.uk (Isaac) wrote: >Yes ALLAN I am Sure I am using different bits > > >E.g > >This VHDL code I tried but in PAR file no pin assignment for signal 13 to 7 > > process(CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IRD_int,SR_IWR_int,SR_IVCS_V3_int) >begin > if RISING_EDGE(CLK_2X) then > if SR_IVCS_V3_int = '0' then > if SR_IWR_int = '0' then > if SR_ADDR_IO_int = "001100" then > LED_V3_int <= SR_DATA_IO_int(13 downto 7); > end if; > end if; > end if; > end if; >end process P_SRAM2LED; It's hard to say exactly what's going on, because you didn't include the right bits of VHDL (i.e. the signal declarations). Which signal is related to the "INPUT" signal in your first post? The only signal is likely to be of type std_logic_vector is SR_ADDR_IO_int, and that is only six bits long. Hmmm, the error messages indicated that the six least signficant bits of INPUT were used. Do you have an assignment like: SR_ADDR_IO_int <= INPUT(5 downto 0); anywhere in your code? You also might want to fix the sensitivity list. Regards, Allan.Article: 57943
rickman wrote: > Hal Murray wrote: > >>>>If there is an Ethernet card in the machine, I can't assure my customers >>>>that it will not be connected in a forgetful manner. >>> >>>Why not take the ethernet card and attack the connector with >>>wirecutters? You get a MAC address but the net don't work. :) >> >>I was going to suggest bubble gum. Might need epoxy for govt work. :) >> >>How does not having an ethernet card solve anything interesting >>about the integrity of the system? Have virus writers given up on >>floppies now? How does a good anti-virus (with auto-updates) >>compare to a no-network machine? >> >>-- >>The suespammers.org mail server is located in California. So are all my >>other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited >>commercial e-mail to my suespammers.org address or any of my other addresses. >>These are my opinions, not necessarily my employer's. I hate spam. > > > I should have used the term "security" rather than just virus. Virus > attack is just one way to mess with a system. But if the machine gets > connected to a network that is connected to the outside, any number of > things can happen. Sure, there is software available that can help > minimize or prevent damage, but it is *never* foolproof. Making sure > the machine is not connected to a network is a *much* more sure way of > stopping such problems. Of course anytime you insert a data disk you > need to verify that it does not contain a virus. But that is a much > smaller job if you are not connected to a network. > > Also, no anti-virus software is ever up to date, by definition. Any > *new* virus will not be addressed by the software no matter how often > you update. But then I am not trying to achive 100% protection. I am > just trying to take a few simple measures that get very close to 100%. > Certainly not having an Ethernet card in a computer should not make the > machine worthless for running free CAD software. > > In any event, the issue is moot. Altera has already provided for disk > serial number keying, they just have not put it on the web site (or even > told their support people about it). Seems it was not availble before > because some of the synthesis software required a NIC keyed license file > due to contractual reasons. It's all a problem of MicroCrap$oft. In linux you can simply change some permissions, startup scripts, turn off any open ports, or disable tcp/ip in the kernel. The solution is to stop paying for garbage and maybe they'll stop making it. Why should anyone need a virus checker?Article: 57944
Hello
I have problem with understanding following pseudocode:
-------------------------------------------------------
TRACEBACK
begin
N = current state
do while ( ((state(N)<<1) AND 63) OR conbit(N)) !=
state(N-1) )
begin
state(N-1)=((state(N)<<1) AND 63) OR conbit(N);
N = N - 1;
end
end
-- This is from : Power Reduction Techniques for a Viterbi Decoder
-- Implementation
-- I. Bogdan, M. Munteanu, P. A. Ivey, N. L. Seed, N. Powell
-------------------------------------------------------
For me it's like moving forward not backward.
I mean, when You look at butterfly and next state calculation, You see
that upper algorithm is for calculation next state not previous.
It makes me mad...
Why...
Help me...
Jerzy Gbur
Article: 57945"..:: Gabster ::.." <gabsterblue@hotmail.com> wrote in message news:<_C2Pa.101491$Il3.2931504@wagner.videotron.net>... > Hi, > > I have a PROM (XC18V02) set up on my Spartan IIE evaluation board. I'm > developing under Xilinx ISE 5. I'm wondering what would be the simplest JTAG > cable I could build (or buy if real cheap) to download my code in the PROM. > Is any JTAG cable supposed to do the job? The fact is I already a very > simple JTAG interface (with a 74HC244 buffer for parallel port)...I tried it > but it didn't work. > > Thanks keep on trying, a 5 resistors to the parallel port cable defenetly works also for XC18V02, we have memec spartan II 200 board and we reprogram both fpga and the config rom using the low cost cable. anttiArticle: 57946
Sorry , I changes my code to Input ....... So please read SR_DATA_IO_int (13 downto 0) as Input (13 downto 0) Cheers Isaac Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote in message news:<0ccqgvs49b23uhvhb8g5j2hbfeika71kui@4ax.com>... > On 9 Jul 2003 11:00:32 -0700, fpga_uk@yahoo.co.uk (Isaac) wrote: > > >Yes ALLAN I am Sure I am using different bits > > > > > >E.g > > > >This VHDL code I tried but in PAR file no pin assignment for signal 13 to 7 > > > > process(CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IRD_int,SR_IWR_int,SR_IVCS_V3_int) > >begin > > if RISING_EDGE(CLK_2X) then > > if SR_IVCS_V3_int = '0' then > > if SR_IWR_int = '0' then > > if SR_ADDR_IO_int = "001100" then > > LED_V3_int <= SR_DATA_IO_int(13 downto 7); > > end if; > > end if; > > end if; > > end if; > >end process P_SRAM2LED; > > > It's hard to say exactly what's going on, because you didn't include > the right bits of VHDL (i.e. the signal declarations). > Which signal is related to the "INPUT" signal in your first post? > > The only signal is likely to be of type std_logic_vector is > SR_ADDR_IO_int, and that is only six bits long. Hmmm, the error > messages indicated that the six least signficant bits of INPUT were > used. > Do you have an assignment like: > SR_ADDR_IO_int <= INPUT(5 downto 0); > anywhere in your code? > > You also might want to fix the sensitivity list. > > Regards, > Allan.Article: 57947
millim wrote: > > Hi, > > I have a question on Spartan-3 devices. Does anybody know if there is > a possibility to request some free samples if those devices. Not likely. Xilinx does not provide *free* samples to the best of my knowledge. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57948
Check with your distributor. The XC3S50J ( that is the one without BlockRAM and DCM) should be available, and the price will not break anybody's budget... The XC3S1000 is also available, but in much tighter supply. The rest is coming soon. Peter Alfke =========== rickman wrote: > > millim wrote: > > > > Hi, > > > > I have a question on Spartan-3 devices. Does anybody know if there is > > a possibility to request some free samples if those devices. > > Not likely. Xilinx does not provide *free* samples to the best of my > knowledge. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57949
Hi, I am doing my Ph.D research related to partial dynamic reconfiguration of FPGAs. I need a few real designs to test my work. Can someone tell me where I can get them from? The more frequently the design reconfigures a part of the FPGA, the better it will work for me. I expect the design to be in Verilog, VHDL, EDIF or NGD format (in some format that Xilinx ISE can map and PAR). Any help in this regard will be deeply appreciated. Thanks, Aman
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