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Hello, Does anybody know what going on? Using the foundation timing analyzer just a few runs drains my system recources on my Win98 system. Exiting the program is the only option left to get back about 70%(!!!) of the resources. Especially scrolling the report eats up resources. Does anybody else experience this problem? greetings, Edwin BaaijArticle: 22426
Hi, I want to use the Megafunction SCFIFO created with Maxplus 2. The properties are: - width: 1Bit - deep: 8 - both sides are synchronized by one clock - outputs: empty - asynchronous clear - show-ahead synchronous FIFO mode I am targeting a FLEX6k. After synthesis in Leonardo I get the message: Warning, component scfifo has no visible entity binding. During place&route the following message appears: Warning: Illegal memory cell name "scfifo_1_8_on_on" Error: can't find design file "scfifo_1_8_on_on" If I use only Maxplus 2 everything works fine. Is it possible to use megafunctions created with MaxPlus 2 any how? How can I use these functions with Leonardo? I hope someone can help me. Thanks, ThorstenArticle: 22427
Joel Kolstad <Joel.Kolstad@USA.Net> wrote > But is he active in multi-threaded programming under Windows NT or perhaps > VMS? We've got plenty of people with their CS degrees at work, and only a > small fraction of them could tell you what a mutex (or semaphore) is. I've never heard it before now, but the MSDN library does, indeed, reference it: "An object of class CMutex represents a "mutex" - a synchronization object that allows one thread mutually exclusive access to a resource. Mutexes are useful when only one thread at a time can be allowed to modify data or some other controlled resource. For example, adding nodes to a linked list is a process that should only be allowed by one thread at a time. By using a CMutex object to control the linked list, only one thread at a time can gain access to the list." Ciao, Peter K. -- Peter J. Kootsookos Wb: www.clubi.ie/PeterKArticle: 22428
I have some shift registers in a Xilinx Virtex design and between the synthesis tool (FPGA Compiler II) and the Xilinx Alliance P&R (2.1i), it is placing these shift registers inside the Look-up tables, not in the 'regular' registers in the slices/CLBs -- which is where I need them since they are acting as pipeline registers to help break up the long travel time from one side of the chip to the other -- and forcing them inside a "SRL16" of one CLB isn't going to do that. Is there a way of coaxing the synthesis and/or P&R tool to put shift registers in a resource of the designers' choosing (without manual instantiation of SRL16's vs. FDCE's)? -- ======================== William Lenihan lenihan3we@earthlink.net ========================Article: 22429
Hi Andy, I also struggled to understand this cryptic statement. I believe that the case that the Xilinx hardware supports but that Leonardo can't infer is when one or other of the two ports is a read/write port. So you are allowed: - a single read/write port - one read port and one write port but not - two read/write ports - one read port and one read/write port - one write port and one read/write port HOWEVER I'd strongly advise against trying to infer ANY Xilinx block RAMs using Leonardo at the moment. I uncovered a serious bug in this back in January and have yet to hear of a fix. I suggest that you just instantiate the Xilinx component directly. (Even when ram inferencing does work in Leonardo it is horribly slow.) Regards, --Phil. Andy Krumel wrote: > > The Xilinx Spartan II and Vertex datasheets claims (and Mentor documentation > backs it up) that: > "Currently, LeonardoSpectrum does not infer dual port RAMs that read both > read and write address." > > A dual port RAM has independent clocks and addresses which support > simultaneous read from the same/different locations and simultaneous > read/write to different locations. > > The possible interpretations seem to be: > 1) LS does not infer dual port RAMs. > 2) LS infers dual port RAMs but only one read is allowed at a time, ie > either port A or port B. > 3) #2 except restriction in place only when writing data. > > My best guess is #2. > > Thanks, > AndyArticle: 22430
I want to implement FEC techniques in Xilinx FPGAs. Could someone please list some good books on FEC like Viterbi, Reed-Solomon and Turbo codes. What are the names of the Research magazines that publish the new research in these fields. I will be thankful Regards, SHAH Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22431
Jim Granville wrote: > CThis is actually very similar to what I had in mind - a combination of > shifter and PROM/Tables > ( a lot of our IP has this type of code, and I have often thought it > woud be a dog to > reverse engineer ) > > The only difference is whether you allow external, or self 'seed' of the > shifter. > I guess a public source version of this could allow users either option, > or maybe > more a seed select, than a seed load ( too open ). > > So, if we accept that this raises the bar sufficently on CPLD and > handshake attack, that > leaves just bitstream attack on the FPGA. > > There are potential weaknesses here :- > > a) If just one copy exists in FPGA, correlation of PROM to bitstream > location starts to > look simpler. A Hacker can get 100's of your bitstreams quite easily, > plus generate their > own reference ones. > b) I am sure a std HDL compile ( common source code ) will tend to place > cells in > a similar bitstream order, again aiding hacking. > > For a) the design could 'fill' the spare space in the FPGA with > multiple copies of > this engine - now, many bits are changing. > For b) the FPGA vendors would need to add a scramble place/route > option, so that within a > block, the CLBs change order, from compile to compile. > > > > > If anybody wants to try to break this I can set up a challenge test. > > Send me an email, and we can discuss this further. > > - jg As several people have pointed out this is still suseptible to JBits attack. (1) Use JBits to get a map of the routed design. [Can JBits do this ? If not then readback the configuration via the JTAG i/f.]. (2) Find the pin that takes the input from the CPLD. (3) Trace the logic forward from this pin. >>From then in the simplest case the hacker could, (4) Find the output from the scrambling logic that sends a go/no-go signal to the rest of the FPGA. (5) Use JBits to modify the the bitstream so that the output from (4) is permanently ``o.k.''. This could probably be made very difficult by using multiple output bits through look-up tables. So the remaining vulnerability is (3) which, in principle, will enable our determined - & by now v. pissed off - hacker to re-create the CPLD. First step in protecting this would be to include a lot of ``dummy'' logic in the FPGA so that to re-create it in the CPLD would require a bigger one than on the original board. So we now have 2 new conditions required for our protection scheme: o The output from the FPGA logic should affect the design in a sufficiently complex way that will put off all but the most absolutely determined hacker. o The CPLD & FPGA mangling logic should be asymmetric to the extent that knowledge of the FPGA will not allow the CPLD to be recreated - or only with great difficulty. The current proposed scheme of running the same state machine in both CPLD & FPGA and comparing results will fall down here. What we need is a pair of functions E (in CPLD) and D (in FPGA) such that E followed by D produces a known result. This result could be a fixed output value checked every so often but it would have to be fairly long to resist probing. A better idea might be to generate an MFM encoded stream where a legal E/D pair will produce a known pattern of edge drop-outs.Article: 22432
On Mon, 08 May 2000 22:30:04 -0400, Jerry Avins <jya@ieee.org> wrote: >Result of check: I asked a CS friend (he has a masters degree and is >active in the profession) if he knew or could guess what a mutex is. He >had a vague memory that it is a species of mosquito. > >Jerry Funny, I study CS in the Netherlands and the theory of operation systems (like synchronisation algorithms, multitasking theory) was part of the first half of the bachalors program, dealing with semaphores, mutexes, critical regions, producers/consumers, deadlocks etcetera. Guess it depends on the university where you're studying... Johan. <snip>Article: 22433
Hello, What's synthesisable model (verilog) is better: 1) model which contains only nets. 2) model which contains only registers. Both models are exactly the same. Thanks for each reply tbrychcy@sensor.ime.pz.zgora.plArticle: 22434
Jon Elson wrote: > "J. Boss" wrote: > > > Hi, > > > > I've just made a very easy design, which I want to implement in a Xilinx > > SpartanXL FPGA using a processor-bus. I'm using the Foundation Series F2.1i. > > The design is schematic-based. The implementation-file has been succesfully > > created (bit-file). When I upload the program to the FPGA, everything works > > fine (INIT remains low during programming and DONE becomes high after all > > bits have been send and after this at least four CCLK-cycles follow!). Also > > all timing-specs of programming the FPGA are applied. But when I measuring > > some output pins, I just don't see what I would expect. > > Well, I have a bit of experience with the XC9500 parts, but I'm just moving > into the FPGA world, too. I did see some knowledge base articles on the > correct settings for the clock source selection for programming to function > correctly. But, DONE shouldn't go high unless the download blocks have > passed the checksum, so it sounds like the programming was correctly > loaded into the device. Is there some simply combinatorial signal you can > check? My guess is that the internal clock is set up wrong, and is not > taking the clock from the source you intend it to. > > Jon In my case I had to switch the done to clock pulse 4 instead of clock pulse 1. This was using a serial EEPROM to load code. It doesn't sound like that is your problem but you might check it out.Article: 22435
Greg Neff wrote: > > In article <8f76nd$rp4$1@sun27.hrz.tu-darmstadt.de>, > Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: > > Hallo, > > > > are there any high pin count ( around 220 usable IO pins) FPGA/CPLD > > available in Non-BGA package? > > > > Thanks for pointers. > > > > Bye > > > > -- > > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > > > It looks like some Xilinx XC4000E and XC4000XL devices are available in > 304pin QFPs, with 256 I/Os. Check with Xilinx for real availability. Because of the high power and ground pin counts on most packages, you will need to go larger than 256 package pins to get 220 IOs. The smallest package I can find that will give you this is a 304 pin QFP. It looks like the Xilinx families have up to 256 IOs in this package. Another option is a PGA, but they are quite expensive. They also don't seem to be as commonly used. If you want high IO count in smaller devices, the Lucent OR2 family gives you the best bang for the CLB. The OR2C12A through OR2C40A provide 252 IOs in the 304 pin QFP. Several of these devices also come in 3 volt versions. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22436
Johan Kwisthout wrote in message <3917fdf7.20732581@obsserver>... >On Mon, 08 May 2000 22:30:04 -0400, Jerry Avins <jya@ieee.org> wrote: > >>Result of check: I asked a CS friend (he has a masters degree and is >>active in the profession) if he knew or could guess what a mutex is. He >>had a vague memory that it is a species of mosquito. >> >>Jerry > >Funny, I study CS in the Netherlands and the theory of operation >systems (like synchronisation algorithms, multitasking theory) was >part of the first half of the bachalors program, dealing with >semaphores, mutexes, critical regions, producers/consumers, deadlocks >etcetera. Guess it depends on the university where you're studying... > >Johan. > ><snip> > I studied CS some 20 years ago and also covered semaphores, but don't ever recall the term mutex, until I came across it a couple of years ago doing some NT stuff. Is "mutex" purely Microsoft-speak for what everyone else calls a semaphore? I don't like the use of "flag" in such specific terms - to me, a flag is simply an indication of state, with no protection mechanism for setting or resetting. BTW Didn't Dijkstra first describe semaphores, and wasn't he from the Netherlands? (not that its got anything to do with anything, much ;-)Article: 22437
On Tue, 9 May 2000 08:56:06 +0100, "Peter J. Kootsookos" <p.kootsookos@remove_this.ieee.org> wrote: >I've never heard it before now, but the MSDN library does, indeed, reference >it: I learned about mutex semaphores while reading the Design of OS/2 by H.M. Deitel and M.S. Kogan back in 1992. So the term is definately older than win32. Whether it is older than Microsoft(one time partner in OS/2's development) I do not know. John StewartArticle: 22438
Johan Kwisthout wrote in message <3917fdf7.20732581@obsserver>... >On Mon, 08 May 2000 22:30:04 -0400, Jerry Avins <jya@ieee.org> wrote: > >>Result of check: I asked a CS friend (he has a masters degree and is >>active in the profession) if he knew or could guess what a mutex is. He >>had a vague memory that it is a species of mosquito. >> >>Jerry > >Funny, I study CS in the Netherlands and the theory of operation >systems (like synchronisation algorithms, multitasking theory) was >part of the first half of the bachalors program, dealing with >semaphores, mutexes, critical regions, producers/consumers, deadlocks >etcetera. Guess it depends on the university where you're studying... > It certainly does. Some universities and courses will cover things like Windows programming, which does not really have anything to do with CS, but which looks good to PHBs for later employment. Others will teach you the theory of computer systems, and will cover semaphores, etc., in a manner which can then be applied to any system. Part-time courses and newer universities tend towards the former, while older, more accademic universities tend towards the later (I know that's a terrible, unsubstantiated generalisation, but it is basically true). Dutch universities will of course tend towards the theoretical - after all, a high proportion of the work in synchronisation was done by Dutch mathematicians such as Djikstra (spelling?). >Johan. > ><snip> >Article: 22439
Prof. Andrew Tanenbaum refers to a binary semaphore named "mutex" in Operating Systems Design and Implementation (the book with the entire source code to Minix, precursor and insperation for Linux, as an Appendix) in 1987. The reference is to solve a buffer situation with three semaphores - "full" and "empty" initialised to 0, and a binary semaphore "mutex" initialised to 1 to ensure mutually exclusive access to the buffer. So the term "mutex" has probably been generalised from particular uses such as this one. John Stewart wrote in message <39180b20.30634157@news.mindspring.com>... >On Tue, 9 May 2000 08:56:06 +0100, "Peter J. Kootsookos" ><p.kootsookos@remove_this.ieee.org> wrote: > >>I've never heard it before now, but the MSDN library does, indeed, reference >>it: > > I learned about mutex semaphores while reading the Design of >OS/2 by H.M. Deitel and M.S. Kogan back in 1992. So the term is >definately older than win32. Whether it is older than Microsoft(one >time partner in OS/2's development) I do not know. > > John Stewart > >Article: 22440
Hi does anyone have a simple schematic for a Xilinx fpga board. perhaps the 4000 series fpga and a power supply, clock and some i/o & or connectors? I will be buying the student edition book and sw when the new version comes out in July. I think there are schematics for there demo board in the book, but i would like to design a pcb to test out some designs now. p.s. I use "pads power pcb" but can import most ascii files schmatic and or PCB. or with a word or pdf file I could create my own schematic and pcb. Thanks any help is appreciated. My email address if it is easyer to send there is "martinb@magma.ca"Article: 22441
Phil Endecott wrote:
> Hi Andy,
>
> I also struggled to understand this cryptic statement. I believe that
> the case that the Xilinx hardware supports but that Leonardo can't infer
> is when one or other of the two ports is a read/write port. So you are
> allowed:
>
> - a single read/write port
> - one read port and one write port
>
> but not
>
> - two read/write ports
> - one read port and one read/write port
> - one write port and one read/write port
>
> HOWEVER I'd strongly advise against trying to infer ANY Xilinx block
> RAMs
> using Leonardo at the moment. I uncovered a serious bug in this back in
> January and have yet to hear of a fix. I suggest that you just
> instantiate the Xilinx component directly. (Even when ram inferencing
> does work in Leonardo it is horribly slow.)
>
> Regards,
>
> --Phil.
>
> Andy Krumel wrote:
> >
> > The Xilinx Spartan II and Vertex datasheets claims (and Mentor documentation
> > backs it up) that:
> > "Currently, LeonardoSpectrum does not infer dual port RAMs that read both
> > read and write address."
> >
> > A dual port RAM has independent clocks and addresses which support
> > simultaneous read from the same/different locations and simultaneous
> > read/write to different locations.
> >
> > The possible interpretations seem to be:
> > 1) LS does not infer dual port RAMs.
> > 2) LS infers dual port RAMs but only one read is allowed at a time, ie
> > either port A or port B.
> > 3) #2 except restriction in place only when writing data.
> >
> > My best guess is #2.
> >
> > Thanks,
> > Andy
I asked the same question of Synplify some time ago. They said that Block RAM
inference will be allowed via some sort of template in a future release. Basically
AFAIK the only way to define a true dual port RAM at the Verilog level is to have
the reg array that defines the RAM written in 2 independent always blocks.
This is o.k. for simulation but is not allowed in the synthesis tools. In other
words the obvious definition:
reg [15:0] mem [256:0]
always @(clk_a) begin
dout_a <= mem[addr_a];
if (we_a)
mem[addr_a] <= din_a
end
always @(clk_b) begin
dout_b <= mem[addr_b];
if (we_b)
mem[addr_b] <= din_b
end
will fail synthesis, try it yourself.
Article: 22442This is the sort of thing I would expect to be an FAQ, but there doesn't seem to be one for this group. I have been thinking about "playing" with an FPGA both from the view of learning about an interesting-looking technology and with the hope of constructing an emulation of a '60s mainframe (more about this later). I am looking for advice on low-cost ways of doing this (Let's say price ceiling of about £200 [$300]). It seems that I am going to need two main things: * A package of software. * A prototyping/evaluation board. Taking the second of these first there seem to be few choices available (without paying lots of $$$) - The most obvious seems to be the XS40 from Xess using the Xilinx 4000 series devices. (http://www.xess.com) Less expensive with more features on board is the Atmel FPGA Starter Kit from Kanda (http://www.kanda.com) If I qualify for the special deal (I am a member of staff at a University), the Altera Design Laboratory Package looks very attractively priced - if I can't get the deal it is likely to be too expensive. (http://www.altera.com) The only other low-priced boards available seem to be the Australian ones from Burch Electronic Designs (http://www.burched.com.au) that were recently advertised on this group. However they seem to be very "bare" and more designed for building real-world prototypes than for learning. All versions also come with FPGAs of minimal capacity (almost certainly too small for my "big" project). As for software, the Kanda and Atmel packages come with some, for the Xess one I would also have to spend another $100 for the Foundation student edition. ** so, first question: any known "gotcha's" with the above alternatives? [ISTR a recent hint that the Atmel software was weak in one respect - it is noticeable that their web site seems to say almost nothing about its functionality - and the low cost version of Foundation doesn't include VHDL?] Are there other reasonable options? The other main question I have concerns estimating how big an FPGA I would need for the mainframe emulation. I assume that the "usable gate" counts for all devices tend to be as much marketing as technical statements. I have detailed (but only "almost complete") descriptions of the logic design for the mainframe that I am interested in (ICT 1905 - aka FP6000) and I can be reasonably confident that it has less than 6000 gates including FPU ... probably less than 4000 without. Is this likely to fit in a "10000 gate" FPGA?, a "20000 gate" one, or whatever? More questions later :-) Andy Holt Systems Consultant City University London, England andyh@city.ac.ukArticle: 22443
Andy Holt wrote: > ... ooops, so busy trying to avoid any stupid misteaks that I forgot to say "please" ... I'm not usually so rude - I hope AndyArticle: 22444
PeterS wrote:
>
> Johan Kwisthout wrote in message <3917fdf7.20732581@obsserver>...
> >On Mon, 08 May 2000 22:30:04 -0400, Jerry Avins <jya@ieee.org> wrote:
> >
> >>Result of check: I asked a CS friend (he has a masters degree and is
> >>active in the profession) if he knew or could guess what a mutex is. He
> >>had a vague memory that it is a species of mosquito.
> >>
> >>Jerry
> >
> >Funny, I study CS in the Netherlands and the theory of operation
> >systems (like synchronisation algorithms, multitasking theory) was
> >part of the first half of the bachalors program, dealing with
> >semaphores, mutexes, critical regions, producers/consumers, deadlocks
> >etcetera. Guess it depends on the university where you're studying...
> >
> >Johan.
> >
> ><snip>
> >
> I studied CS some 20 years ago and also covered semaphores, but don't ever
> recall the term mutex, until I came across it a couple of years ago doing
> some NT stuff. Is "mutex" purely Microsoft-speak for what everyone else
> calls a semaphore?
>
> I don't like the use of "flag" in such specific terms - to me, a flag is
> simply an
> indication of state, with no protection mechanism for setting or resetting.
The original system of semaphores, for signalling, used flags. A
semaphore is simply a signal, as is a flag, flags are not necessarily
binary, originally semaphore, the method of singalling, each with
different context sensitive meaning. Semaphore pre-dates Dijkstra et al.
I believe it originated in the 18th century.
Semaphore noun [U]
a system of communication using two mechanical arms or
hand-held flags which are moved into different positions to
represent different letters, numbers or symbols
Semaphore was widely used at sea, before the advent of
electricity.
(figurative) When I lived opposite her we would send
semaphore signals (=messages without speaking) to each
other from our bedroom windows.
Al
Article: 22445Clearly your friend has a bright future at Microsoft.Article: 22446
I am working with a global comms organisation who have several sites across the Uk and who are growing by acquisition all the time. I am trying to find the following: This can be based in Cambridge or the Midlands. Please email me at JCrump@alphatec.uk.com EDA ADMINISTRATION This is a newly created role which is central to the creation of an EDA group. The successful candidate will assist in building a new EDA team. This group will sit above the project teams and support large numbers of design projects totalling around 400+ engineers. This support will involve training, assisting complex design work, introducing and developing new tools. This challenging role provides technical support in all areas of ASIC and FPGA development. The job encompasses all aspects of administering and managing a complex electronic design automation infrastructure based on verilog in a distributed Sun-Solaris environment headquartered in Birmingham. The role is hands-on and proactive. In addition to day-to-day support, the successful candidate will be capable of taking the initiative to find and promote solutions related to EDA issues and development policies as they arise. Experience:  In depth Cadence/ Synopsis administration skills (1 year+)  Sound UNIX skills (preferably Solaris)  NT experience advantageous  Shell scripting (Skill, Perl, Tcl)  General Configuration Management skills and an understanding of complete HW development lifecycle. * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is BeautifulArticle: 22447
>> I don't like the use of "flag" in such specific terms - to me, a flag is >> simply an >> indication of state, with no protection mechanism for setting or resetting. > >The original system of semaphores, for signalling, used flags. A >semaphore is simply a signal, as is a flag, flags are not necessarily >binary, originally semaphore, the method of singalling, each with >different context sensitive meaning. Hmmm, interesting sentence. Wonder what it means ;-) Chains of simple signal flags were also used to "post" entire messages from the rigging of sailing ships (like Nelson's "England expects this day..." signal at Trafalgar), but there was nothing, I guess to stop anyone else (ie no interlock) putting up a message from their own rigging, which is why I dislike the interchangeable use of "flag" and "semaphore". >I believe it originated in the 18th century. > >Semaphore noun [U] > a system of communication using two mechanical arms or > hand-held flags which are moved into different positions to > represent different letters, numbers or symbols > Semaphore was widely used at sea, before the advent of > electricity. > > (figurative) When I lived opposite her we would send > semaphore signals (=messages without speaking) to each > other from our bedroom windows. > >Al I live near to a restored semaphore tower dating from the time of the Napoleonic wars which signalled from the Admiralty in central London down a chain of towers to Portsmouth and Plymouth.( Just off the A3 outside the M25.) It has working arms, and an interesting display model of an earlier system which used six flat, square shutters which could be individually displayed upright, face-on, or rotated horizontal. Somewhat OT, I realise, but a fascinating monument. Oh yes, a short message took less than 15 minutes from London to Portsmouth, weather permitting (50 odd miles, 80+ km).Article: 22448
Does anyone know how to recover the clock from the lvds data stream within a Xilinx Virtex E device? Any ideas how to do this without external devices? Thanks in advance.Article: 22449
OneStone wrote: > > I probably just move in much older circles than you, Hmmm, I'm feeling pretty old right now, thanks for making me feel younger ;-) > before the computer > world went insane with jargon. What year, exactly, was that ? Was that the year Grace Hopper coined the term "bug" ? Seems to me, that any substantial technology will inevitably require its own terminology. I have no problem with this, I simply want whatever terminology that is developed to be clear, and concise (btw: I don't consider "bug" to be in the category of clear and concise, although it is quaint). > Mutual exclusion mechanism smacks of the > same sort of mentality that turned housewifes into domestic engineers, > and directory enquiries operators into information consultants. Since I disagree. MUTual EXclusion is the function of the device. Personally, I find functional naming clearer than say, the term "bit flag" (which is incredibly overloaded, and gives no clue as to the intended function of the device - and in no way conveys the requirement for atomic state change). Contrast the rationale behind this, to that behind the term "domestic engineer". The term "domestic engineer" is more ambiguous than housewife. I contend that mutex is *less* ambiguous than "bit flag", since a mutex can only be one thing, while a "bit flag" could be many things (much as housewife can mean only one thing, while "domestic engineer" could mean many things). > pthreads are a POSIX multithreading standard I have never had cause to > read about them extensively or use them in any embedded systems. And a > review in Amazon showed that only the Butenhof book seemed to be really > popular, the numbers sold on this subject hardly makes the book > 'popular'. Hmmm, Amazon.com, as dearly as they may want us to believe so, is not the only source of technical reference material on the planet, hence your data (with regards to popularity) may be incomplete. Certainly, I didn't mean to imply that these books were popular relative to, say Stephen King novels :-) > Perhaps reasonably popular amongst POSIX programmers, but my A reasonable guess would be that every real-time Posix programmer, has a copy of at least one pthreads book. > HC12, HC16, and even my MCORE systems aren't running POSIX, definitely > none of my 8 bitters do. Understood. My original point was simply that I don't believe the Embedded Systems Glossary was being obscure, simply by including the term mutex; in fact, it appears to be a necessary inclusion (since the purpose of a glossary is to explain terms). Your point was that the term "bit flag" should be included, and while this would be nice, I can understand why someone attempting to produce a concise glossary would avoid this term (due to the fact it is extensively overloaded). Rennie
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