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Hello All,
I'm currently doing a Virtex design that makes heavy use of Coregen modules.
I want to do the majority of my design entry in schematic under Innoveda's
(Viewlogic's) Viewdraw.
I want to be able to use simulation for design verification but the Coregen
modules present a problem with respect to simulation models. The Coregen
tool seems to me architected for people who use pure VHDL design entry. In
particular Coregen does not generate a simulateable netlist for the
schematic user. Rather, only a .vho file is generated which tells how to
instantiate the Coregen module in VHDL and it gives a configuration
statement that you can use to point your macro to the appropriate generic
VHDL mode.
This is pretty unwieldy for a designer using schematic entry. Has anyone out
there found a smooth simulation flow for schematic based simulation of
Xilinx Coregen modules?
Thanks in advance for your help.
********************************************************************
Pete Dudley
Sandia National Labs
Dept 2336 MS 0505
PO BOX 5800
Albuquerque, NM 87185
voice: 505.844.5565 fax: 505.844.2925 email: padudle@sandia.gov
http://www.sandia.gov/RADAR/sarcap.html
Signal Processing in Hardware and Software
********************************************************************
Article: 22551Try www.xess.com. In article <3918A9FA.566D109E@aps-euro.com>, Laurent Gauch <laurent.gauch@aps-euro.com> wrote: > Try www.aps-euro.com : stand-alone board, PC104 boards, ISA board. > > Laurent > > myself a écrit : > > > Hi does anyone have a simple schematic for a Xilinx fpga board. > > > > perhaps the 4000 series fpga and a power supply, clock and some i/o & > > or connectors? > > > > I will be buying the student edition book and sw when the new version > > comes out in July. I think there are schematics for there demo board > > in the book, but i would like to design a pcb to test out some designs > > now. > > > > p.s. I use "pads power pcb" but can import most ascii files schmatic > > and or PCB. or with a word or pdf file I could create my own schematic > > and pcb. > > > > Thanks any help is appreciated. > > > > My email address if it is easyer to send there is "martinb@magma.ca" > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22552
On Thu, 11 May 2000 11:18:21 +0200, Patrick Schulz <schulz@rumms.uni-mannheim.de> wrote: >> http://www.annapmicro.com/ >They don't have a VIRTEX1000(e)-board. They do have PCI based Virtex1000 boards, even if they don't market them much on their website. But the PCI core is, as I understand it, hidden from the user, it is implmemented in a separate FPGA not available for user applications. / Jonas ThorArticle: 22553
Utku Ozcan wrote: > > I think you want to use hardware model (real silicon) > instead of software model (any HDL model, such as > RTL, gate-level or postlayout) in the testbench. > > This is possible in ASIC. Synopsys has a device called > Hardware Modeller, which can be connected with a fibre > to the workstation. It has a special software which > interacts with special PLI functions, that is normally > called by an HDL simulator. You put your device into > a special device adapter and then finally, your HDL > simulator can "see" your hardware model just as an > HDL model. > > These equipments are very expensive. > > But AFAIK, in current technologies, such a thing is > practically impossible for FPGAs. The reason would > be, as some engineers claimed, that you have to model > programming phase of your FPGA in the simulation, which > takes very long, especially in large FPGAs. > > Utku > > -- > I feel better than James Brown. I believe this is like what Mentor used to sell (maybe still does). It is the reverse of an emulator in that it allows you to connect to the environment hardware. This saves you the trouble of writing test benches that may or may not be an accurate reflection of the environment. The downside was that it was rather slow. You might think the hardware would be fast, but the problem is that the software simulation of the logic design could not keep up with the hardware. So the machine ran the simulation for one clock cycle, used that as a vector to drive the hardware. Then another clock cycle was simulated and two vectors were used to drive the hardware, then three, etc... So you would have to run the hardware with resets inbetween for (N^2)/2 clock cycles to get your full result. I think the hardware was based on a logic analyzer with pattern generation capability from a company that Mentor bought. Do they still sell this equipment? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22554
I need a multi FPGA board to do ASIC verification. So far, I've looked at WildStar (by Annapolis Micro) and RSPE (by Viasat). Can anyone reccomend another board I should look at? Thanks, JohnArticle: 22555
Johan Kwisthout wrote: > > ... > > It's Dijkstra (turn the i and j the other way around). ... > > >>Johan. I remember the order because it looks like the letter "y" (with two tittles) in script. The great British (later, US) optical designer Conrady was born Conradij in The Netherlands. Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 22556
Hi Folks, :) I was wondering if anyone can report any success in programming a Spartan (e.g., XCS40XL) part by hooking it directly up with one of the Xilinx XC18V00 serial/parallel configuration proms (for either master-serial or Express configuration). The isp JTAG reprogrammability of the XC18V's is fairly appealing for a board design I'm working on. I know/gather the XCSxxLV parts can also be programmed with atmel EEPROMs... I was just wondering if somone knows of any gotchas that I should be aware of upfront before going down the XC18Vxx route? Ta in advance! -adamArticle: 22557
Pete, Coregen generates a .edn file (older version generates a .xnf file) which is in edif format. I am not sure how viewlogic can reference this edif file from within a symbol, but in Mentor Graphics, I set a FILE property and specify the full path to the edif file in the "value" field. I have tried to use the .vho file in VHDL designs, so that I can simulate in Mentor Graphic's Modelsim, but the Coregen documentation was not very helpful. When you said "makes heavy use of Coregen modules", what actually are the modules you are using? Regards, LC Pete Dudley <padudle@sandia.gov> wrote in message news:8fevje$9k0$1@sass1828.sandia.gov... > Hello All, > > I'm currently doing a Virtex design that makes heavy use of Coregen modules. > I want to do the majority of my design entry in schematic under Innoveda's > (Viewlogic's) Viewdraw. > > I want to be able to use simulation for design verification but the Coregen > modules present a problem with respect to simulation models. The Coregen > tool seems to me architected for people who use pure VHDL design entry. In > particular Coregen does not generate a simulateable netlist for the > schematic user. Rather, only a .vho file is generated which tells how to > instantiate the Coregen module in VHDL and it gives a configuration > statement that you can use to point your macro to the appropriate generic > VHDL mode. > > This is pretty unwieldy for a designer using schematic entry. Has anyone out > there found a smooth simulation flow for schematic based simulation of > Xilinx Coregen modules? > > Thanks in advance for your help. > > > ******************************************************************** > Pete Dudley > Sandia National Labs > Dept 2336 MS 0505 > PO BOX 5800 > Albuquerque, NM 87185 > voice: 505.844.5565 fax: 505.844.2925 email: padudle@sandia.gov > http://www.sandia.gov/RADAR/sarcap.html > Signal Processing in Hardware and Software > ******************************************************************** > > >Article: 22558
Yeh! I tried to use package ieee.std_logic_unsigned which allows the use of SHL (supports std_logic_unsigned) and it works! yeh!! The code becomes fedge: PROCESS(nReset,BClk) VARIABLE tmp : std_logic_VECTOR(2 downto 0); BEGIN IF nReset='0' THEN DataO <=(OTHERS=>'0'); tmp:="000"; ELSIF BClk'event AND BClk='0' THEN tmp:=tmp+"001"; DataO <= SHL(DataI, tmp); end if; end process; MK Yap <mkyap@REMOVE.ieee.org> wrote in message news:391a8741.0@news.cyberway.com.sg... > Hi, > > I realized that shifting using sll, ror..... etc can only be done using > bit_vector... > what can i do so that my input and output port can be changed to > std_logic_vector to reflect real situation???? > > Any help is appreciated?? > MK > > ********** > LIBRARY ieee ; > USE ieee.std_logic_1164.all; > --USE ieee.std_logic_arith.all; > USE ieee.numeric_std.all; > > ENTITY test IS > PORT( > nReset : in STD_LOGIC; > BClk : in STD_LOGIC; > DataI : in bit_VECTOR (15 DOWNTO 0); > DataO : out bit_VECTOR(15 downto 0) > ); > END test; > > ARCHITECTURE p2s OF test IS > BEGIN > fedge: PROCESS(nReset,BClk) > VARIABLE tmp : integer range 0 to 7; > BEGIN > IF nReset='0' THEN > DataO <=(OTHERS=>'0'); > tmp:=0; > ELSIF BClk'event AND BClk='0' THEN > tmp:=4; > DataO <= DataI sll tmp; > END IF; > END PROCESS fedge; > END p2s; > >Article: 22559
In bygone days, the letter 'y' was written with an umlaut (German - don't know the English for that one) which is two dots on the 'y', which makes it look almost exactly like 'ij', and these characters were in fact equivalent. Jerry Avins wrote: > > Johan Kwisthout wrote: > > > > ... > > > > It's Dijkstra (turn the i and j the other way around). ... > > > > >>Johan. > > I remember the order because it looks like the letter "y" (with two > tittles) in script. The great British (later, US) optical designer > Conrady was born Conradij in The Netherlands. > > Jerry > -- > Engineering is the art of making what you want from things you can get. > -----------------------------------------------------------------------Article: 22560
Try Dini Group. They've got a board they hawk specifically for ASIC emulation with up to 6 XCV1000's on it. John Fielden wrote: > I need a multi FPGA board to do ASIC verification. So far, I've looked at > WildStar (by Annapolis Micro) and RSPE (by Viasat). > > Can anyone reccomend another board I should look at? > > Thanks, > > John -- P.S. Please note the new email address and website url -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 22561
William,
I forgot to mention, there is a second way to keep it as registers without monkeying
with the reset: You can use the syn_keep attribute on the intermediate signals to
keep them from being collapsed into an SRL16. For example a 10 clock pipeline:
signal dq: std_logic_vector(1 to 10);
--this here syn keep thingy keeps the flops as individual flops
attribute syn_keep: boolean;
attribute syn_keep of dq:signal is TRUE;
begin
process(clk)
begin
if clk'event and clk='1' then
dq<=input & dq(1 to 9);
end if;
end process;
output<= DQ(10);
With the reset trick, you don't need to bring the reset outside the component.
Again, you use the syn keep:
signal zero:std_logic:='0';
attribute syn_keep of zero:signal is TRUE;
begin
reset<=zero;
process(clk,reset)
begin
if reset='1 then
Q<='0';
elsif clk'event and clk='1' then
Q<=D;
William LenihanIii wrote:
> Rick has given a good clarification of why I want the shift reg 'distributed' in
> regular CLB/Slice registers across the chip (as opposed to the 'efficient' way of
> implementing them in the SRL16's that would be most appropriate in 99% of
> applications).
>
> Since I posted this message, I've discovered that
>
> (a) the reset solution works quite well (but does need careful documentation in
> the HDL code to explain why I need a reset that I'm not really using except to
> bring to a dummy I/O pin or uP port) and
>
> (b) more recent versions (3.4 just released) of my synthesis tool, Synopsys FPGA
> Compiler II, has a feature called "retiming", which will take some existing
> combinatorial datapath + registers, and redistribute the registers in/around the
> combinatorial logic to balance the timing in all sections of the pipeline -- this
> solution also works just fine, except that the catch is that you must have SOME
> combinatorial logic in the path, a pure shift register doesn't cause the retiming
> to occur. Fortunately, my datapath had a mux picking between 2 data sources and
> that was all I needed.
>
> Thanks to all who responded.
>
> R--
P.S. Please note the new email address and website url
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com or http://www.fpga-guru.com
Article: 22562John Fielden wrote: > > I need a multi FPGA board to do ASIC verification. So far, I've looked at > WildStar (by Annapolis Micro) and RSPE (by Viasat). Please post the web-adress of the RSPE-Board, I'm interested too. Thanks Patrick -- Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) University of Mannheim - Dep. of Computer Architecture 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 22563
On Fri, 12 May 2000 02:42:07 GMT, Herman <aerosoft@AerospaceSoftware.com> wrote: >In bygone days, the letter 'y' was written with an umlaut (German - >don't know the English for that one) which is two dots on the 'y', which >makes it look almost exactly like 'ij', and these characters were in >fact equivalent. I recall WP5.1 had a character for that, which (in my experience) noone ever used. Everyone types an 'i' and a 'j' instead of the dotted y. Johan. > >Jerry Avins wrote: >> >> Johan Kwisthout wrote: >> > >> > ... >> > >> > It's Dijkstra (turn the i and j the other way around). ... >> > >> > >>Johan. >> >> I remember the order because it looks like the letter "y" (with two >> tittles) in script. The great British (later, US) optical designer >> Conrady was born Conradij in The Netherlands. >> >> Jerry >> -- >> Engineering is the art of making what you want from things you can get. >> -----------------------------------------------------------------------Article: 22564
Forget about what the FPGA vendor says about the future of the FPGAs. Let us have discussion from professionals who are and have been working in these areas. Discussion might be or may not be limited to the following: Its true that FPGAs will never replace ASICs but will penetrate the ASIC market in one way or the other. FPGAs will be used mainly for prototyping and educational environment. There is going to be a market saturation very soon for the businesses providing cores for FPGAs. The demand for job market for FPGAs is not very huge. The expected growth for PLD industry for the year 2000 is 35% Cheers, SHAH Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22565
I have to implement the following: 1. 8032 microcontroller, 2. 64kbytes SRAM, 3. some 8 latches and two 3x8 decoders, 4. 12kHz Generator 5. 16kHz detection 6. DTMF dialer. The above is the customized solution for a telephone set for some telecom company. After some initial study, i think that Virtex could give me solution. There is also an A/D converter(which i might need) in the Virtex and such a large memory could only be implemented in an Virtex. But then i thought that since Virtex is expensive, this is not a good solution. I thought of SPARTAN II but then SRAM is out. What do u thing and suggest. Any comments........? Thanks and Regards, SHAH Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22566
I have to implement the following: 1. 8032 microcontroller, 2. 64kbytes SRAM, 3. some 8 latches and two 3x8 decoders, 4. 12kHz Generator 5. 16kHz detection 6. DTMF dialer. The above is the customized solution for a telephone set for some telecom company. After some initial study, i think that Virtex could give me solution. There is also an A/D converter(which i might need) in the Virtex and such a large memory could only be implemented in an Virtex. But then i thought that since Virtex is expensive, this is not a good solution. I thought of SPARTAN II but then SRAM is out. What do u thing and suggest. Any comments........? Thanks and Regards, SHAH Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22567
I am sorry, I firstly thought the my reply to Steven didn't cover his mail, because of that I cancelled my post. > [my cancelled post snipped] > > I believe this is like what Mentor used to sell (maybe still does). It > is the reverse of an emulator in that it allows you to connect to the > environment hardware. This saves you the trouble of writing test benches > that may or may not be an accurate reflection of the environment. I don't know any equipment & environment other than Synopsys, so, I can't talk about Mentor. But I think in the same way, i.e. such additional capabilities encourages you to design less erroneous testbenches. > The downside was that it was rather slow. You might think the hardware > would be fast, but the problem is that the software simulation of the > logic design could not keep up with the hardware. So the machine ran the > simulation for one clock cycle, used that as a vector to drive the > hardware. Then another clock cycle was simulated and two vectors were > used to drive the hardware, then three, etc... So you would have to run > the hardware with resets inbetween for (N^2)/2 clock cycles to get your > full result. Yes, the simulation speed is unfortunately limited by the equipment. I think this can not be accelerated by more powerful workstations / servers / simulation accelerators. > I think the hardware was based on a logic analyzer with pattern > generation capability from a company that Mentor bought. Do they still > sell this equipment? > [Rick] No idea. In my opinion, it is impossible to have a simulation of a design in real-time speed. This is exactly to have hardware tests on the real-silicon. In current technologies, I think, none of any simulator / environment can simulate a model in real-time speed. Please correct me if I am wrong. Utku -- I feel better than James Brown.Article: 22568
i'm newbie to this field what is the diff between an asic and fpga? sharpArticle: 22569
This is a multi-part message in MIME format. --------------E000CBB42BA99A42961ECE39 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit You might want to look at the Triscend TE5 series of CSoC chips (http://www.triscend.com). I know they have one with an internal RAM of 40K and an 8032. The rest of the circuitry you list could fit into the configurable system logic array of their chip. shahzad2512@my-deja.com wrote: > I have to implement the following: > 1. 8032 microcontroller, > 2. 64kbytes SRAM, > 3. some 8 latches and two 3x8 decoders, > 4. 12kHz Generator > 5. 16kHz detection > 6. DTMF dialer. > > The above is the customized solution for a telephone set for some > telecom company. > > After some initial study, i think that Virtex could give me solution. > There is also an A/D converter(which i might need) in the Virtex and > such a large memory could only be implemented in an Virtex. > > But then i thought that since Virtex is expensive, this is not a good > solution. I thought of SPARTAN II but then SRAM is out. > What do u thing and suggest. > Any comments........? > Thanks and Regards, > SHAH > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 || --------------E000CBB42BA99A42961ECE39 Content-Type: text/x-vcard; charset=us-ascii; name="devb.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Dave Vanden Bout Content-Disposition: attachment; filename="devb.vcf" begin:vcard n:Vanden Bout;Dave tel;fax:(919) 387-1302 tel;work:(919) 387-0076 x-mozilla-html:FALSE url:http://www.xess.com org:XESS Corp. adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA version:2.1 email;internet:devb@xess.com title:FPGA Product Manager x-mozilla-cpt:;-16464 fn:Dave Vanden Bout end:vcard --------------E000CBB42BA99A42961ECE39--Article: 22570
thanks for all the help I like the xess boards but i found a nother board at www.digilent.cc/ on a xilinx web link and it looks very resonable with a spartan fpga switches led's proto aria ect for $94 assenbled and tested. $74 unassembled. and they provided there shcematics online in pdf format Any coments? Also thanks for the e-mail responces they were very usefull MartinArticle: 22571
With SRL16 I am trying to specify an initial value without resorting to playing with tools like JBITs. It's really doing my head in. Any ideas out there? -- Tim Courtney Electrical & Electronic Engineering mobile : +44 (0)7801 250 903 The Queen's University of Belfast tel(wk) : +44 (0)28 9027 4275 Ashby Building, Stranmillis Road fax : +44 (0)28 9066 7023 Belfast, Northern Ireland, BT9 5AH e-mail : t.courtney@ee.qub.ac.ukArticle: 22572
shahzad2512@my-deja.com wrote: : Forget about what the FPGA vendor says about the future of the FPGAs. : Let us have discussion from professionals who are and have been working : in these areas. Discussion might be or may not be limited to the : following: Sure. I haven't been one of those for very long, but I do qualilfy. : Its true that FPGAs will never replace ASICs but will penetrate the : ASIC market in one way or the other. I don't know why you'd want to debate the obvious. As NRE charges go through the roof for high-density ASICs, FPGAs will continue to severely erode all but the highest-volume ASIC sockets. : FPGAs will be used mainly for prototyping and educational environment. That's a total load of crap. Ask Cisco. : There is going to be a market saturation very soon for the businesses : providing cores for FPGAs. : The demand for job market for FPGAs is not very huge. Sure. Just like the market for programmers has saturated. : The expected growth for PLD industry for the year 2000 is 35% Beats me, and as a design engineer I don't find the question interesting. Ask Dataquest. JonathanArticle: 22573
On 07 May 2000 20:48:05 +0200, Christian Mautner <at@utanet.cmautner> wrote: >Rickman <spamgoeshere4@yahoo.com> writes: > >> Christian Mautner wrote: >> > I'm using the USERCLK (being the system clock of the fully synchronous >> > design) always at the startup clock. I believe that, if CCLK is used, >> > timing constraints might be violated (since CCLK is asynchronous to >> > the system clock) at startup. Is this more carful than necessary? >> > >> > chm. >> >> This is exactly the reason that you would want to use a USERCLK for >> startup. But it may or may not be necessary depending on how your >> circuit works. If you have a reset that is external to the FPGA, then >> you can hold the entire circuit in reset when it is done configuring. >> Then when the reset is released, the FPGA will start correctly. If you >> don't have an external reset, using a USERCLK for startup would be a >> good idea. But then you have to tell the design software that this is >> what you are doing by adding the startup block to your design and >> showing where the USERCLK is coming from. Just selecting the bit in the >> configuration stream is not enough. >> > >Certainly. This is where this thread started, selecting the bit, but >not using the startup block. If USERCLK is selected, the startup clock >input should fed by the system clock, as I said. > >Another point is: What timing can I expect from the GSR signal? I >mean, at a clock cycle period of t, how small may t be, so that all >flip flops are ready at the first clock edge after the GSR? And is >this covered by any timing constraints? I'm not sure if I've missed any posts in this thread, but I don't think a USERCLK/GSR scheme is a good way to go. None of the important numbers are in any datasheets I've checked, for 4K or Virtex. I had a quick look with the timing analyser last year and decided that it might be possible at clock rates under 30MHz, but I didn't check in detail. The reason the numbers aren't documented is that GSR is simply an internal resource (ie. at the ASIC level for testing, not the level we see), and no-one at Xilinx seems to have quite decided whether they should make it completely available to us or just throw it away. The result is that we get a half-way solution - we can access the net, but we've got no timing for it. Xilinx seems to be silently encouraging people to forget GSR - a big mistake, IMO. My current-favourite GSR solution is to start the device's internal clock after GSR has released. On my last Virtex I synchronised GSR, and used the result as a synchronous reset on an FSM which produced the device's main internal clock. This clock therefore only started after GSR was released, and everything on this clock used GSR as an async reset. Evan and Xilinx couldn't quite bring themselves to hide it completely from usArticle: 22574
LC, I'm using adders, block ROM's and multipliers so far. I'll probably use more if I can figure out how to simulate them. Your idea to use the edif netlist for simulation is interesting. Viewlogic provides an edif netlist reader called edifneti. Maybe I can use that to get a simulateable netlist. Thanks -- Pete Dudley "Kang Liat Chuan" <kanglc@agilis.st.com.sg> wrote in message news:391b577a.0@news.cyberway.com.sg... > Pete, > > Coregen generates a .edn file (older version generates a .xnf file) which is > in edif format. I am not sure how viewlogic can reference this edif file > from within a symbol, but in Mentor Graphics, I set a FILE property and > specify the full path to the edif file in the "value" field. > > I have tried to use the .vho file in VHDL designs, so that I can simulate in > Mentor Graphic's Modelsim, but the Coregen documentation was not very > helpful. When you said "makes heavy use of Coregen modules", what actually > are the modules you are using? > > Regards, > LC > Pete Dudley <padudle@sandia.gov> wrote in message > news:8fevje$9k0$1@sass1828.sandia.gov... > > Hello All, > > > > I'm currently doing a Virtex design that makes heavy use of Coregen > modules. > > I want to do the majority of my design entry in schematic under Innoveda's > > (Viewlogic's) Viewdraw. > > > > I want to be able to use simulation for design verification but the > Coregen > > modules present a problem with respect to simulation models. The Coregen > > tool seems to me architected for people who use pure VHDL design entry. In > > particular Coregen does not generate a simulateable netlist for the > > schematic user. Rather, only a .vho file is generated which tells how to > > instantiate the Coregen module in VHDL and it gives a configuration > > statement that you can use to point your macro to the appropriate generic > > VHDL mode. > > > > This is pretty unwieldy for a designer using schematic entry. Has anyone > out > > there found a smooth simulation flow for schematic based simulation of > > Xilinx Coregen modules? > > > > Thanks in advance for your help. > > > > > > ******************************************************************** > > Pete Dudley > > Sandia National Labs > > Dept 2336 MS 0505 > > PO BOX 5800 > > Albuquerque, NM 87185 > > voice: 505.844.5565 fax: 505.844.2925 email: padudle@sandia.gov > > http://www.sandia.gov/RADAR/sarcap.html > > Signal Processing in Hardware and Software > > ******************************************************************** > > > > > > > >
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