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8087 is a math coprocessor and does calculations in FP numbers. Is it wise to implement 8087 in an FPGA. I want to do this for a University project. Please comment and advice. Thanks in advance. Regards, SHAHZAD Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22776
"Jann" <jannkaminski@hotmail.com> wrote in message news:T5zW4.193$tM6.9546@newsfeed.avtel.net... > The company I work for develops polymer light emitting matrix displays (not > 7-segment or alphanumeric). That's kind of cool. What kind of luminous efficiency do they get relative to LEDs, fluorescent lamps coupled with LCDs, etc.? > I would like to develop a custom controller that utilizes the features of > our displays for monochrome and gray-scale applications. Are there any > public libraries, app notes, public implementation of FPGA devices used as > Display Timing Controllers. The searches I have done only bring up > 'captured' applications in embedded products. I would search this newsgroups for people asking for "VGA controllers." That request comes up semi-regularly. Off the top of my head, I'd surf on over to www.xess.com. They sell FPGA prototyping boards that include VGA connectors and have an application note on their implementation of the video generation circuitry. ---Joel KolstadArticle: 22777
Larry Doolittle wrote: I think you get an even more useful yardstick by counting 4-LUTs, then you can sort of compare it with Altera too, taking into consideration the carry logic differences of course. > > For a while I was counting CLB's, but Xilinx changed the architecture > enough from 40xx and Spartan to Virtex and Spartan-II that you have to > watch factors of two. I guess (for now) you can use "Slices" as a > meaningful comparison, where 1 Slice = 1 40xx CLB = 1/2 Virtex CLB. > > : On a more significant note, I can't say that I understand the carry > : chain description in the Spartan II datasheet. I can't seem to cut and > : paste from the document (odd, I can do that with most other PDF > : files...) but the text says, "The Spartan-II CLB supports two separate > : carry chains, one per Slice. The height of the carry chains is two bits > : per CLB." The Virtex carry chain is described the same way so that sheds > : no additional light on the matter. > > The point is that they have not rearranged the carry chain (much) from > the 40xx and Spartan line. I beg to differ here. True, the carry chain connects two luts in a cell (by whatever name), and the connections run vertically, but thats where the similarity ends. The new carry chain is after the lut, where the 4K/Spartan one is in front of the LUT. This has some subtle implications, especially if you are using the carry chains for something other than addition/subtraction/inc/dec (you can do non-math with them things). In that respect, the 4K carry chain was a bit more useful because you could do things like wide ands and first ones detects very quickly without using up LUT resource, and there are some applications like a first one's where you need logic on the output side of the carry chain at each bit. That takes two levels of logic to do in Virtex, where it was only one in spatan/4K. On the otherhand, I'm told the new carry chain is more synthesis friendly (although I'm not sure I'd agree on that one...Try to convice the tools to use the flip-flop reset input and make a loadable counter in one level of logic. It can be done, but convincing the synthesizer can be a tremedous waste of time). -- P.S. Please note the new email address and website url -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 22778
Xilinx has an app note on the subject of plug and play that covers the ISA interface, probably much more gussied up than you need. You'd still have to gin up the motorola side, but at least it would be half done. Suttipan Limanond wrote: > Hi: > > I'm trying to find a ref. design for ISA interface on FPGA or CPLD for > motorola processors. I can't seem to find one on the internet. Any > suggestion is appreciated. > > Thank you very much, > > Suttipan Limanond. -- P.S. Please note the new email address and website url -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 22779
This is a multi-part message in MIME format. --------------FE04ADE6AE3C5F2717DF19D1 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hello shazad, To my knowledge , Speed will be factor . If you dont care about speed . Choose a FPGA which provides a good support for Arithmetic operations . Cheers and all the best kamal shahzad2512@my-deja.com wrote: > 8087 is a math coprocessor and does calculations in FP numbers. Is it > wise to implement 8087 in an FPGA. I want to do this for a University > project. Please comment and advice. > Thanks in advance. > Regards, > SHAHZAD > > Sent via Deja.com http://www.deja.com/ > Before you buy. --------------FE04ADE6AE3C5F2717DF19D1 Content-Type: text/x-vcard; charset=us-ascii; name="raja.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for kamal Content-Disposition: attachment; filename="raja.vcf" begin:vcard n:;kamal raja tel;home:1/240,carmody road , st lucia , australia tel;work:Computer science and electrical engineering x-mozilla-html:FALSE adr:;;;;;; version:2.1 email;internet:raja@elec.uq.edu.au fn:kamal raja end:vcard --------------FE04ADE6AE3C5F2717DF19D1--Article: 22780
>> For a while I was counting CLB's, but Xilinx changed the architecture
>> enough from 40xx and Spartan to Virtex and Spartan-II that you have to
>> watch factors of two. I guess (for now) you can use "Slices" as a
>> meaningful comparison, where 1 Slice = 1 40xx CLB = 1/2 Virtex CLB.
And Virtex2 has 4 slices/8 LUTs in a CLB...
I guess we will get Virtex3: 8 slices/16 LUTs
Virtex4: 16 slices/32 LUTs
Virtex5: 32 slices/64 LUTs
at which point we stop using the CLB name and call it an XC2064--.
Article: 22781Try the APS-X208 on www.aps-euro.com Laurent Suttipan Limanond a écrit : > Hi: > > I'm trying to find a ref. design for ISA interface on FPGA or CPLD for > motorola processors. I can't seem to find one on the internet. Any > suggestion is appreciated. > > Thank you very much, > > Suttipan Limanond.Article: 22782
Could anyone help me finding FPGA core for Xilinx FPGAs for V23 and DTMF/ Regards, SHAHZAD Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22783
Why I can't place power symbols on my schematic?Article: 22784
sorry i am using Foundation 2.1i by Xilinx with a XC9500 Simon Bilodeau <simon.bilodeau@htrc.com> a écrit dans le message : lNRW4.5112$BD1.153040@weber.videotron.net... > Why I can't place power symbols on my schematic? > > > >Article: 22785
Given the amount of operations that must be integrated into such a modem to make it useable, and considering that V23 modems are very slow (1200 / 75 Bps) a microprocessor based solution would be much simpler, and is ready made : http://www.scenix.com/virtual/download/v23Kit.html there is also a similar project built with PIC processors Eric. --------------------------- shahzad2512@my-deja.com wrote: > Could anyone help me finding FPGA core for Xilinx FPGAs for V23 and > DTMF/ > Regards, > SHAHZAD > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 22786
The display has a luminance efficiency of 10cd/A (it is a current driven polymer diode device) . The power efficiency (~12 lumens/watt) is better than LED, LCD w/ backlight, VFD. Check out www.uniax.com , and look for a commercial display in about a year in a handheld application. JannArticle: 22787
Also check www.tech-forge.com. My thesis documents interfacing (4) 8051 controllers through an Altera 10K30 onto the ISA bus. It is a pretty simple interface, but pretty slow. -steen In article <392B41AF.D81C457E@ksc.th.com>, Suttipan Limanond <limanond@ksc.th.com> wrote: >Hi: > >I'm trying to find a ref. design for ISA interface on FPGA or CPLD for >motorola processors. I can't seem to find one on the internet. Any >suggestion is appreciated. > >Thank you very much, > >Suttipan Limanond.Article: 22788
Hi, Two clocks, only constraining one. It's sourced from io. I am clocking ESB ram with it. I do not know about Auto Global. After starting fresh and running this again, it seemed to clear up the quartus db and I didn't get the error, but then I did see it again on a later revision. Thanks Michel Le Mer wrote: > Hello > > How many clock do you have in your design? Is your in > question clock supply directly from an I/O or built inside > the fpga? Do you use ESB ram without clocking the ESB > input / output? > In the Quartus software the Auto Global is ON by default, > what about an equivalent option with Leonardo? > > Good luck > > * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is BeautifulArticle: 22789
Simple 256k Dram tester code Hi I would like to program a FPGA to write to and read from an older 256k Dram. This is to check for errors i.e. data in should = data out unless a cell is damaged or upset from environmental testing I would need to generate RAS, CAS, the address (a0 to a8)(512 rows x 512 column=262144 cells), and data (one bit hi or low). I will use up counters to provide the address and data decoding. Should I use a state machine or just multiplex the addressing? Does anyone have some VHDL code that I could refer to or adapt for my application? I am looking for a simple way to do this. Thanks M P Brown. Ps if code is to big to post it can be emailed to: mpbrown@magma.caArticle: 22790
Ray Andraka wrote: > > Rickman, > > Those are marketing logic cells, not to be confused with the actual logic. > The way they get the numbers is by figuring how many 4 LUTs would be > required to get the same logic. Nonsense as far as I'm concerned. It is > much better, IMHO to understand what the CLB/slice is capable of, then count > the CLBs. That part I understand completely. I always count LUTs since that is a convenient point to compare with other vendors. My point is that the "Logic Cell" count does not belong in the data sheet. It should be limited to the marketing glossies that everyone pretty much ignore. > Now as far as the slice/CLB confusion, the two slices in a CLB are for the > most part independent of one another. Pretty much the only time the two > slices get considered together is when you use the F6 mux, which lets you > implement any 6 input logic function in a CLB. I think things would have > been alot clearer (and some problems in the mapper would have gone away) if > they did away with the notion of a SLICE and called what is now called a > slice a CLB. Also, the delay between slices within a CLB is shorter than > delay between slices in adjacent CLBs. > > That said, treat the two slices indpenedently when considering the carry > chain. The carry chain for each slice is two bits, and connects in a chain > to the same slice in the CLB neighbors above and below. You can't connect > the carry from one slice to the other, at least not and stay on the carry > chain. The carry chain structure is on the output side of the LUT, rather > than on the input side like it was in the 4K /spartan parts. Figure 5 on > page 7 of the databook at http://www.xilinx.com/partinfo/ds003.pdf is a > pretty accurate depiction of the logic inside the slice. As an adder, the > carry chain mux selects the previous carry chain output if the A and B > inputs to the LUT don't match (the LUT is programmed as an XOR for a simple > adder), so that if there is one '1 in the input at this bit, the carry in is > propagated. If there is not just one '1' input, then the value of an input > to the LUT is propagated, essentially propagating a '1' if both inputs are > '1's or '0' if both inputs are '0's. The and gate allows you to gate the > carry input parallel to a gate added into the LUT so you can do a 2xN > partial product for a multiplier in one column of slices. > > Since the two slices are independent you can have two carry chains running > up a column of CLBs. The carry chains aren't meant to be combined to make > one carry chain. There are fast connects dedicated to carry chain running > vertically from one slice to the same slice in the neighboring CLB above. > Additionally there are fast connections from the CLB output to each of the E > and W neighbors, but that one is not related to the carry chain. This makes sense. The way I understand it is that the new CLB should be considered as two of the old CLBs arranged horizontally. So you have two carry chains and two fast carry routes. I wonder why Xilinx did not list the routing time in the data book like they did for the XC4000 series? I could calculate the timing of an adder in the old logic without ever starting up the software. I think I understand why they rearranged the logic the way they did as it gives you full 6 input functions and nibble wide registers. What I don't understand is why they don't document the new parts as well as they did the older logic. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22791
Suttipan Limanond wrote: > > Hi: > > I'm trying to find a ref. design for ISA interface on FPGA or CPLD for > motorola processors. I can't seem to find one on the internet. Any > suggestion is appreciated. > > Thank you very much, > > Suttipan Limanond. I can't help you with a reference design, but are you looking for a target or a master interface? Is the Motorola processor controlling the bus or just a slave on it? This makes a big difference. As a slave you only need to decode the address lines and a small number of control lines. As a master you will need to drive a very strange split address bus, deal with both 8 and 16 bit transfers and may need to handle interrupts and DMA depending on your application. All of this will be implementation dependant. In the slave case, it is a very simple design that you don't need a reference design for (you can use a schematic for a serial port board perhaps). In the master case, your needs will dictate what you end up with. I suggest that you grab a good ISA reference book jump in. One nice thing about rolling your own ISA bus interface is that it runs very slowly compared to today's busses. ISA uses an 8.33 MHz bus clock. Such a slow clock should make it very easy to meet timing in an FPGA or memory. If you would like consulting help, drop me line. I have done ISA interfaces a few times and am currently working on a UART emulation for the ISA bus. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22792
shahzad2512@my-deja.com wrote in message <8gflvq$jr4$1@nnrp1.deja.com>...
>8087 is a math coprocessor and does calculations in FP numbers.
Yes, I know.
>Is it wise to implement 8087 in an FPGA.
Probably not, since floating-point math is one of the few things FGPAs don't
do well.
also, I think that Intel might step all over your buttocks if you tried to
sell it.
> I want to do this for a University project.
you may want to consider doing a vending machine.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 22793Hi, i've a pb, it's my first time i must implement in FpGA so i'm a novice, i want all what you are about DCT implementation using FPGA or anything who can help me because i'm a beginner and i must take all what i can find about DCT and implementation using FPGA after i'll can begin too learn seriously because some books are not very clear so, pliz help me !! thx in advance SEBArticle: 22794
> I think I understand why they rearranged the logic the way they did as > it gives you full 6 input functions and nibble wide registers. What I > don't understand is why they don't document the new parts as well as > they did the older logic. Why do you need documentation? Just push the big Green button and the software will take care of everything for you. ;) -- These are my opinions, not necessarily my employers.Article: 22795
Try www.hotgurus.com Dan wrote: > I am looking for work as an FPGA designer. > My specialty is graphics/video/imaging. > > Are there any good web pages dedicated to this field ? > > Thanks > DanArticle: 22796
"Simon Zhang" <zhangyuc@online.sh.cn> writes: > Hi, all, > > I am in a project of DSP embedded ASIC, hope to utilize a FPGA with large > gatecount volumn and IO pins, as well as internal SRAM. Seems that Xilinx > Virtex E is superior in these fields, do I have any other choice? So as to > Xilinx VirtexE, any larger types than XCV2000E, such as 3200E? And is > XCV2000E available(on North America market) in FG860 and FG1156? Altera 20KE series? Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 22797
Please do not feed the trolls On Tue, 23 May 2000 03:14:02 GMT, "Dan" <daniel.deconinck@sympatico.ca> wrote: >eom > > > For Email remove "NOSPAM" from the addressArticle: 22798
Andy Peters wrote: > > shahzad2512@my-deja.com wrote in message <8gflvq$jr4$1@nnrp1.deja.com>... > >8087 is a math coprocessor and does calculations in FP numbers. > > Yes, I know. > > >Is it wise to implement 8087 in an FPGA. > > Probably not, since floating-point math is one of the few things FGPAs don't > do well. > Given the size of modern FPGAs there certainly is enough logic in a FPGA to implement such a device. However, implementing a true clone of a 8087 is probably not practical for a short term project. A subset of the functionality is certainly possible. > also, I think that Intel might step all over your buttocks if you tried to > sell it. > Isn't the 8087 over 17 years old? What legal mechanism would Intel use to try and control the sale? --------------------------------------------------------------------- | Dr. Kevin Dale Kirmse, PhD EE | Portable System Design, High Speed Serial Links | FPGA Design, Video Hardware, Graphics Hardware | | King of Prussia, PA 19406 | kirmse@netaxs.com ---------------------------------------------------------------------Article: 22799
shahzad2512@my-deja.com wrote: > > 8087 is a math coprocessor and does calculations in FP numbers. Is it > wise to implement 8087 in an FPGA. I want to do this for a University > project. Please comment and advice. > Thanks in advance. > Regards, > SHAHZAD > > Sent via Deja.com http://www.deja.com/ > Before you buy. If you think you are up to the task of reverse engineering and specifying a chip as complex as an 8087, then this would likely be a good project for insertion into an FPGA. Someone indicated that FPGAs are not good for floating point math, but that is not correct. The only real difference in floating point and fixed point math as far as the hardware is concerned is that you have an exponent that must be dealt with and the mantissia needs to be normallized before storing back into registers or memory. But there is nothing magical about floating point math. As long as you understand what the chip needs to do with each instruction, I think the hardest and largest part of the design will be designing the instruction decode (other than verifying that it works). The only issue with floating point math is that you can't expect to synthesize it automatically from an HDL. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com
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Compare FPGA features and resources
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