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rob_dickinson@my-deja.com wrote: > > In article <lsIP4.105451$2D6.2668300@news20.bellglobal.com>, > "Dan" <daniel.deconinck@sympatico.ca> wrote: > > Can only be done with experience and the proper tip. > > > > Do not try it without guidance from an expert and without the right > tip. > > > > Dan > I don't suggest that we squabble about this all day but... ...snip... > Think of your iron as a very small wave solder machine and you've got > the idea. If you go to a show and watch a demo of a PACE machine (with > its quite clever surface tension friendly tip) you will see experts do > a 240PQFP in under 2 minutes, remove it with a paint stripper and put > the same device down again and again. > > Sent via Deja.com http://www.deja.com/ > Before you buy. What do you mean "remove it with a paint stripper"? You mean a hot air gun? I have an engineer who insists on using a torch with a very high temperature and seems to damage boards after about two passes. Is the hot air gun a better way to remove parts? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22251
Hello, I search a very small design to use a Xilinx in Serial Slave Mode. I have do a design with this mode but I have any incomprehensible problems. So perhaps it's just an dummy error from me. Anyone known a example of the Slave Serial Mode on the net ? Thanks Gordh,Article: 22252
Dear recruiting team, - you are looking for a highly-motivated digital design/systems/CAD engineer? - you need an engineer who is fascinated of computer technology, especially parallel/vector architectures, System-On-a-Chip and high-speed datacommunications? - you ask for an employee who's motivation to study electrical engineering was generated by Seymour Cray and his machines? - you are searching for a creative mind combined with strong problem solving capabilities? - you want a new member for your team, who is committed to excellence and success? - you desire an open-minded person who is programmed to reach the goal, increasing your efficiency and pushing the limits? Try this..... => http://www.asic.cc Best regards, Andreas Schmidt P.S.: Everything is possible, if you really want it... * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 22253
Hi, I wonder why wait until statement when used in a process can generate a warning of : Warning: Clock signal is not in the sensitivity list. "pClk" in routine ntyCounter line 18 in file '/home/yeowk/vhdl.dir/MyProj.dir/Vhdl.dir/arcCounter.vhd' (HDL-400) I thought that code (1) is the same as code (2) functionally: process -- Code(1) begin wait until rising_edge(clk); : : : end process; process(Clk) - Code(2) begin if rising_edge(Clk) then : : : end if; end process I check the Solvit in Synopsys but cannot find any workaround. Can someone enlightened why the above statement is not accepted in synthesis engine(particular Synopsys). By the way, code(2) pass the synthesis without warning! Can you explain? Yeo Wee Kwong, Sky (Mr)Article: 22254
In article <390FE618.FA839E5A@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > rob_dickinson@my-deja.com wrote: > > > > In article <lsIP4.105451$2D6.2668300@news20.bellglobal.com>, > > "Dan" <daniel.deconinck@sympatico.ca> wrote: > > > Can only be done with experience and the proper tip. > > > > > > Do not try it without guidance from an expert and without the right > > tip. > > > > > > Dan > > I don't suggest that we squabble about this all day but... > ...snip... > > Think of your iron as a very small wave solder machine and you've got > > the idea. If you go to a show and watch a demo of a PACE machine (with > > its quite clever surface tension friendly tip) you will see experts do > > a 240PQFP in under 2 minutes, remove it with a paint stripper and put > > the same device down again and again. > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > What do you mean "remove it with a paint stripper"? You mean a hot air > gun? I have an engineer who insists on using a torch with a very high > temperature and seems to damage boards after about two passes. Is the > hot air gun a better way to remove parts? > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX Sorry, a bit of american <> english translation required, the engineers I circle in would all know what I meant. I meant that they used a large hot air gun simillar to the type used to apply heat shrink insulation (allthough probably temperature controlled) rather than the little dainty re-work kit which PACE and others also sell. As my memory is being jogged I think they used their clever and expensive PQFP removers at the show and a "paint stripper" when the salesman visited our site. The problem with removing PQFPs is that modern ones often have a copper heat slug (eg the SHARC). The more air you blow the less heat is conducted away (into the silicon?)and the quicker you will get the solder at all 240 pins to be molten for the same instant. We normally pay a bit more for development PCB's as you can rework them for longer before pads start lifting. If you've ever looked at the PCBs used for assembly training their much thicker with no pins attached to a ground pin! I'm not an expert, I have probably removed and replaced about 30 high density devices over the last 5 years, but watched over the shoulder of many more. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22255
Hi, I'm currently using the Foundation software (2.1i), and designing a schematic with one top-level and several sub-levels (which use VHDL and FSM's) for the Xilinx FPGA XCS30XL. The FPGA has to communicate with a processor. I'v tried to design a bidirectional bus (databus) by using the LogiBLOX module Inputs/Outputs. I've made a bidirectional buffer. One side of the buffer is connected to the output-pads and the other side split up in DIN and DOUT. These buses go to several sublevels. The DIN-bus will internally be clocked into DFF's(when selected). From several sub-levels the DOUT-bus will seperatly be activated when tristate-buffer is enabled. So the DOUT-bus is buffered twice, first in a sublevel using tristate-buffers and secondly at the toplevel using normal buffers! But when I trie to implement the schematic I always get an error-message that this twice buffering isn't allowed! Why? Has anyone a suggestion how to make a bidirectional bus, which is connected to several sublevels? Kind regards, Jurjen Boss Mirbachstraat 19 6471 CW KERKRADE Tel.: 045 - 5670098 Email: jboss@wxs.nlArticle: 22256
news:2063ed28.2d0ad971@usw-ex0102-016.remarq.com... > I am taking a class in computer organinzation and design. We > can use XLINX or Altera. I chose to user Altera MAX PLUS II. I > need a good web source on how to create modules. Can you help > me please? > > Thanks, > > Erica > A good start would be www.altera.com, and search around for some examples. Other than that, creating a module is not *really* Xilinx/Altera/Etc specific, especially on first pass. Thus, just do a web search on VHDL/Verilog (depends on what language you are using) Once you start to get timing results, then you may need to make some changes that reflect the strengths of the architectures. Cheers, XanatosArticle: 22257
Why couldn't the FPGA companies but some flash rom internal to the fpga that can be written but never read...then just burn it once at the factory and you are done...and since it's flash, you still have the reprogramability option. Craig Jacobs In article <8eno4j$88j$1@nnrp1.deja.com>, Greg Neff <gregneff@my-deja.com> wrote: > In article <390F5925.CC48CA69@raytheon.com>, > Robert Posey <muddy@raytheon.com> wrote: > > > > You also had better be really, really sure that external power > transients can't > > cause the FPGA to dump its memory, or trigger its reset circuit. I > wouldn't > > feel very good about using external power at all, but you will still > face > > ground spike problems. > > Correct. With our microprocessor circuit, the code SRAM was write > protected unless it was connected to the production test fixture. > Also, there is no reset and/or reconfiguration circuit to worry about > in an SRAM. > > > In addition, you face potential problems with having > > the FPGA outputs being powered, while the rest of the circuit is not > powered. > > This could damage the other circuits. > > Again correct. You could use a "power no good" signal to tri-state all > the FPGA outputs. > > I can see applications where this technique would be useful, outside of > mainstream production. For example, if a small company is > demonstrating new technology to a potential licensee (or anyone else > for that matter), then proof-of-concept hardware could be built like > this, to prevent IP rip-off. > > -- > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22258
Why couldn't the FPGA companies put some flash rom internal to the fpga that can be written but never read...then just burn it once at the factory and you are done...and since it's flash, you still have the reprogramability option. Craig Jacobs In article <8eno4j$88j$1@nnrp1.deja.com>, Greg Neff <gregneff@my-deja.com> wrote: > In article <390F5925.CC48CA69@raytheon.com>, > Robert Posey <muddy@raytheon.com> wrote: > > > > You also had better be really, really sure that external power > transients can't > > cause the FPGA to dump its memory, or trigger its reset circuit. I > wouldn't > > feel very good about using external power at all, but you will still > face > > ground spike problems. > > Correct. With our microprocessor circuit, the code SRAM was write > protected unless it was connected to the production test fixture. > Also, there is no reset and/or reconfiguration circuit to worry about > in an SRAM. > > > In addition, you face potential problems with having > > the FPGA outputs being powered, while the rest of the circuit is not > powered. > > This could damage the other circuits. > > Again correct. You could use a "power no good" signal to tri-state all > the FPGA outputs. > > I can see applications where this technique would be useful, outside of > mainstream production. For example, if a small company is > demonstrating new technology to a potential licensee (or anyone else > for that matter), then proof-of-concept hardware could be built like > this, to prevent IP rip-off. > > -- > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22259
In article <390FE514.FC8FBE84@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: >Paul Walker wrote: >The FPGA companies don't want to have to make their profit selling >apples at the market rate when they can be selling golden apples at much >higher prices and profits. Remember how much it costs to run a fab! > >My problem is more of a board space issue. I need several FPGAs on the >board to each control a separate IO module. Because the module can be >any one of N different types, the FPGA has to be loadable with the >corresponding design for that module. This makes it hard to combine >several module interfaces into one FPGA. So I only need about 45 IOs >which I might be able to get in a 64 pin package if they made it. A 64 >pin TQFP is a very small animal and would be much easier to route than >the 100 pin TQFP I have to use now. Yes, but this is an apple market, not a golden apple market. It is just a "metric ton" of apples market. :) So if you did see more 64 pin and even lower pin count devices, you can bet that they will be TQFP, SOIP, BGA, or some other very small outline, fine pitch packages. Of little use to hobbyiests who aren't going to have someone else assemble the prototype. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 22260
csjacobs@my-deja.com wrote: > > Why couldn't the FPGA companies put some flash rom internal to the fpga > that can be written but never read...then just burn it once at the > factory and you are done...and since it's flash, you still have the > reprogramability option. > > Craig Jacobs > If a company thinks your IP is worth it, it would be no big deal to strip the chip and read the Internal Flash ROM. Its not trivial by any means, but I have heard from a source of unknown quality. Semiconductor Companies have groups that reverse engineer other companies parts to see how they work. Of course they never, ever use protected idea. :) MuddyArticle: 22261
Peter Alfke wrote: > > Well, this newsgroup is supposed to be technical, not commercial. > But (the other) Peter asked the question, and here is the answer: > > As of May 2000 you can buy an XC2S15 in quantity 1 through 24 for $ 7.10 > : > > You get 96 CLBs, i.e 384 LUT / flip-flop combinations ( Logic Cells ) > plus four dual-ported BlockRAMs, each 4096 bits > plus four DLLs > plus 60 I/Os with lots of options. > > That's less than 2 cents per flip-flop plus associated logic, > with 16K bits of RAM and four DLLs thrown in for free. > > We just finished the design of a 256-deep, 16-wide FIFO with independent > read and write clocks running >100 MHz, that uses only half the memory > plus 10% of the CLBs on this chip. > > "This is not your father's XC3020 anymore..." > > Peter Alfke Peter, I am starting a new design that is similar to my existing one. I need one FPGA with lots of IO (~200) and three smaller ones. The current board is using a 256 pin BGA (221 IOs) and three 100 pin TQFPs (73 IOs each). They are almost put on the board with a shoe horn. If I don't want to lose any IOs, are FP BGAs my only option for using the XC2S parts? Checking the data sheet, I see that the XC2S15 and 30 will be out in a 100 pin VQFP. Any idea when? Actually this package has 13 fewer IOs than the one I am using now. If I loose IOs on the smaller parts, I will need to pick up IOs on the large part. Fine pitch BGAs very hard to use since they require very fine geometries on the PC board (smaller than 5/5 design rules). Does the Xilinx web site provide info on board routing with the fine pitch BGA and CS packages? Looking at the package diagrams, I don't see how I can route the IOs and still be able to add decoupling caps close to the Vss and Vdd pins. I can't combine all three of the small parts into one larger part unless I can get software to support segmented design and partial configuration. I have to manage the three chips as independent designs that get loaded with different logic depending on what modules are attached to the board. With up to dozens of possible modules in the future, the logistical problems would be enormous if these three chips were combined. N**3 is a much larger number of designs than I want to support, even for small N. :) I checked the pricing on some larger XC2S parts and found that they are not all that cheap. The XC2S100-5FG256CES is $65.60 at qty 25 from Avnet and the XC2S50-5FG256CES is $49.55. Are these prices a bit high because they are engineering samples? Can you tell me what target price they have in a month or two? How about the XC2S150 in the FG456 package? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22262
Maurice wrote: > > Hi, > > I'm currently using the Foundation software (2.1i), and designing a > schematic with one top-level and several sub-levels (which use VHDL and > FSM's) for the Xilinx FPGA XCS30XL. The FPGA has to communicate with a > processor. I'v tried to design a bidirectional bus (databus) by using the > LogiBLOX module Inputs/Outputs. I've made a bidirectional buffer. One side > of the buffer is connected to the output-pads and the other side split up in > DIN and DOUT. These buses go to several sublevels. The DIN-bus will > internally be clocked into DFF's(when selected). From several sub-levels the > DOUT-bus will seperatly be activated when tristate-buffer is enabled. So the > DOUT-bus is buffered twice, first in a sublevel using tristate-buffers and > secondly at the toplevel using normal buffers! But when I trie to implement > the schematic I always get an error-message that this twice buffering isn't > allowed! Why? Has anyone a suggestion how to make a bidirectional bus, which > is connected to several sublevels? > > Kind regards, > > Jurjen Boss > Mirbachstraat 19 > 6471 CW KERKRADE > Tel.: 045 - 5670098 > Email: jboss@wxs.nl I am not sure what the exact error message is, but what you are describing should work just fine. I have done this many times in the past. The lower level tristate buffers should be standard TBUFs and the top level output buffers should be OBUFs. I forget the name of the input tristate buffers, it may be IBUFT. But that does not sound like it is where you are having problems. Other than that, it should work. Perhaps you can cut and paste the error message. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22263
They could put Flash memory into the FPGA if it was really worth it. But that causes several problems that Peter Alfke has pointed out when people ask about Flash vs. SRAM technology. Adding Flash to a logic part requires extra mask steps and delays the introduction of the latest and greatest processing technology. This means that the chip will be one shrink back, have a larger die size and cost more. Certainly if they won't use flash for the configuration bits, they won't do it for a not universally used security feature. I don't know, but maybe a one time programmable section could be added rather than Flash, but likely any of the available technologies will have the same problem as the Flash. csjacobs@my-deja.com wrote: > > Why couldn't the FPGA companies put some flash rom internal to the fpga > that can be written but never read...then just burn it once at the > factory and you are done...and since it's flash, you still have the > reprogramability option. > > Craig Jacobs > > In article <8eno4j$88j$1@nnrp1.deja.com>, > Greg Neff <gregneff@my-deja.com> wrote: > > In article <390F5925.CC48CA69@raytheon.com>, > > Robert Posey <muddy@raytheon.com> wrote: > > > > > > You also had better be really, really sure that external power > > transients can't > > > cause the FPGA to dump its memory, or trigger its reset circuit. I > > wouldn't > > > feel very good about using external power at all, but you will still > > face > > > ground spike problems. > > > > Correct. With our microprocessor circuit, the code SRAM was write > > protected unless it was connected to the production test fixture. > > Also, there is no reset and/or reconfiguration circuit to worry about > > in an SRAM. > > > > > In addition, you face potential problems with having > > > the FPGA outputs being powered, while the rest of the circuit is not > > powered. > > > This could damage the other circuits. > > > > Again correct. You could use a "power no good" signal to tri-state > all > > the FPGA outputs. > > > > I can see applications where this technique would be useful, outside > of > > mainstream production. For example, if a small company is > > demonstrating new technology to a potential licensee (or anyone else > > for that matter), then proof-of-concept hardware could be built like > > this, to prevent IP rip-off. > > > > -- > > Greg Neff > > VP Engineering > > *Microsym* Computers Inc. > > greg@guesswhichwordgoeshere.com > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22264
In article <8epfc4$4n3$1@nnrp1.deja.com>, csjacobs@my-deja.com wrote: > Why couldn't the FPGA companies but some flash rom internal to the fpga > that can be written but never read...then just burn it once at the > factory and you are done...and since it's flash, you still have the > reprogramability option. > > Craig Jacobs (snip) Now that sounds like a helluva good idea. Flash instead of SRAM. It would be nice to hear from Xilinx about this idea... -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22265
Definately interested!
Eric wrote:
> Hi !
>
> I was in the same situation not too long ago.
>
> I bought 10000 gates Spartan devices in PLCC84 package (exact number is
> XCS10-3PC84C)
> on the net from Insight Electronics. I paid 18.10 US for them (and 10.00 for
> XCS05 (5K gates))
> in 3 pcs qty (min order is 50 $ and there is no shiping charges to US (15$ to
> Canada)).
>
> here is a list of distributors in N. America :
> http://www.xilinx.com/company/sales/na_disti.htm
>
> Uploading the bit stream to the device is easy, either using the Xilinx parallel
>
> cable or
> designing your own.
>
> I choosed the second option, and all it take is to connect the following pins :
>
> - ground & VCC (even works stray powered by the parallel interface signals)
> - PROGRAM pin (Pin 55) to pin 16 (INIT) of the parallel interface with a 470pF
> capacitor to ground (to prevent noise from other signals in the parallel cable
>
> to reset the device)
> - DIN (pin 71) to pin 2 (D0) of the parallel interface
> - CCLK (pin 73) to pin 1 (STROBE) of the parallel interface
>
> You'll find the source code at the end of this post.
>
> If there is interrest, I can make the loader executable (Windows) availiable as
>
> freeware.
>
> Next step was to add a LED and a resistor to pin P3, start a new project in
> Xilinx
> Foundation software, go to the schematic editor, drop an "Osc4", a "obuf" and a
> "opad"
> components, connect "F15" output of Osc4 to Obuf and obuf to Opad.
>
> Then double click on the Opad, and in the symbol properties screen, add the
> following parameter :
> Name : LOC
> description : P3
>
> Compile, upload to the device, and when your LED starts blinking, you've got it
> and sky is the limit ;-)
>
> Unlike processor based design that are somewhat painful to kickstart, using
> Xilinx chips was really easy and nearly all worked well on the first try.
>
> hope this helps,
>
> Eric.
>
> PS : Xilinx devices usage is somewhat addictive <G>
> ----------------------------------------------------------------------------------------------
>
> "R. T. Finch" wrote:
>
> > Hi, I'm new to fpga designs. I'd like to experiment with some (at home) (I
> > am not new to dabbling in electronics, I've built several small computers)
> > a) Should I bother looking at pre-constructed systems such as offered by
> > Xess ? Or should I just go ahead and purchase the parts ? b) where can I get
> > parts in single quantities ? I like to use parts with a moderate number of
> > I/O's available say 100. c) How do you use quad flat packs "at home" (This
> > seems to be a popular packaging method) ? Do you solder very carefully ? Is
> > there some sort of "extender boards" to allow the parts to be reused ?
> >
> > Thanx
> > Rob
>
> Delphi source code to upload a Spartan FPGA :
> ------------------------------------------------------------------------------
>
> var Xil_MWB:byte;
>
> procedure Xil_WB (B:Byte);
>
> var g : word;
>
> begin
> g:=8;
> with Form1.p do while g<>0 do
> begin
> dec (g);
> port[LPTPort_Control]:=$05; { CCLK = 0 }
> if b and $80 <> Xil_MWB then
> begin
> inc (Xil_MWB,$80);
> if Xil_MWB=0 then port[LPTPort]:=$FE else port[LPTPort]:=$FF ;
> end;
> inc (b,b);
> port[LPTPort_Control]:=$04; { CCLK = 1 }
> end;
> end;
>
> Function Xil_Config (FName:String):Boolean;
>
> type buf4096 = Array[0..4095] of byte;
>
> var f,state : word;
> fi:bytefile;
> by : Byte;
> buf : ^buf4096;
>
> Begin
> Result:=False;
> buf:=NIL;
> if not fileExists(FName) then
> begin
> FName:=ExtractFilePath(application.ExeName)+ExtractFileName(FName) ;
> if not fileExists(FName) then exit;
> end;
> with Form1.p do
> begin
> port[LPTPort_Control]:=$24;
> for f:=1 to 10000 do __dummyfunc; { Delay so that the pulse is long enough }
> port[LPTPort_Control]:=$20; { Pulses "PROGRAM" (INIT) pin low }
> for f:=1 to 10000 do __dummyfunc; { Delay so that the pulse is long enough }
> port[LPTPort_Control]:=$24;
> f:=0;
> repeat
> inc (f);
> until (Port[LPTPort_Status] and $10<>0) or (f=60000); { Wait for "INIT" pin
> to go high}
> for f:=1 to 10000 do __dummyfunc;
> port[LPTPort_Control]:=$04;
> try
> buf:=NIL;
> new(buf);
> byteassign(fi,buf^,sizeof(buf),FName);
> bytereset (fi);
> state:=0;
> Result:=True;
> Xil_MWB:=$0;
> while not byteof(fi) and Result do
> begin
> byteread (fi,by);
> case state of
> 2 : xil_wb(by);
> 1 : if by and $F0 = $20 then
> begin
> xil_wb($FF);
> xil_wb(by);
> state :=2;
> end
> else
> state:=0;
> 0 : if by=$FF then state:=1;
> end;
> Result := (Port[LPTPort_Status] and $10<>0);
> Result:= True;
> end;
> finally
> if buf<>NIL then dispose(buf);
> byteclose(fi);
> end;
> end;
> End;
Article: 22266
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Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit
Jurjen,
Maybe try to write your Bid. Buffer in VHDL like:
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
ENTITY TBuff IS
PORT(
A_out : IN std_ulogic; -- or vector
A_oe : IN std_ulogic;
A_in : OUT std_ulogic; -- or vector
A_io : INOUT std_logic; -- or vector -- std_logic only
);
END TBuff ;
--
-- |-----------------< A_oe
-- |/|
-- / |
-- A_io <>---|----< |---------------< A_out
-- | \ |
-- | \|
-- |-----------------------> A_in
--
ARCHITECTURE bhv OF TBuff IS
BEGIN
A_io <= A_out WHEN (A_oe = '1') ELSE 'Z'; -- ELSE (OTHERS => 'Z');
A_in <= A_io;
END bhv;
Work very fine. I used this in many designs.
But be careful with A_io :
A_io must be std_logic (std_logic_vector or unsigned) and not std_ulogic or
std_ulogic_vector
Have a nice day!
Laurent
Maurice a écrit :
> Hi,
>
> I'm currently using the Foundation software (2.1i), and designing a
> schematic with one top-level and several sub-levels (which use VHDL and
> FSM's) for the Xilinx FPGA XCS30XL. The FPGA has to communicate with a
> processor. I'v tried to design a bidirectional bus (databus) by using the
> LogiBLOX module Inputs/Outputs. I've made a bidirectional buffer. One side
> of the buffer is connected to the output-pads and the other side split up in
> DIN and DOUT. These buses go to several sublevels. The DIN-bus will
> internally be clocked into DFF's(when selected). From several sub-levels the
> DOUT-bus will seperatly be activated when tristate-buffer is enabled. So the
> DOUT-bus is buffered twice, first in a sublevel using tristate-buffers and
> secondly at the toplevel using normal buffers! But when I trie to implement
> the schematic I always get an error-message that this twice buffering isn't
> allowed! Why? Has anyone a suggestion how to make a bidirectional bus, which
> is connected to several sublevels?
>
> Kind regards,
>
> Jurjen Boss
> Mirbachstraat 19
> 6471 CW KERKRADE
> Tel.: 045 - 5670098
> Email: jboss@wxs.nl
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Jurjen,
<p>Maybe try to write your Bid. Buffer in VHDL like:<font face="Courier New,Courier"><font size=-1></font></font>
<p><font face="Courier New,Courier"><font size=-1>LIBRARY ieee ;</font></font>
<br><font face="Courier New,Courier"><font size=-1>USE ieee.std_logic_1164.all;</font></font><font face="Courier New,Courier"><font size=-1></font></font>
<p><font face="Courier New,Courier"><font size=-1>ENTITY TBuff IS</font></font>
<br><font face="Courier New,Courier"><font size=-1> PORT(</font></font>
<br><font face="Courier New,Courier"><font size=-1>
A_out : IN std_ulogic; -- or vector</font></font>
<br><font face="Courier New,Courier"><font size=-1>
A_oe : IN std_ulogic;</font></font>
<br><font face="Courier New,Courier"><font size=-1>
A_in : OUT std_ulogic; -- or vector</font></font>
<br><font face="Courier New,Courier"><font size=-1>
A_io : INOUT std_logic; -- or vector -- std_logic only</font></font>
<br><font face="Courier New,Courier"><font size=-1> );</font></font><font face="Courier New,Courier"><font size=-1></font></font>
<p><font face="Courier New,Courier"><font size=-1>END TBuff ;</font></font><font face="Courier New,Courier"><font size=-1></font></font>
<p><font face="Courier New,Courier"><font size=-1>--</font></font>
<br><font face="Courier New,Courier"><font size=-1>--
|-----------------< A_oe</font></font>
<br><font face="Courier New,Courier"><font size=-1>--
|/|</font></font>
<br><font face="Courier New,Courier"><font size=-1>--
/ |</font></font>
<br><font face="Courier New,Courier"><font size=-1>-- A_io <>---|----<
|---------------< A_out</font></font>
<br><font face="Courier New,Courier"><font size=-1>--
| \ |</font></font>
<br><font face="Courier New,Courier"><font size=-1>--
| \|</font></font>
<br><font face="Courier New,Courier"><font size=-1>--
|-----------------------> A_in</font></font>
<br><font face="Courier New,Courier"><font size=-1>--</font></font>
<br><font face="Courier New,Courier"><font size=-1>ARCHITECTURE bhv OF
TBuff IS</font></font>
<br><font face="Courier New,Courier"><font size=-1>BEGIN</font></font>
<br><font face="Courier New,Courier"><font size=-1> A_io <= A_out
WHEN (A_oe = '1') ELSE 'Z'; -- ELSE (OTHERS => 'Z');</font></font>
<br><font face="Courier New,Courier"><font size=-1> A_in <= A_io;</font></font>
<br><font face="Courier New,Courier"><font size=-1>END bhv;</font></font>
<p>Work very fine. I used this in many designs.
<br>But be careful with A_io :
<br>A_io must be std_logic (std_logic_vector or unsigned) and not std_ulogic
or std_ulogic_vector
<p>Have a nice day!
<br>Laurent
<p>Maurice a écrit :
<blockquote TYPE=CITE>Hi,
<p>I'm currently using the Foundation software (2.1i), and designing a
<br>schematic with one top-level and several sub-levels (which use VHDL
and
<br>FSM's) for the Xilinx FPGA XCS30XL. The FPGA has to communicate with
a
<br>processor. I'v tried to design a bidirectional bus (databus) by using
the
<br>LogiBLOX module Inputs/Outputs. I've made a bidirectional buffer. One
side
<br>of the buffer is connected to the output-pads and the other side split
up in
<br>DIN and DOUT. These buses go to several sublevels. The DIN-bus will
<br>internally be clocked into DFF's(when selected). From several sub-levels
the
<br>DOUT-bus will seperatly be activated when tristate-buffer is enabled.
So the
<br>DOUT-bus is buffered twice, first in a sublevel using tristate-buffers
and
<br>secondly at the toplevel using normal buffers! But when I trie to implement
<br>the schematic I always get an error-message that this twice buffering
isn't
<br>allowed! Why? Has anyone a suggestion how to make a bidirectional bus,
which
<br>is connected to several sublevels?
<p>Kind regards,
<p>Jurjen Boss
<br>Mirbachstraat 19
<br>6471 CW KERKRADE
<br>Tel.: 045 - 5670098
<br>Email: jboss@wxs.nl</blockquote>
</html>
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Article: 22267How about this as a mechanism: o The FPGA is paired up with a small Flash CPLD. o Both the FPGA & the CPLD implement the same algorithm that performs some mangling/encryption on a shortish bits stream 50-100 bits. o The algorithm is configurable so that it is unique for each FPGA/CPLD pair. o Once the FPGA has loaded up it generates a random number which it both sends to the CPLD & encrypts itself. o The CPLD encrypts the same random number and sends the result back to the FPGA. o Unless the internal & external encrypted values are the same the FPGA remains in reset. This then reduces the problem to 3 things: (1) Generating a random number in a way that is completely unrelated to the FPGA configuration. (2) Finding an algorithm that can be configured for the FPGA by changing the definitions of some ROMs so that different bit streams can be generated by changing some ``init'' statements & not by rebuilding the whole device. Of course the positions of these bits could be detected by comparing a few bit streams so some configuration ``noise'' would have to be introduced. (3) Protecting the CPLD from attack. I think that (1) is the most difficult. Maybe this is the thing that the FPGA vendors could add to their parts.Article: 22268
Look at the tutorial files on www.freecore.com In article <2063ed28.2d0ad971@usw-ex0102-016.remarq.com>, erica <ericaNOerSPAM@remarq.com.invalid> writes >I am taking a class in computer organinzation and design. We >can use XLINX or Altera. I chose to user Altera MAX PLUS II. I >need a good web source on how to create modules. Can you help >me please? > >Thanks, > >Erica > >* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * >The fastest and easiest way to search and participate in Usenet - Free! > -- Steve DeweyArticle: 22269
If you do not have a separate logic signal you can use that gives the direction you want the signals to flow, i.e. left to right or right to left, then I don't think that you want to do is possible. In article <390CC141.5BD5D6AC@home.com>, Russ Magee <rmagee@home.com> writes >Hi there, > >We're having trouble defining a bi-directional pass-through in the >MAX+Plus II (8.1) schematic editor. here's what we want: > > ENABLE---+ > logic | > | > +--|>--+ > | | | ><====>-------------+ | +-----------------<====> > | | | > +--<|--+ > >We just want the pins to function as bi-directional, open-collector pass >throughs UNLESS our internal logic decides to suppress the connection. > >We can't seem to find a valid way to represent this in the schematic, as >hooking two bidir pins to each other (as above) has so far given us only >"Error: Node missing source:" messages. > >What is the simplest way to implement this? > >Thanks in advance, >-Russ Magee -- Steve DeweyArticle: 22270
All, We are programming multiple FPGAs with the same configuration on mulitple boards through a backplane. Because of many reasons, we are not going to tie all the INIT pins back to the PROMs, but just one. We are going to delay the INIT signal to the PROM to ensure that all of the FPGAs are ready to program. The problem is we don't know how long to delay it. So, if you had 1000 FPGAs (All Virtex E) and they all went through Vcc threshold at the same time, what would be the time delta between the first FPGA INIT signal going high and the last. We really only need the order. Right now we have a delay of 100ms built in which we believe is way more than enough....any thoughts. Yes, I know this is unconventional, but so are most things we do around here. TomArticle: 22271
Hi, I checked out www.freecore.com and I really like the site! Thanks. I tried searching on Altera's website last night...and it wasn't specific enough for what I needed. Maybe I will try again. I also need to understand how to use Altera to create a module. What the process is .... Thanks for your help! * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 22272
Dan wrote: > I design Xilinx FPGA based circuit boards. > > Some of my customers in the past have copied and manufactured my boards to > avoid buying them from me. > > How can I design my circuit boards to vastly reduce the chances of them > being copied. The main problem is the Xilinx bitstream is easy to copy. If you can possibly use XC9500 series parts, they can be made quite hard to copy. With a little ingenuity, you might also be able to add some circuitry that will complicate the job of deducing the internal logic, since there is no bitstream to read with these parts. You should also copyright the bitstream, and sue the infringers. And, of course, never do work for these companies again, and see if you can get in touch with other independant consultants and tell them what this company did to you. I wish Xilinx made their FPGAs available with an EEPROM technology like the XC9500s. JonArticle: 22273
Greg Neff wrote: > In article <8epfc4$4n3$1@nnrp1.deja.com>, > csjacobs@my-deja.com wrote: > > Why couldn't the FPGA companies but some flash rom internal to the > fpga > > that can be written but never read...then just burn it once at the > > factory and you are done...and since it's flash, you still have the > > reprogramability option. > > > > Craig Jacobs > (snip) > > Now that sounds like a helluva good idea. Flash instead of SRAM. It > would be nice to hear from Xilinx about this idea... Groan! I just asked the local Xilinx rep two days ago about this! No plans! Period! Apparently, the main reason is the semi process for flash is not good for fast logic. The SRAM process is also good for fast logic. Now, I didn't think to ask about a two-chip solution. A flash serial prom with appropriate logic for a write protect bit, so it could be erased, but not read, would be the perfect solution. If the data stream from the prom to the configure input of the FPGA was just a wire bond, only the most sophisticated outfits could intercept this signal without destroying a lot of chips first. Putting the two chips in one package would really do it! PS: Anyone want to start a company based on this idea? JonArticle: 22274
There's also the question as to whether the die will fit in the small package. Might require an FPGA with less resources. Rickman wrote: > Paul Walker wrote: > > > > In article <390D80B8.FF675C7F@egr.msu.edu>, Theron Hicks > > <hicksthe@egr.msu.edu> writes > > >I personally would love to see some 64 PQFP parts. > > >> Or I could use larger parts in the 100 PQFP package. But it would appear > > >> that I am alone in that need. > > > > > >NO, you are not. I agree whole heartedly. > > > > Hear! Hear! > > > > With interfaces going serial, like IEEE 1355, which uses less logic per > > 100MBaud port than a 16550 UART, the small devices in small packages > > would be wonderful. > > > > Paul > > Even if there is some significant demand, there is not a lot of profit > in the smaller chips in smaller packages at smaller prices. It is a > little like the guy selling apples during the depression for $10,000. > When a potential customer criticized his pricing and asked how many > apples thought he could he sell at that price, the man replied, "I only > have to sell one!" > > The FPGA companies don't want to have to make their profit selling > apples at the market rate when they can be selling golden apples at much > higher prices and profits. Remember how much it costs to run a fab! > > My problem is more of a board space issue. I need several FPGAs on the > board to each control a separate IO module. Because the module can be > any one of N different types, the FPGA has to be loadable with the > corresponding design for that module. This makes it hard to combine > several module interfaces into one FPGA. So I only need about 45 IOs > which I might be able to get in a 64 pin package if they made it. A 64 > pin TQFP is a very small animal and would be much easier to route than > the 100 pin TQFP I have to use now. > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- P.S. Please note the new email address and website url -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com
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