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Hi there, does anybody have performance measurements of the 64/66 PCI LogiCORE? What do you think about the internal interface? Thanks Patrick -- Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) University of Mannheim - Dep. of Computer Architecture 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 22226
Theron Hicks <hicksthe@egr.msu.edu> wrote: : Ray Andraka wrote: :> The XCV50E-6CS144C is $33.25 in single quantities on Avnet. Seems this is :> preety close to what you want, no? :> : Close, but not quite close enough. I need something I can hand solder for : prototype and small production runs. I prefer a 84 pin plcc but if I were : desperate I might try a VQFP or even a TQFP type package. Unless you have a : suggestion for handling a ball chip package I am afraid I will have to stick : with what I have. Pin Pitch > 0.5 mm is preferred! Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 22227
I am using Foundation 2.1i SP4. The EDIF file generated by Foundation for a hierarchical design does not contain the implementation of the hierarchy sub-components, rather it contains just the I/Os. The implementation of these componenets is taken from other files (*.xnf I think). How can I force Foundation to generate an a stand alone EDIF file (i.e. with all the sub-components implementations in one file). I remember that Foundation 1.5i was doing that. What should I do?? Cheers.Article: 22228
The ATM man wrote: > First, If anybody is offended that I put this out here, let > me know and it will cease. Second, I realize that there are > a number of great VHDL and ASIC people out there. Some > might be looking for new positions and some not. I know you > do not like me calling you at work, and I can understand > that. What would you suggest is the best way to speak with > you about new positions I have just received? > > * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is Beautiful I'm not offended because I use Verilog mostly!! Utku -- I feel better than James Brown.Article: 22229
What is the recommended way to start up the FPGA after configuration to a known state? My flops are currently synchronous reset only, so I wasn't using GSR. I thought maybe I could use the DONE line connected to an I/O? Or is it just better to make all my flops asynchronous reset so I can use GSR? BTW, my flops as sync reset because that is how they are implemented on the asic I am eventually going to target. -- Ed Richter ed@earth.wustl.edu Washington UniversityArticle: 22230
One solution used I've heard of is that a modem company configured the FPGA on the board which had a lithium backup cell so the chip's SRAM configuration wouldn't need reloading. The boards were then shipped with *no* configuration device. If the chip was removed to analyze the board traces, it promptly forgot its programming, reducing the board to junk. And with the security bit set in the FPGA, it's programming couldn't be read. Of course, this creates a long term time bomb that when the backup battery fails (and it will), the product does too. But I thought you might find the concept of interest. Jim Horn WB9SYN/6Article: 22231
Yes, but if the range is not 2^n or 2^n -1 then the logic is more complicated. One method is to discard out of range samples, but this requires a synchronous fifo and generating samples faster than you use them. Jamil Khatib wrote: > Hi, > Is there any simple method to generate random numbers "integers not > bits" that are constrained to a specific range? > > Thanks in advance > > Jamil Khatib -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 22232
Are you currently looking? * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is BeautifulArticle: 22233
How about a PQ240 package. More pins than you wanted, but not impossible to hand solder. I think that was about $36 on Avnet. Another option is to go to a contract assembly thta specializes in prototypes (small runs). Theron Hicks wrote: > Ray Andraka wrote: > > > The XCV50E-6CS144C is $33.25 in single quantities on Avnet. Seems this is > > preety close to what you want, no? > > > > Close, but not quite close enough. I need something I can hand solder for > prototype and small production runs. I prefer a 84 pin plcc but if I were > desperate I might try a VQFP or even a TQFP type package. Unless you have a > suggestion for handling a ball chip package I am afraid I will have to stick > with what I have. > > Thanks for the suggestion anyway. > > > > > Theron Hicks wrote: > > > > > Rickman wrote: > > > > > > > Peter wrote: > > > > > > ... I would love a small Virtex-E series part (fast, with LVPECL I/O > > > capability). > > > For that part I would probably be willing to pay as much as $30 or more. > > > (If it were fast enough.) > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 22234
In article <390f0ef3@news1.svn.net>, James Horn <jimhorn@svn.net> wrote: > One solution used I've heard of is that a modem company configured the > FPGA on the board which had a lithium backup cell so the chip's SRAM > configuration wouldn't need reloading. The boards were then shipped with > *no* configuration device. If the chip was removed to analyze the board > traces, it promptly forgot its programming, reducing the board to junk. > And with the security bit set in the FPGA, it's programming couldn't be > read. > > Of course, this creates a long term time bomb that when the backup battery > fails (and it will), the product does too. But I thought you might find > the concept of interest. > > Jim Horn WB9SYN/6 > That reminds me... We used a similar approach to protecting microprocessor code (in battery protected SRAM), on a project we did almost ten years ago. The production test fixture included a bootloader and the production code in EPROM, so the microcontroller could load its own SRAM. The product never made it to full production, so I can't offer any anecdotal information regarding reliability in the field. We used a pair of lithium coin cells for redundancy. Some lithiums (Tadiran, for example) have very long shelf lives, in the order to ten to twenty years. One thing to watch out for is that FPGAs will likely have significantly higher retention currents than low power SRAMs. This approach might be viable for systems that are normally always on, but may be problematic for systems that are powered on for a smaller percentage of the time. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22235
This is a multi-part message in MIME format.
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If you have preset or reset flops in your design, then all preset flops
will be logic '1' on powerup, reset flops will be '0' on powerup. If you
are doing a HDL based design, you can infer these flops by using the same
reset line for all flops in such a manner
if (clk'event and clk='1') then
if (reset = '1')
preset <= '1';
rset <= '0';
else
preset <= somelogic;
reset <= otherlogic;
end if;
end if;
If you have more than one reset line in your code you should use the
rocbuf component to allow for GSR. See the Synthesis and Simulation guide
for this in the doc scan utility at support.xilinx.com (software manuals)
If you are using schematic, just place the right flops in your design.
You can always use init attributes in the constraint file as well:
http://toolbox.xilinx.com/docsan/2_1i/data/common/lib/lib12_6.htm#X32162
Best regards,
Chris Dunlap
Xilinx Applications
ed@earth.wustl.edu wrote:
> What is the recommended way to start up the FPGA after configuration
> to a known state? My flops are currently synchronous reset only, so I
> wasn't using GSR. I thought maybe I could use the DONE line connected
> to an I/O? Or is it just better to make all my flops asynchronous
> reset so I can use GSR? BTW, my flops as sync reset because that is
> how they are implemented on the asic I am eventually going to target.
>
> --
> Ed Richter
> ed@earth.wustl.edu
> Washington University
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Article: 22236
In article <390D80B8.FF675C7F@egr.msu.edu>, Theron Hicks
<hicksthe@egr.msu.edu> writes
>I personally would love to see some 64 PQFP parts.
>> Or I could use larger parts in the 100 PQFP package. But it would appear
>> that I am alone in that need.
>
>NO, you are not. I agree whole heartedly.
Hear! Hear!
With interfaces going serial, like IEEE 1355, which uses less logic per
100MBaud port than a 16550 UART, the small devices in small packages
would be wonderful.
Paul
--
Paul Walker Chair of the 1355 Association
www.1355.org
4Links:
Boards, chips, IP and consultancy ... for links
phone/fax
paul@4Links.co.uk P O Box 816, Two Mile Ash +44 1908
http://www.4Links.co.uk Milton Keynes MK8 8NS, UK 566253
Article: 22237
Daryl Bradley wrote:
> I may stand to be corrected, so tell me if I'm wrong as I'll be interested
> to know the solution, but as far as I am aware from looking through the
> xilinx support, the parallel cable (parallel cable iii dcl5?) does not
> support readback adn so you can't debug with this cable.
That's the situation as I understand it as well, at least for Virtex:
(1) The JTAG programmer doesn't support readback or partial re-config.
(2) The hardware debugger does but only from the 8bit SelectMap port with a
$500 MultiLinx cable.
[Caveat: AFIK there's only been one post to this group who's tried this
and he didn't succeed].
Even the Java based stuff you can get from the Xilinx Web only goes as far as
the JTAG programmer although its an obvious place to start if anybody wanted
to use the various apps notes to write a JTAG readback funtion.
Article: 22238HI Longshot, but I am consulting for one of the major US FPGA companies. They are seeking a High Level Design consultant to work with their European customers. Based from the UK, they want someone to be the synthesis expert advising customers on design flow issues. Excellent salary, stock, car and huge bonus. Any PCI experience would be of interest. Must know VHDL and or Verilog to a very high standard. I work purely in the semiconductor industry. You can mail me at the company I work for - details below. Thanks Simon simon@microscape.co.uk http://www.microscape.couk Christian Mautner <at@utanet.cmautner> wrote in message news:7wpur6xejc.fsf@NB8845UX.frequentis.frq... > antera@mweb.co.za (Anton Erasmus) writes: > > > Hi, > > > > I Have done some simple EPLD designs in AHDL, but I want to start to > > use Verilog and/or VHDL. Unfortuanetly the Free License version of > > Alteras Max+Plus II does not support Verilog and VHDL. Is there a free > > Compiler which I can use to test Compile simple Verilog and maybe > > simulate ? > > Have you been to www.altera.com recently? If I understand them > correctly, they will give away FPGA express and/or another synthesis > tool (in a special OEM version) for free (starting in some weeks). > > chm. > > -- > cmautner@ - Christian Mautner > utanet.at - Vienna/Austria/EuropeArticle: 22239
Hi !
I was in the same situation not too long ago.
I bought 10000 gates Spartan devices in PLCC84 package (exact number is XCS10-3PC84C)
on the net from Insight Electronics. I paid 18.10 US for them (and 10.00 for XCS05 (5K gates))
in 3 pcs qty (min order is 50 $ and there is no shiping charges to US (15$ to Canada)).
here is a list of distributors in N. America :
http://www.xilinx.com/company/sales/na_disti.htm
Uploading the bit stream to the device is easy, either using the Xilinx parallel cable or
designing your own.
I choosed the second option, and all it take is to connect the following pins :
- ground & VCC (even works stray powered by the parallel interface signals)
- PROGRAM pin (Pin 55) to pin 16 (INIT) of the parallel interface with a 470pF
capacitor to ground (to prevent noise from other signals in the parallel cable
to reset the device)
- DIN (pin 71) to pin 2 (D0) of the parallel interface
- CCLK (pin 73) to pin 1 (STROBE) of the parallel interface
You'll find the source code at the end of this post.
If there is interrest, I can make the loader executable (Windows) availiable as freeware.
Next step was to add a LED and a resistor to pin P3, start a new project in Xilinx
Foundation software, go to the schematic editor, drop an "Osc4", a "obuf" and a
"opad" components, connect "F15" output of Osc4 to Obuf and obuf to Opad.
Then double click on the Opad, and in the symbol properties screen, add the
following parameter :
Name : LOC
description : P3
Compile, upload to the device, and when your LED starts blinking, you've got it
and sky is the limit ...
Unlike processor based design that are somewhat painful to kickstart, using
Xilinx chips was really easy and nearly all worked well on the first try.
hope this helps,
Eric.
PS : Xilinx devices usage is somewhat addictive <G>
----------------------------------------------------------------------------------------------
"R. T. Finch" wrote:
> Hi, I'm new to fpga designs. I'd like to experiment with some (at home) (I
> am not new to dabbling in electronics, I've built several small computers)
> a) Should I bother looking at pre-constructed systems such as offered by
> Xess ? Or should I just go ahead and purchase the parts ? b) where can I get
> parts in single quantities ? I like to use parts with a moderate number of
> I/O's available say 100. c) How do you use quad flat packs "at home" (This
> seems to be a popular packaging method) ? Do you solder very carefully ? Is
> there some sort of "extender boards" to allow the parts to be reused ?
>
> Thanx
> Rob
Delphi source code to upload a Spartan FPGA :
------------------------------------------------------------------------------
var Xil_MWB:byte;
procedure Xil_WB (B:Byte);
var g : word;
begin
g:=8;
with Form1.p do while g<>0 do
begin
dec (g);
port[LPTPort_Control]:=$05; { CCLK = 0 }
if b and $80 <> Xil_MWB then
begin
inc (Xil_MWB,$80);
if Xil_MWB=0 then port[LPTPort]:=$FE else port[LPTPort]:=$FF ;
end;
inc (b,b);
port[LPTPort_Control]:=$04; { CCLK = 1 }
end;
end;
Function Xil_Config (FName:String):Boolean;
type buf4096 = Array[0..4095] of byte;
var f,state : word;
fi:bytefile;
by : Byte;
buf : ^buf4096;
Begin
Result:=False;
buf:=NIL;
if not fileExists(FName) then
begin
FName:=ExtractFilePath(application.ExeName)+ExtractFileName(FName) ;
if not fileExists(FName) then exit;
end;
with Form1.p do
begin
port[LPTPort_Control]:=$24;
for f:=1 to 10000 do __dummyfunc; { Delay so that the pulse is long enough }
port[LPTPort_Control]:=$20; { Pulses "PROGRAM" (INIT) pin low }
for f:=1 to 10000 do __dummyfunc; { Delay so that the pulse is long enough }
port[LPTPort_Control]:=$24;
f:=0;
repeat
inc (f);
until (Port[LPTPort_Status] and $10<>0) or (f=60000); { Wait for "INIT" pin to go high}
for f:=1 to 10000 do __dummyfunc;
port[LPTPort_Control]:=$04;
try
buf:=NIL;
new(buf);
byteassign(fi,buf^,sizeof(buf),FName);
bytereset (fi);
state:=0;
Result:=True;
Xil_MWB:=$0;
while not byteof(fi) and Result do
begin
byteread (fi,by);
case state of
2 : xil_wb(by);
1 : if by and $F0 = $20 then
begin
xil_wb($FF);
xil_wb(by);
state :=2;
end
else
state:=0;
0 : if by=$FF then state:=1;
end;
Result := (Port[LPTPort_Status] and $10<>0);
Result:= True;
end;
finally
if buf<>NIL then dispose(buf);
byteclose(fi);
end;
end;
End;
Article: 22240
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Article: 22241Hi Folks, I have a basic question to ask: I know that 2-D DCT does not take the phase information of an image into account. FFT, however, does. Where is DCT used, and where is FFT used? Am I true in thinking that Phase in Freq. domain means delay in Time domain. So DCT works on stil images, whereas FFT works on both stil and moving images. DCT is simpler to compute and thus more used in still image compression... Is that true?? Any comment is much appraciated! Cheers.Article: 22242
Can only be done with experience and the proper tip. Do not try it without guidance from an expert and without the right tip. DanArticle: 22243
Greg Neff wrote: > > One thing to watch out for is that FPGAs will likely have significantly > higher retention currents than low power SRAMs. > > This approach might be viable for systems that are normally always on, > but may be problematic for systems that are powered on for a smaller > percentage of the time. You also had better be really, really sure that external power transients can't cause the FPGA to dump its memory, or trigger its reset circuit. I wouldn't feel very good about using external power at all, but you will still face ground spike problems. In addition, you face potential problems with having the FPGA outputs being powered, while the rest of the circuit is not powered. This could damage the other circuits. Muddy > > -- > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 22244
In article <390F5925.CC48CA69@raytheon.com>, Robert Posey <muddy@raytheon.com> wrote: > > You also had better be really, really sure that external power transients can't > cause the FPGA to dump its memory, or trigger its reset circuit. I wouldn't > feel very good about using external power at all, but you will still face > ground spike problems. Correct. With our microprocessor circuit, the code SRAM was write protected unless it was connected to the production test fixture. Also, there is no reset and/or reconfiguration circuit to worry about in an SRAM. > In addition, you face potential problems with having > the FPGA outputs being powered, while the rest of the circuit is not powered. > This could damage the other circuits. Again correct. You could use a "power no good" signal to tri-state all the FPGA outputs. I can see applications where this technique would be useful, outside of mainstream production. For example, if a small company is demonstrating new technology to a potential licensee (or anyone else for that matter), then proof-of-concept hardware could be built like this, to prevent IP rip-off. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22245
Lattice Semiconductor and Centaur North will be hosting a technical seminar and workshop on the new and exciting ispPAC Programmable Analog product line, and you have been invited! Seminar Outline ------------------- What programmable Analog can do for you, examples Building blocks of PAC Technology Discussion of ispPAC10/20/80: specifications, features, circuit examples Slashing design time with PAC-Designer S/W: editing, simulating, programming, macros Selected application discussions (anti-aliasing filters, signal conditioning, monitoring) Lab (based on an audio demo) There will be giveaways for attending: Lattice HDL Design Software - $495 value - absolutely free! Plus drawings for the following giveaways: ispPAC Development Systems San Francisco Giants tickets - see a game at the new Pac Bell Park! Several seminar times and dates are available, as follows: Monday, May 8th: 1:30pm - 4:30pm Tuesday, May 9th: 9:00am - noon Tuesday, May 9th: 1:30pm - 4:30pm Wednesday, May 10th: 1:30pm - 4:30pm The seminars will be held at the following location: Lattice Semiconductor, 995 Stewart Drive, Sunnyvale, CA To sign up, please call: Centaur North: (408) 328-9260, or respond to this email. Some additional information is attached. See you there!Article: 22246
Rickman <spamgoeshere4@yahoo.com> writes: > The process of copying a "one-wire" part is not as simple as you might > think. Any CPLD will use a much larger package and require a clock > input. Yes. On the other hand, a small 8-pin AVR or PIC chip would not occupy much more space, has internal clock and running at a few MHz clock, it is quick enough to play the one-wire protocol. Zoltan -- +------------------------------------------------------------------+ | ** To reach me write to zoltan in the domain of bendor com au ** | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 22247
I am taking a class in computer organinzation and design. We can use XLINX or Altera. I chose to user Altera MAX PLUS II. I need a good web source on how to create modules. Can you help me please? Thanks, Erica * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 22248
In article <lsIP4.105451$2D6.2668300@news20.bellglobal.com>, "Dan" <daniel.deconinck@sympatico.ca> wrote: > Can only be done with experience and the proper tip. > > Do not try it without guidance from an expert and without the right tip. > > Dan I don't suggest that we squabble about this all day but... Just use PLENTY of flux, almost no solder to begin with and a very hot iron. Almost any tip will do and much bigger than you would expect, ideally with a flat edge. The knack is to have a solder blob which is big enought to short a couple of pins, the flux does the right things to surface tension and the solder would rather attach to the iron than the pins and just draw the solder blob along the pins, just the right amount will be left behind at each pin. If the blob leaves the iron and sits on the pins then add more flux untill surface tension is working for you again. When you are done, run a scalpel along the vertical part of the pins to look for dry joints, apply enough force to hear the scalpel ping off of each pin, a dry joint is obvious and at worst will nudge the pin sideways a bit but easily straightened. Think of your iron as a very small wave solder machine and you've got the idea. If you go to a show and watch a demo of a PACE machine (with its quite clever surface tension friendly tip) you will see experts do a 240PQFP in under 2 minutes, remove it with a paint stripper and put the same device down again and again. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22249
Paul Walker wrote: > > In article <390D80B8.FF675C7F@egr.msu.edu>, Theron Hicks > <hicksthe@egr.msu.edu> writes > >I personally would love to see some 64 PQFP parts. > >> Or I could use larger parts in the 100 PQFP package. But it would appear > >> that I am alone in that need. > > > >NO, you are not. I agree whole heartedly. > > Hear! Hear! > > With interfaces going serial, like IEEE 1355, which uses less logic per > 100MBaud port than a 16550 UART, the small devices in small packages > would be wonderful. > > Paul Even if there is some significant demand, there is not a lot of profit in the smaller chips in smaller packages at smaller prices. It is a little like the guy selling apples during the depression for $10,000. When a potential customer criticized his pricing and asked how many apples thought he could he sell at that price, the man replied, "I only have to sell one!" The FPGA companies don't want to have to make their profit selling apples at the market rate when they can be selling golden apples at much higher prices and profits. Remember how much it costs to run a fab! My problem is more of a board space issue. I need several FPGAs on the board to each control a separate IO module. Because the module can be any one of N different types, the FPGA has to be loadable with the corresponding design for that module. This makes it hard to combine several module interfaces into one FPGA. So I only need about 45 IOs which I might be able to get in a 64 pin package if they made it. A 64 pin TQFP is a very small animal and would be much easier to route than the 100 pin TQFP I have to use now. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com
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