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Well possible. But wouldn't it be simpler to just have one clock and put a clock enable on each part of the design, then enable and disable as necessary in the same way ? jc "Nicolas Matringe" <nicolas@dotcom.fr> wrote in message news:38D63858.2A94786B@dotcom.fr... > Hi all > I am working on a design which may be used in two products, one of which > won't need some functions of the design. I don't want to have 2 designs > (we won't make 2 ASICs). > I was wondering if it was possible to have 2 clock domains (same > frequency) with the possibility to turn one of them off to reduce power > consumption (this would be done by pulling a pin high or low for > example) > -- > Nicolas MATRINGE DotCom S.A. > Conception electronique 16 rue du Moulin des Bruyeres > Tel 00 33 1 46 67 51 11 92400 COURBEVOIE > Fax 00 33 1 46 67 51 01 FRANCEArticle: 21376
Andy Krumel wrote: > > Hi, > > I was attempting to synthesize a VHDL design for a Xilinx SpartanXL FPGA to > get some timing and usage statistics and received the following > LeonardoSpectrum error message: > > ERROR: a gnd net is driven by primitive gate(s) -- NET: GND0 DRIVING GATE: > i6_i2_i4_i2_reg_s_active_0 > optimize: view can not be optimized because of electrical problems > Using wire table: s10xl-3_avg > > I understand what the i6...s_active_0 are but what does NET: GND0 DRIVING > GATE mean and is there a method for finding/fixing such problems. > > Many thanks, > Andy I can't tell you what the cause of your problem is, but the error message is telling you that the gnd net is GND0 and the gate driving it is "i6_i2_i4_i2_reg_s_active_0". The double space between GND0 and DRIVING is a separator. I can only assume that this is caused by an internal error in LeonardoSpectrum. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 21377
Hi everyone! How I can DLL function unsing VHDL in Virtex? I would appreciate it if you show me the example source. Thank you for reading my question.Article: 21378
Have you checked the xilinx web site? There are application notes with code examples on the website for using the DLLs ÀÓÀçȯ wrote: > Hi everyone! > How I can DLL function unsing VHDL in Virtex? > I would appreciate it if you show me the example source. > Thank you for reading my question. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21379
Dave Vanden Bout (devb@xess.com) wrote:
: All our XS Boards use the parallel port for programming, including the XC9500-based boards which use JTAG. We have our low-level programming routines at http://www.xess.com/xstools-source-2_0.zip and documentation at http://www.xess.com/xstools-src-doc-2_0.pdf.
.. and for those non-MS-Windows people, an older but functional
version of those programs has been ported to Linux (a couple of times
actually). One of those copies is at
http://recycle.lbl.gov/~ldoolitt/fpga/
Porting from there to other x86 *nixes should be pretty easy.
- Larry Doolittle <LRDoolittle@lbl.gov>
Article: 21380On Mon, 20 Mar 2000 22:04:45, "MegaBolt" <MegaBolt@mbox5.singnet.com.sg> wrote: > Hi, > > Advice for beginner. > Web sites, book ref...any thing to get started in VHDL, FPGAs as a primer, I like "Essential VHDL" (sorry, don't have the ISBN, but can get it tomorrow, if you care). It is very readable and I picked up the "essentials" very quickly. A reference it is not. It is a very good introduction though. As has been noted in previous answers, you could do worse than starting out at the programmable logic jump-site. > Heard of Xilinx Foundation Series 1.5 (Student Edition) but no info at > Xilinx wed site. Not supported most likely. I bought it recently. I'm not really impressed, maybe because I was already using Synplify and Alliance 2.1i (admittadly at about 200x the price-tag). I guess if it were my money I'd go this way. However, I'd still latch onto a copy of "Essential VHDL". ---- KeithArticle: 21381
This error is usually (from my experience ) caused by bad HDL. You can try RTL viewer, if you have license, and see which net was optimised out and may be you will see, which process or component cause the error. Hope it helps, Bonio Remove_this_Bonio.lopez@gmx.ch_remove_this In article <sdde2rn7lul157@corp.supernews.com>, "Andy Krumel" <andy@krumel.com> wrote: > Hi, > > I was attempting to synthesize a VHDL design for a Xilinx SpartanXL FPGA to > get some timing and usage statistics and received the following > LeonardoSpectrum error message: > > ERROR: a gnd net is driven by primitive gate(s) -- NET: GND0 DRIVING GATE: > i6_i2_i4_i2_reg_s_active_0 > optimize: view can not be optimized because of electrical problems > Using wire table: s10xl-3_avg > > I understand what the i6...s_active_0 are but what does NET: GND0 DRIVING > GATE mean and is there a method for finding/fixing such problems. > > Many thanks, > Andy > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21382
Hi, You don't indicate which FPGA family you use. For instance in Virtex you have only 4 primary clock but you have 24 secondary and there's a answer in the Xilinx database to you this secondary clock : http://www.xilinx.com/techdocs/6198.htm If it's not the case (Spartan family) keep in mind to use either primary or secondary clock buffer (in schematic or in VHDL). <boniolopez@my-deja.com> a écrit dans le message news: 8b5mrk$k76$1@nnrp1.deja.com... > Hi all, > I'm not very new in FPGA design but I can't find the issue of following > problem: > > > WARNING:Timing:33 - Clock nets using non-dedicated resources were found > in this > design. Clock skew on these resources will not be automatically > addressed > during path analysis. To create a timing report that analyzes clock > skew for > these paths, run trce with the '-skew' option. > > > > I'm quite sure to use in my design the deducted clock resources only > (and connected to BufG or Buf GP). I think the syntheses tool can' > recognise some part in my design and form it so, that clock some FF > with the gated signal. But I cant find where. > > THE QUESTION: How I can find out where the Alliance 2.1i found the non- > dedicated resources(which signal is such clock)? > > Any help will be appreciated, > Bonio > Remove_this_Bonio.lopez@gmx.ch_remove_this > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. Reply-To: "Sherdyn" <sherdyn@yahoo.com>Article: 21383
I am using the following component instantiation in one of my design but
when it was synthesized by Synplicify and place & route by Altera MaxPlusII,
I got different type of IOs (from Altera .rpt report). Some are open-drain
and others are tristate. What are the differences between them and is there
a coding style in VHDL to specify an open-drain output port?
Please note that the code for TOP is not complete.
Sherdyn
---------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TRISTATE is
port (
A : in STD_LOGIC;
B : out STD_LOGIC;
OEN : in STD_LOGIC;
---------------------------------------------------------------------
C : inout STD_LOGIC
);
end TRISTATE;
architecture tristate_arch of TRISTATE is
begin
B <= C;
C <= A when OEN = '0' else 'Z';
end tristate_arch;
---------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY TOP IS
PORT (RESETN : in STD_LOGIC;
CLK25M : in STD_LOGIC;
TSID : inout STD_LOGIC;
TS_DATA0 : inout STD_LOGIC;
TS_DATA9 : inout STD_LOGIC;
PerData : inout STD_LOGIC_VECTOR(7 downto 0);
PerCS1N : in STD_LOGIC;
PerADDR : in STD_LOGIC_VECTOR(3 downto 0);
PerCS2N : in STD_LOGIC;
-------
------
);
END TOP;
---------------------------------------------------------------------
ARCHITECTURE STRUCTURAL OF TOP IS
component TRISTATE is
PORT(A : in STD_LOGIC;
B : out STD_LOGIC;
OEN : in STD_LOGIC;
---------------------------------------------------------------------
C : inout STD_LOGIC
);
end component;
signal ----
----
---
BEGIN
----
----
----
U1_TRI : TRISTATE
PORT MAP(A => '0',
B => DCIN_TSID,
OEN => SPI_ENBN,
C => TSID
);
U2_TRI : TRISTATE
PORT MAP(A => '0',
B => SC_D,
OEN => SPI_ENBN,
C => TS_DATA0
);
PerDATA_GEN: for I in 0 to 7 generate
U_TRI_PerDATA : TRISTATE
PORT MAP(A => PerDATA_OUT(I),
B => PerDATA_IN(I),
OEN => PerDATA_ENBN,
C => PerDATA(I)
);
end generate;
-------
-------
-------
end structural;
Article: 21384Wow, there are really other Actel users out there, Hi all, I had also a timing problem for an ACT3 (much slower than SX of course). The design was based on VHDL and was synthesized via FPGAExpress3.xx. There was a bi-directional 32 bit bus with the tri-state I/O control. The OUT enable signal was generated by a FSM (finite state machine). Due to the high fan out (32) of the enable signal, a buffer tree was synthesized. These buffer tree inserted the main delay of the bus control (relative slow gates). Solution: I duplicated the enable FF in the state machine to an enable vector (4 bit, always the same value!). At that time, FPGAExpress did not perform automatic register duplication. Now, there was no need to insert additional buffers by FPGAExpress. The enable FF’s could be placed by designer P&R near the 8 bit bus segment. The penalty of the additional FF’s was minimal because the fan out of the FSM to the FF-D input was increased from 1 to 4 (with a lot of setup time left). All changes worked fine if I took under account to keep alive the “redundant” enable vector during synthesis. There, I had to switch off the “remove duplicate register” option in the constrains editor!!! (BSW, it is not possible to enable globally the “remove duplicate register” option and only locally disable it on a lower block of the hierarchical design in FPGAExpress3.31 for Actel (ACT3,ACT2) devices.) Regards, Holger Venus DLR Institute of Space Sensor Technology rk schrieb: > Andrew batchelor wrote: > > > Dear All > > > > I am a hardware engineer down in Rochester, and I am having great > > problems fitting a design to a 42MX36. The problem is that I would like > > my design to run at 55 MHz across the full mil temp range. There is one > > section of an 8 bit bus which I cannot get to go fast enough. Has anyone > > got any ideas on how to improve the fitting performance, or how I could > > increase the speed of the system. Also does any one know what type of > > algorithm they use to place and route, say Genetic Algorithm or some > > other process for optimization? > > Of course, there are lots of ways to make things go faster. Have you > contacted the local FAE? > > Perhaps a bit more detail about the logic can help. > > Some more general things to do, some not great ideas, but when you're stuck > ... > > Bias the voltage up higher with tight regulation. > > Pick faster speed grade, if available. > > Heat sink the part better and see if you can cut the temperature range. > You'll get somewhere around 0.3%/deg C. > > Dump MX series and go with SX or SX-A. > > Are you using timing driven P&R? > > Some versions of the P&R did not give the same P&R solution each time [at > least that was my experience with some SX designs] and varied by a bunch; > try running it several times and see if your "luck" improves or if you get > the same solution each time. > > Try a different revision of the P&R software, both older and newer. > > Have you used Chipedit and try to improve the placement and help it with the > critical paths? > > With the Act 2 logic cell in the MX-series, make sure that if you have logic > between flops the last stage is combinable with the flip-flop that you've > chosen. > > Er, try Quicklogic QL3000 series. > > Look carefully at fan out loads. > > Redundant buffering of signals to cut loads if there's a bunch of fanout. > > Sometimes inserting buffers will help (don't forget the preserve property!) > if the lines are long and you wind up long tracks or runs with a bunch of > antifuses. > > Using an HDL? Try schematics! ;-) > > Anyways, just a few ideas to get started, > > Have a good evening, > > rk > > p.s. Ah, I think we're up to 6 Actel users on the newsgroup! <g>Article: 21385
Rémi ,thank you for the answer. But I write once more, there is no obvious clock signal that not use global or secondary clock buffer (I have 2 bufG and 2 bufGP in my Virtex device and they are really used as the Alliance 2.1i report ). So I must find out which signal the Alliance mean under undedicated clock! The question: How can I find out which signal mean Alliance software under such clock. Can any tool from alliance set say me: "The signal A on the place B is a clock, but not use clock buffer" or is it any indirect way to find out which signal is it. Regards, Bonio In article <8b7brf$gkv$1@minus.oleane.net>, "Rémi SEGLIE" <rseglie@celogic.com> wrote: > Hi, > > You don't indicate which FPGA family you use. For instance in Virtex you > have only 4 primary clock but you have 24 secondary and there's a > answer in the Xilinx database to you this secondary clock : > http://www.xilinx.com/techdocs/6198.htm > > If it's not the case (Spartan family) keep in mind to use either primary or > secondary clock buffer (in schematic or in VHDL). > > <boniolopez@my-deja.com> a écrit dans le message news: > 8b5mrk$k76$1@nnrp1.deja.com... > > Hi all, > > I'm not very new in FPGA design but I can't find the issue of following > > problem: > > > > > > WARNING:Timing:33 - Clock nets using non-dedicated resources were found > > in this > > design. Clock skew on these resources will not be automatically > > addressed > > during path analysis. To create a timing report that analyzes clock > > skew for > > these paths, run trce with the '-skew' option. > > > > > > > > I'm quite sure to use in my design the deducted clock resources only > > (and connected to BufG or Buf GP). I think the syntheses tool can' > > recognise some part in my design and form it so, that clock some FF > > with the gated signal. But I cant find where. > > > > THE QUESTION: How I can find out where the Alliance 2.1i found the non- > > dedicated resources(which signal is such clock)? > > > > Any help will be appreciated, > > Bonio > > Remove_this_Bonio.lopez@gmx.ch_remove_this > > > > > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21386
Hi, MegaBolt wrote: > Hi, > > Advice for beginner. > Web sites, book ref...any thing to get started in VHDL, FPGAs > You may also take a look at the VHDL FAQ (http://www.vhdl.org/comp.lang.vhdl/). Part 2 includes a list of recommended books on VHDL as well as some links to free documents. -- EdwinArticle: 21387
Hi Bonio, What about using the Design Editor and highliting all your clock nets (you cannot have that many) one by one? It isi easy to see which ones do not use a clock buffer. Reagrds, Catalin boniolopez@my-deja.com wrote: > Rémi ,thank you for the answer. > But I write once more, there is no obvious clock signal that not use > global or secondary clock buffer (I have 2 bufG and 2 bufGP in my > Virtex device and they are really used as the Alliance 2.1i report ). > So I must find out which signal the Alliance mean under undedicated > clock! > > The question: How can I find out which signal mean Alliance software > under such clock. > Can any tool from alliance set say me: "The signal A on the place B is > a clock, but not use clock buffer" or is it any indirect way to find > out which signal is it. > Regards, > Bonio >Article: 21388
You could do this, but you would think that the software would tell you rather than you having to go hunting. Sometimes you get clocks on nets that you did not expect. However the original post does suggest that you run the timing analyzer. "To create a timing report that analyzes clock skew for these paths, run trce with the '-skew' option." That may list the clock nets including any inadvertant ones. a@z.com wrote: > > Hi Bonio, > > What about using the Design Editor and highliting all your clock nets (you > cannot have that many) one by one? It isi easy to see which ones do not use > a clock buffer. > > Reagrds, > > Catalin > > boniolopez@my-deja.com wrote: > > > Rémi ,thank you for the answer. > > But I write once more, there is no obvious clock signal that not use > > global or secondary clock buffer (I have 2 bufG and 2 bufGP in my > > Virtex device and they are really used as the Alliance 2.1i report ). > > So I must find out which signal the Alliance mean under undedicated > > clock! > > > > The question: How can I find out which signal mean Alliance software > > under such clock. > > Can any tool from alliance set say me: "The signal A on the place B is > > a clock, but not use clock buffer" or is it any indirect way to find > > out which signal is it. > > Regards, > > Bonio > > -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 21389
Hi Catalin, The problem is that all my clock nets USE the global buffers, but I suppose any other clock nets made by syntheses or Alliance and I can't find out where. The question: How can I hunt such nets? In article <38D776B5.98988C7C@z.com>, a@z.com wrote: > Hi Bonio, > > What about using the Design Editor and highliting all your clock nets (you > cannot have that many) one by one? It isi easy to see which ones do not use > a clock buffer. > > Reagrds, > > Catalin > > boniolopez@my-deja.com wrote: > > > Rémi ,thank you for the answer. > > But I write once more, there is no obvious clock signal that not use > > global or secondary clock buffer (I have 2 bufG and 2 bufGP in my > > Virtex device and they are really used as the Alliance 2.1i report ). > > So I must find out which signal the Alliance mean under undedicated > > clock! > > > > The question: How can I find out which signal mean Alliance software > > under such clock. > > Can any tool from alliance set say me: "The signal A on the place B is > > a clock, but not use clock buffer" or is it any indirect way to find > > out which signal is it. > > Regards, > > Bonio > > > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21390
Hi all,
now I still see all my 4 clocks using BufG or BufGp also my QUESTION IS
STILL ACTUAL.
The second question now:
Below the results trce -skew.
Why this constrain is not met if 177<250!!!!!!!!!
* TS_gpp1_dup0 = PERIOD TIMEGRP "gpp1_dup0" | 250.000ns | 177.536ns |
28
250 nS HIGH 50.000 % | |
|
------------------------------------------------------------------------
-------
Xilinx TRACE, Version C.19
Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved.
Design file: envir.ncd
Physical constraint file: envir.pcf
Device,speed: xcv800,-4 (PRELIMINARY 1.94 1999-10-25)
Report level: summary report
------------------------------------------------------------------------
--------
1622 circuit loops found and disabled.
Asterisk (*) preceding a constraint indicates it was not met.
------------------------------------------------------------------------
--------
Constraint | Requested | Actual |
Logic
| | |
Levels
------------------------------------------------------------------------
--------
NET "ix2305/IBUFG" PERIOD = 62.500 nS | 62.500ns | 23.198ns |
4
HIGH 50.000 % | |
|
------------------------------------------------------------------------
--------
NET "ix2307/IBUFG" PERIOD = 25 nS HIGH | 25.000ns | 17.895ns |
3
50.000 % | |
|
------------------------------------------------------------------------
--------
TS_ls_dup0 = PERIOD TIMEGRP "ls_dup0" 25 | 250.000ns | 110.646ns |
33
0 nS HIGH 50.000 % | |
|
------------------------------------------------------------------------
--------
* TS_gpp1_dup0 = PERIOD TIMEGRP "gpp1_dup0" | 250.000ns | 177.536ns |
28
250 nS HIGH 50.000 % | |
|
------------------------------------------------------------------------
--------
1 constraint not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock clk0
---------------+---------+---------+---------+---------+
| Src/Dest| Src/Dest| Src/Dest| Src/Dest|
Source Clock |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|
---------------+---------+---------+---------+---------+
clk0 | | | 11.593| |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk40mhz
---------------+---------+---------+---------+---------+
| Src/Dest| Src/Dest| Src/Dest| Src/Dest|
Source Clock |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|
---------------+---------+---------+---------+---------+
clk40mhz | 17.895| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 76 Score: 142293
Constraints cover 3577402745 paths, 0 nets, and 14068 connections (96.0%
coverage)
Design statistics:
Minimum period: 177.536ns (Maximum frequency: 5.633MHz)
Analysis completed Tue Mar 21 17:24:35 2000
------------------------------------------------------------------------
--------
In article <38D78BC0.F394394E@yahoo.com>,
Rickman <spamgoeshere4@yahoo.com> wrote:
> You could do this, but you would think that the software would tell
you
> rather than you having to go hunting. Sometimes you get clocks on nets
> that you did not expect.
>
> However the original post does suggest that you run the timing
analyzer.
> "To create a timing report that analyzes clock skew for these paths,
run
> trce with the '-skew' option."
>
> That may list the clock nets including any inadvertant ones.
>
> a@z.com wrote:
> >
> > Hi Bonio,
> >
> > What about using the Design Editor and highliting all your clock
nets (you
> > cannot have that many) one by one? It isi easy to see which ones do
not use
> > a clock buffer.
> >
> > Reagrds,
> >
> > Catalin
> >
> > boniolopez@my-deja.com wrote:
> >
> > > Rémi ,thank you for the answer.
> > > But I write once more, there is no obvious clock signal that not
use
> > > global or secondary clock buffer (I have 2 bufG and 2 bufGP in my
> > > Virtex device and they are really used as the Alliance 2.1i
report ).
> > > So I must find out which signal the Alliance mean under
undedicated
> > > clock!
> > >
> > > The question: How can I find out which signal mean Alliance
software
> > > under such clock.
> > > Can any tool from alliance set say me: "The signal A on the place
B is
> > > a clock, but not use clock buffer" or is it any indirect way to
find
> > > out which signal is it.
> > > Regards,
> > > Bonio
> > >
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> remove the XY to email me.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com
>
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21391
Sherdyn wrote in message <38d73877.0@news.cyberway.com.sg>...
>I am using the following component instantiation in one of my design but
>when it was synthesized by Synplicify and place & route by Altera
MaxPlusII,
>I got different type of IOs (from Altera .rpt report). Some are open-drain
>and others are tristate. What are the differences between them and is there
>a coding style in VHDL to specify an open-drain output port?
Tristate means that when a driver is enabled, it drives either a zero or a
one. Also, *only one driver can be enabled at any one time(.
Open-drain means that when a line is disabled, its output is high-z and an
external resistor is required to pull the signal up to a valid logic level.
When the line is enabled, it drives a zero. Many open-drain outputs can
drive a line simultaneously. This is common for interrupt requests and
such.
In other words, they're highly similar but their functions are different.
Given:
entity that is
port (
oe_l : in std_logic; -- output enable
tri_in : in std_logic; -- tristate buffer input
tri_out : out std_logic; -- tristate buffer output
od_out : out std_logic); -- open-drain driver output
end entity that;
architecture this of that;
begin
tri_out <= tri_in when oe_l = '0' else 'Z';
od_out <= '0' when oe_l = '0' else 'Z';
end architecture that;
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 21392
boniolopez@my-deja.com wrote in message <8b5mrk$k76$1@nnrp1.deja.com>...
>Hi all,
>I'm not very new in FPGA design but I can't find the issue of following
>problem:
>
>
>WARNING:Timing:33 - Clock nets using non-dedicated resources were found
>in this
> design. Clock skew on these resources will not be automatically
>addressed
> during path analysis. To create a timing report that analyzes clock
>skew for
> these paths, run trce with the '-skew' option.
>
>
>
>I'm quite sure to use in my design the deducted clock resources only
>(and connected to BufG or Buf GP). I think the syntheses tool can'
>recognise some part in my design and form it so, that clock some FF
>with the gated signal. But I cant find where.
>
>THE QUESTION: How I can find out where the Alliance 2.1i found the non-
>dedicated resources(which signal is such clock)?
Wow. I had the exact same problem. (scroll down in your newsreader; maybe
the articles haven't expired yet). turns out that it had to do with crossing
clock domains and such. One of the Xilinx apps guys sent me a note with a
shell script that parses ncdread's output so you can find out if there
really is a problem.
In FPGA Editor, you can highlight your clock nets and print out the chip. I
plotted mine onto E-size paper. Unfortunately, FPGA Editor only prints out
in gray-scale, so that fancy-shmancy HP DesignJet wasn't all that helpful.
--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 21393Simpler an safer, yes. But it would not eliminate the unnecassary power in the clock distribution. Designing for low power mmay force you to do strange things... Peter Alfke, Xilinx Applications ==================================== Jared Church wrote: > Well possible. > > But wouldn't it be simpler to just have one clock and put a clock enable on > each part of the design, then enable and disable as necessary in the same > way ? > > jc > > "Nicolas Matringe" <nicolas@dotcom.fr> wrote in message > news:38D63858.2A94786B@dotcom.fr... > > Hi all > > I am working on a design which may be used in two products, one of which > > won't need some functions of the design. I don't want to have 2 designs > > (we won't make 2 ASICs). > > I was wondering if it was possible to have 2 clock domains (same > > frequency) with the possibility to turn one of them off to reduce power > > consumption (this would be done by pulling a pin high or low for > > example) > > -- > > Nicolas MATRINGE DotCom S.A. > > Conception electronique 16 rue du Moulin des Bruyeres > > Tel 00 33 1 46 67 51 11 92400 COURBEVOIE > > Fax 00 33 1 46 67 51 01 FRANCEArticle: 21394
Send email to JBits@xilinx.com to get more info about JBits. Prasanna Bingfeng Mei wrote: > Where can I find information about JBit? I searched the Xilinx's website, and > got some pieces of message. But they are so simple and out-of-date. > Daryl Bradley wrote: > > > You can now do evolution with the Virtex > > If you get hold of Jbits for Virtex you can do all the evolutionary > > processes in JAVA - and make sure the bit streams are valid before they are > > downloaded. > > > > Peter Alfke <palfke@earthlink.net> wrote in message > > news:38D08376.95DFB62C@earthlink.net... > > > Sorry, Xilinx is sold out. I tried previously and could not dig up any > > parts. > > > And I have a bit of clout... > > > Peter Alfke > > > =============================== > > > Peter Sutton wrote: > > > > > > > Does anyone know if XC6200 series devices can be obtained anywhere > > anymore? > > > > The Xilinx University Program told me no, I'm just wondering if there > > are > > > > any out there to be had. > > > > > > > > (I have a senior project student who wanted to try some Silicon > > Evolution > > > > experiments and an architecture which won't blow up with a random > > bit-stream > > > > and lets you work backwards to a design is kind of useful.) > > > > > > > > Thanks, > > > > Peter > > > > -- > > > > Dr Peter Sutton > > > > Department of Computer Science and Electrical Engineering > > > > The University of Queensland > > > -- Prasanna 3/20/00Article: 21395
Wouldn't you use both edges ? I had the same problem some time ago (and YOU solve it ;o) boniolopez@my-deja.com a écrit : > > Hi all, > now I still see all my 4 clocks using BufG or BufGp also my QUESTION IS > STILL ACTUAL. > > The second question now: > Below the results trce -skew. > > Why this constrain is not met if 177<250!!!!!!!!! > * TS_gpp1_dup0 = PERIOD TIMEGRP "gpp1_dup0" | 250.000ns | 177.536ns | > 28 > 250 nS HIGH 50.000 % | | > | > Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 21396
Call for Participation
CASES 2000
International Conference on
Compilers, Architectures and Synthesis for Embedded Systems
http://www.capsl.udel.edu/conferences/cases2000
November 17-19, 2000
Doubletree Hotel
San Jose, CA, USA
Submission deadline August 14, 2000
CONFERENCE OBJECTIVES
The purpose of this working conference, the third in the series,
is to provide a forum for discussing emerging technology themes in
embedded computing systems design.
Over the past decade, substantial research has gone into the
design of general-purpose microprocessors embodying parallelism at
the instruction-level, as well as aggressive compiler optimization
and analysis techniques for harnessing this parallelism. Growing
demand for high performance in embedded systems is creating new
opportunities to leverage technologies such as instruction-level
parallelism (ILP) or Explicitly Parallel Instruction Computing (EPIC).
Examples of application areas with the need for high performance and
application specific embedded computing include set-top boxes,
hand-held games, mobile and web appliances, and advanced automotive
systems.
However, several novel challenges have to be overcome in order
to harness the opportunities offered by emerging technologies in the
context of embedded systems. Constraints on cost, code size, weight,
power consumption and real-time requirements place stringent
requirements on processors and the software they execute. In addition,
design time is an important issue because of the growing demand for
rapid time-to-market.
Technical as well as position papers espousing significant novel
ideas and technical results are solicited. Conference topics include
(but are not limited to) the following:
* Novel architectures and micro-architectures for embedded
systems based on ILP.
* Automated design and synthesis of application or domain
specific processors.
* Application or domain specific designs.
* Light-weight languages for temporal specification. Optimizing
compilers for ILP exploitation in the presence of temporal
constraints.
* Synergy between extant parallel computing technologies, such as
notations for expressing concurrency, and instruction level
parallel processing.
* Harnessing the interaction between the hardware and software
layers, spurred by innovations in reconfigurable or adaptive
computing systems.
* Characterizing the need of research infrastructure development
for embedded systems based on adaptive technologies.
* Compiler Controlled Memory Hierarchy Management and Smart Caches.
* System-on-a-Chip architectures/compilers and embedded software
including heterogeneous multiprocessor embedded systems.
* Compiler optimizations and synthesis for improved exploitation of
power versus performance tradeoffs.
In addition to presentations, the conference will feature
* Two keynote lectures by experts:
Amir Pnueli, The Weizmann Institute and New York University
B. Ramakrishna (Bob) Rau, Hewlett-Packard Labs
* One expert panel on the following topic:
System on a Chip: Hardware Dream or Software Nightmare?
INFORMATION FOR AUTHORS:
Please submit either one electronic copy of the paper in postscript
format to the following email address, or FIVE hard copies to the program
chair at the address given below. There is no page limit, but the paper
must not exceed 4000 words in length.
E-mail address for submission: CASES@capsl.udel.edu
Mail address for submission:
Krishna V. Palem
CASES 2000
School of Electrical and Computer Engineering
Georgia Institute of Technology
801 Atlantic Drive
Atlanta, GA 30332-0250
USA
IMPORTANT DATES:
Papers due: August 14, 2000
Author notification: September 25, 2000
Camera ready copy due: October 23, 2000
ORGANIZING COMMITTEE
Steering Committee:
James R. Boddie, Lucent Technologies
Guang R. Gao, University of Delaware
Vinod Kathail, Hewlett-Packard Labs
Edward Lee, University of California Berkeley
Reid Tatge, Texas Instruments
Conference Chair:
Krishna Palem, Georgia Institute of Technology and New York University
Local Arrangements Vice-Chair:
Praveen Murthy, Angeles Design Systems
Panels Vice-Chair:
Jack Davidson, University of Virginia
Publications Vice-Chair:
Jaime Moreno, IBM T.J. Watson Research Center
Publicity Vice-Chair:
Vincent Mooney, Georgia Institute of Technology
Program Committee:
Shuvra S. Bhattacharyya, University of Maryland
Henk Corporaal, Delft University of Technology
Srinivas Devadas, Massachusetts Institute of Technology
Christine Eisenbeis, INRIA Rocquencourt
Antonio Gonzalez, Universitat Politecnica de Catalunya
Rajesh Gupta, University of California at Irvine
Nevin Heintze, Lucent Bell Laboratories
Kathryn S. McKinley, University of Massachusetts, Amherst
Lothar Thiele, ETH Zurich
Frank Vahid, University of California at Riverside
Wei Zhao, Star Core
Article: 21397
I have as resources a Xilinx board with the XC4000e. I am looking for a
project that can be comfortably done within 2-3 weeks and that deals with
packet filtering or image processing. I would really appreciate all the
help.
thanks,
--
---------------------------------------------------
"time and space are modes by which we think...... |
they are not the conditions in which we live." |
|
~~Einstein |
---------------------------------------------------
Anshuman Sharma
Georgia Institute of Technology, Atlanta Georgia, 30332
Email: gte600f@prism.gatech.edu
anshu@abraxis.com
Article: 21398Hi everyone! I have a question for Vref pin of Virtex chip. I read the artcle of Vref pin in the data sheet for Virtex. It says to me that for to achive proper I/O backing, I must connect the Vref pins to accurate voltage level. When I read the report file(.pad file) for pad location generated after implementation, I don,t find any Vref pin. So I can't connect this pin correct voltage level. This pin number(Vref pin number) is allocated as user IO pin. Why? I have used Foundation 2.1 software. And I have other questions for pad file(.pad). The report file inform me about pad location in two different view. One is "pin name" and the other is "pin number". Which view of two teachs me the every pin location information exist in Virtext chip? Thank you for read my question? I use "XCV300-5-FG456" The order number "XCV300-5-FG456" say to me that This chip has only 456 pin. But the pad report file(.pad) report 484 pin to me in the second (pin number)view.Why? TIhank you for reading my question.Article: 21399
Hi Dears, I'm looking for Xilinx Spartan synthesis libraries(.db/sdb files) for Synopsys. Where to get it? Thank you.......
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