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Messages from 46050

Article: 46050
Subject: Re: Altera Byteblaster MAX7k programming problem
From: steen@tech-forge.com (Steen Larsen)
Date: 15 Aug 2002 08:53:29 -0700
Links: << >>  << T >>  << A >>
> Any ideas anybody???
>
I would suspect the socket, especially if it is a non-ZIF and you have
used it
over 50 times.  Maybe put a scope on the device while in the socket
and look
at the programming signals while it is being programmed.  If a loose
connection
you will probably see noise.  (Can you replace the socket?)

Also there are at least two Altera byteblaster drawings I have seen. 
The
older one did not have parallel termination on either the parallel bus
interface or the device side.  (I forget which).  If you don't have
it, I think a 1Kohm pullup on all signals going to/from the 244 would
help with noise.

Seems like the problem is between the 244 and 7xxx, since the
programmer seems to detect the loopback signal in the 244.

Good luck,
-Steen

Article: 46051
Subject: Re: Altera Byteblaster MAX7k programming problem
From: edaudio2000@yahoo.co.uk (ted)
Date: 15 Aug 2002 09:04:52 -0700
Links: << >>  << T >>  << A >>
Russell <rjshaw@iprimus.com.au> wrote in message news:<3D5A409F.6F27B9E0@iprimus.com.au>...
> ted wrote:
> > 
> > I have a circuit with an Altera Max7128 CPLD. On the same board there
> > is a programming circuit using a 74HC244 (exactly as per ALTERA
> > byteblaster
> > specs). The whole thing connects to a parallel port on the PC, which
> > is
> > running the latest MAX IDE.
> 
> Last i looked, the 'exact' specs omit the bypass capacitor across
> the 74HC244. Have you got one?
Yes thanks. I have placed decoupling caps everywhere.

I have more or less reduced the problem by adding a 180pf capacitor between 
JTAG TDO and ground. Still have to touch the wire every so often. But 
the problem is now more bearable...(:-(

Article: 46052
Subject: 2 questions using Synplify Pro.
From: darthhen@yahoo.com (Henry)
Date: 15 Aug 2002 09:39:35 -0700
Links: << >>  << T >>  << A >>
Hi,

I'm synthesizing a design in Synplify Pro for Xilinx xc2v6000 part. I
have a couple of questions:

1. Is there a constraint that allows me to invert the output signal.
For example, if the core is outputting a high, but the I/O pad will
output a low.

2. Is there a constraint that allows me to specifiy which output port
will not be connected, meaning no connect. Currently in the design,
there are certain output ports that doesn't need to be connected to
I/O pad. Disabling I/O insertion will do it for the entire design
which is not what I want.

I guess I can always modify the top level Verilog file for this but I
was wondering if there's a way to do this in the tool.

Thanks in advance.

With Regards,
Henry

Article: 46053
Subject: Re: 2 questions using Synplify Pro.
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Thu, 15 Aug 2002 13:29:17 -0400
Links: << >>  << T >>  << A >>
> 1. Is there a constraint that allows me to invert the output signal.
> For example, if the core is outputting a high, but the I/O pad will
> output a low.

Why not just invert the signal in the top level Verilog:

output O_x_N ;
assign O_x_N = ~x ;

> 2. Is there a constraint that allows me to specifiy which output port
> will not be connected, meaning no connect. Currently in the design,
> there are certain output ports that doesn't need to be connected to
> I/O pad. Disabling I/O insertion will do it for the entire design
> which is not what I want.

This may be best done in the .UCF file by using:

CONFIG prohibit = PinNumber ;

...and that will keep a signal from being assigned to that pin.

I know of no Synplify constraints that would do that.  I believe the
inversion has to be in the Verilog, as it is a logic construct.

Austin




Article: 46054
Subject: Re: transputers
From: hypi@gmx.net
Date: 15 Aug 2002 10:44:43 -0700
Links: << >>  << T >>  << A >>
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:<ajdl5a$5co$1@helle.btinternet.com>...
> <hypi@gmx.net> wrote in message
> news:3215928b.0208140333.3cc4957c@posting.google.com...
> > Is the transputer still constructed and used today? Please send us the
> > name of constructor and latest type of transputer.
> >
> > Thank you in advance!
> 
> I think the last transputer was made about five years ago. I've got an
> unused development system a friend gave me.
> 
> A couple of universities are making transputer-like systems with other CPUs.
> They are implementing the link engines in an FPGA.
> 
> Leon

Thank you! And do you know any of these universities you mention?

Article: 46055
Subject: Re: transputers
From: hypi@gmx.net
Date: 15 Aug 2002 10:45:35 -0700
Links: << >>  << T >>  << A >>
"Jan Gray" <jsgray@acm.org> wrote in message news:<ajdr71$s53$1@slb6.atl.mindspring.net>...
> Please see John Jakson's recent posting on T2 at
> http://groups.google.com/groups?selm=38111bbc.0208080412.4d310323%40posting.
> google.com, and also http://fpgacpu.org/log/dec01.html#011210.
> 
> Jan Gray, Gray Research LLC
> FPGA CPU News: www.fpgacpu.org

I thank you for your replies!

But what is the current transputer people work with?

And if it is the ST20, do you know if it is a real transputer?

Article: 46056
Subject: Re: EDIF netlist from XST
From: tom curran <tom_curran@memecdesign_dot_com>
Date: Thu, 15 Aug 2002 11:37:29 -0700
Links: << >>  << T >>  << A >>
Using the "-ofmt ngo_edif" option will give you a EDIF and NGC file,
but NOT an NGO file.  You must still run the EDIF or NGC thru NGDBUILD
to get an NGO file.

--Tom


---
Tom Curran
tom_curran@memecdesign_dot_com

Article: 46057
Subject: Re: Xilinx tools: which one? Esp. schematic
From: ryan_rs@c4.com (Ryan)
Date: 15 Aug 2002 12:40:26 -0700
Links: << >>  << T >>  << A >>
Thanks for your recommendations.  They are:
  * Use a smaller board and WebPack.  Total cost is $2k instead of
$5-6k.
  * Use verilog.
  * Simulate everything first.

Regarding the smaller chips.  The only other FPGA I'm familiar with is
the XC4010XL.  It claims 10k gates.  SpartanE claims 300k (for
WebPack).  I understand these numbers are pretty much lies, but maybe
a Spartan is worth 30 4010s?  But the Spartan likely has more RAM so
closer to 20x 4010.

Compared to my first micro, it seems that a 4x or 8x wider datapath,
I/D/TLB caches, pipelining, SDRAM controller, IDE, etc etc may be a
very tight fit.  I am entertaining the idea of eventually porting
NetBSD to this machine.  So I don't want to be caught short of silicon
three quarters of the way through.

Question:  Is it possible to implement all of this stuff in a 300k
Spartan?  I'd like the processor to be as fast as, say, a fast 486. 
Possible?  Difficult?


Regarding Verilog.  I will take a look at it.  I really enjoyed using
the schematic capture tools though, so no promises.

Regarding simulation.  First simulate, then jtag.  Of course.  I used
some sort of functional simulator in Foundation for my first micro. 
I'm not sure what it was called.  I wrote my own software that would
take assembly and output megabytes of stimulus.  I was able to execute
code in the simulator.  The actual hardware pretty much worked when I
finally dug out the programming cable.

Ryan

Article: 46058
Subject: Re: Reed-Solomon polynom transform....
From: samg@codenet.net
Date: Thu, 15 Aug 2002 19:52:19 GMT
Links: << >>  << T >>  << A >>
Agreed, comparing 285 to any other of the 16 GF(2**8) codes is Apples
and Oranges. 
They run on the same math algorithms but they are in no  way
compatible with respect to encode and decode.

Sam

On Sat, 10 Aug 2002 22:50:45 -0500, Mike Rosing
<rosing@neurophys.wisc.edu> wrote:

>Eric Smith wrote:
>> samg@codenet.net writes:
>> 
>>>I agree that systematic RS system will have the data portion unchanged
>>>but the parity section will screw up the Syndrome generators that are
>>>trying to determine if there is an error.
>>>The reason being that the GF math logic will be slightly different for
>>>285 vs 301, right? 
>>>
>> 
>> The logic to transform the codes would be as complex as the
>> logic to simply decode and reencode.
>> 
>
>If not more complex :-)
>
>-- 
>Mike Rosing
>www.beastrider.com                   BeastRider, LLC
>SHARC debug tools
>


Article: 46059
Subject: Re: Problem with Xilinx mapper
From: "Josh Model" <model@ll.mit.edu>
Date: Thu, 15 Aug 2002 16:01:48 -0400
Links: << >>  << T >>  << A >>
Hello,
Assuming your part is a Spartan IIE-FG456, Pin N2 is a general purpose I/O,
not a clock input.  (Check the pinout info in the Xilinx datasheets).
Your "clk_100" is probably well distributed through your design (depending
on its size), so you probably want to stick with the dedicated clock input
pins (AA12, AB12, A11,C11).  The Mapper inferred a BUFGP (a IBUF connected
to a BUFG in a single IOB, I believe) for the clock in your design.  These
guys efficiently take an input and send it right into the clock distribution
network.  However, since pin N2 doesn't have a BUFG, the mapping failed.
If you're on a Proto-board and can't get at the clock input pins for some
reason (and are reluctant to pull the oscillator that came with the board),
I've gotten around this problem by LOC'ing the clock input to pin N2,
manually instantiating an IBUF, then manually instantiating a BUFG,
connecting the two with a signal.  Chances are this doesn't do wonders for
skew, but it seems to me, so long as a decent signal gets to the BUFG
resource, from there on out you're safe.  Perhaps others on this erudite
list can back me up or shoot me down - I've only used this technique for 20
MHz designs.
Or, there may be a way to turn off inferring the BUFGP in the XST- Mapper.
Anyone?

In any event, your best bet is to simply send the clk_100 signal to one of
the dedicated clock pins.

--Josh Model

"BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no> wrote in
message news:1029424195.442008@halvan.trd.sintef.no...
> Hi all,
>
> I have a problem generating a programming file for my latest Verilog code.
> The mapper says that I have an illegal LOC. The pin N2 is connected to a
> 50-pin header on my SpartanIIe test board. Do you see anything wrong in
> this?
>
> The error message:
>
> Release 4.2WP0.x - Map E.35
> Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
> Using target part "2s300efg456-6".
> ERROR:MapLib:93 - Illegal LOC on symbol "clk_sd" (pad signal=clk_sd) or
> BUFGP
>    symbol "clk_sd_BUFGP" (output signal=clk_sd_BUFGP), IPAD-IBUFG should
> only be
>    LOCed to GCLKIOB site.
>
> From the ucf file:
>
> # #
> NET "clk_sd" LOC = "N2";
> NET "clk_100" LOC = "AB12";
> NET "din_sd" LOC = "M2";
> NET "reset_local" LOC = "D8";
> NET "transmitting" LOC = "F1";
>
> From the v file:
>
> module bit_transfer (clk_100, reset_local, din_sd, clk_sd, parallel_out,
> par_msb, transmitting);
>  input clk_100;      // 100MHz clock
>  input reset_local;    // a local reset button
>  input din_sd;      // bitstream data input
>  input clk_sd;      // bitstream clock.
>  output [7:0] parallel_out;  // output to send to parallel port
>  output par_msb;     // are we currently sending a most significant byte?
>  output transmitting;    // positive flank for valid outdata
>  reg [7:0] parallel_out;
>  reg par_msb;
>  reg transmitting;
> ...
>  always @(negedge clk_sd or negedge reset_local) // sigma-delta data is
> valid at negative clock edge
>  begin
> ...
> end
>
>
> Thanks,
>
> BÝrge
>
>



Article: 46060
Subject: oops
From: "Josh Model" <model@ll.mit.edu>
Date: Thu, 15 Aug 2002 16:20:44 -0400
Links: << >>  << T >>  << A >>
Oops.  Chalk that one up to not reading carefully. Take Clk_sd out of the
sensitivity list, and (in VHDL-speak) use an if-then, or case-when for those
signals. Drive everything off clk_100, and catch the negative edge yourself.
that is, assuming Clk_100 is at least 2X faster than CLK_sd.  Or if you
REALLY need clk_sd to be a genuine clock, pull the trick I mentioned in the
last post.  It's probably not a great idea to have 2 clock domains in 1
module, though.
All this is assuming you use clk_100 to drive something.  If not, then the
previous post applies, except to Clk_sd.

--Josh


"BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no> wrote in
message news:1029424195.442008@halvan.trd.sintef.no...
> Hi all,
>
> I have a problem generating a programming file for my latest Verilog code.
> The mapper says that I have an illegal LOC. The pin N2 is connected to a
> 50-pin header on my SpartanIIe test board. Do you see anything wrong in
> this?
>
> The error message:
>
> Release 4.2WP0.x - Map E.35
> Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
> Using target part "2s300efg456-6".
> ERROR:MapLib:93 - Illegal LOC on symbol "clk_sd" (pad signal=clk_sd) or
> BUFGP
>    symbol "clk_sd_BUFGP" (output signal=clk_sd_BUFGP), IPAD-IBUFG should
> only be
>    LOCed to GCLKIOB site.
>
> From the ucf file:
>
> # #
> NET "clk_sd" LOC = "N2";
> NET "clk_100" LOC = "AB12";
> NET "din_sd" LOC = "M2";
> NET "reset_local" LOC = "D8";
> NET "transmitting" LOC = "F1";
>
> From the v file:
>
> module bit_transfer (clk_100, reset_local, din_sd, clk_sd, parallel_out,
> par_msb, transmitting);
>  input clk_100;      // 100MHz clock
>  input reset_local;    // a local reset button
>  input din_sd;      // bitstream data input
>  input clk_sd;      // bitstream clock.
>  output [7:0] parallel_out;  // output to send to parallel port
>  output par_msb;     // are we currently sending a most significant byte?
>  output transmitting;    // positive flank for valid outdata
>  reg [7:0] parallel_out;
>  reg par_msb;
>  reg transmitting;
> ...
>  always @(negedge clk_sd or negedge reset_local) // sigma-delta data is
> valid at negative clock edge
>  begin
> ...
> end
>
>
> Thanks,
>
> BÝrge
>
>



Article: 46061
Subject: Re: Xilinx tools: which one? Esp. schematic
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Thu, 15 Aug 2002 21:30:10 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <7299ab58.0208151140.679451a3@posting.google.com>,
Ryan <ryan_rs@c4.com> wrote:
>Thanks for your recommendations.  They are:
>  * Use a smaller board and WebPack.  Total cost is $2k instead of
>$5-6k.
>  * Use verilog.
>  * Simulate everything first.
>
>Regarding the smaller chips.  The only other FPGA I'm familiar with is
>the XC4010XL.  It claims 10k gates.  SpartanE claims 300k (for
>WebPack).  I understand these numbers are pretty much lies, but maybe
>a Spartan is worth 30 4010s?  But the Spartan likely has more RAM so
>closer to 20x 4010.

Think in terms of slices/CLBs:

The 4010 is what, ~460 CLBs? (2 4-luts, a 3 lut, and 2 flip flops per
CLB).

While the XC2S300E is 1500 CLBs, so 3000 CLB Slices (each slice being
2 4-luts, an F5 mux, and 2 flip flops), plus 8 KB of BlockRAMs.  So,
discounting the memory, the spartan 2 is 6x bigger in slices.  The
memories are a BIG deal however.

>Compared to my first micro, it seems that a 4x or 8x wider datapath,
>I/D/TLB caches, pipelining, SDRAM controller, IDE, etc etc may be a
>very tight fit.  I am entertaining the idea of eventually porting
>NetBSD to this machine.  So I don't want to be caught short of silicon
>three quarters of the way through.

>Question:  Is it possible to implement all of this stuff in a 300k
>Spartan?  I'd like the processor to be as fast as, say, a fast 486. 
>Possible?  Difficult?

Thought on my own.

Pipelining is easy.  Go with a classic 5-6 stage pipeline and all
should be happy.  An easily achieved target clock rate would be 70+
MHz and should be straightforward to get.  If you want more
throughput, C-slow & retime the core to get a multithreaded
architecture.  The basic datapath for a MIPS-like processor is around
400 slices.  In whatever format you use, hand specify the datapath
layout, it gives 10% or more performance easily.

The RF, caches and TLB are best done as BlockRAMs, probably fairly
small.  The memory controller is pretty simple if you don't get fancy
on taking advantage of DRAM paging options, but could get complex if
you want to start squeezing performance.  

ISA I don't know about, I've never looked at it.  Might you not want
compact flash instead?  Less bandwidth, but you can boot off the card
with the proper ASIC from xilinx, and microdrives are 1GB.

I'd say use MIPS or a small-register-windowed SPARC as your ISA,
simply so you don't have compiler issues.  SPARC I know you can
release, MIPS I think so.  Arm is also nice from an ISA viewpoint, but
they have patent lawyers and ISA related patents and ENFORCE them
against ISA clones.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 46062
Subject: Re: Problem with Xilinx mapper
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Thu, 15 Aug 2002 18:18:03 -0400
Links: << >>  << T >>  << A >>
It appears that the pin you have chosen for the signal is a BUFGP, from what
the tool reports, which is what you should be using for a clock pin...but
you haven't told the synthesis tools that the signal is in fact using a
BUFGP...  In Synplicity, you would use a synthesis directive on the signal
declaration as follows:

input clk_sd  /* synthesis xc_clockbuftype = "BUFGP" */ ;

or what ever you want, ..."BUFGDLL" etc.

You can also get an error (warning may be) if you have a clock that is NOT
on a BUFG...and you would use the directive "/* synthesis syn_noclockbuf = 1
*/" between the declaration and the ";".

Austin



"BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no> wrote in
message news:1029424195.442008@halvan.trd.sintef.no...
> Hi all,
>
> I have a problem generating a programming file for my latest Verilog code.
> The mapper says that I have an illegal LOC. The pin N2 is connected to a
> 50-pin header on my SpartanIIe test board. Do you see anything wrong in
> this?
>
> The error message:
>
> Release 4.2WP0.x - Map E.35
> Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
> Using target part "2s300efg456-6".
> ERROR:MapLib:93 - Illegal LOC on symbol "clk_sd" (pad signal=clk_sd) or
> BUFGP
>    symbol "clk_sd_BUFGP" (output signal=clk_sd_BUFGP), IPAD-IBUFG should
> only be
>    LOCed to GCLKIOB site.
>
> From the ucf file:
>
> # #
> NET "clk_sd" LOC = "N2";
> NET "clk_100" LOC = "AB12";
> NET "din_sd" LOC = "M2";
> NET "reset_local" LOC = "D8";
> NET "transmitting" LOC = "F1";
>
> From the v file:
>
> module bit_transfer (clk_100, reset_local, din_sd, clk_sd, parallel_out,
> par_msb, transmitting);
>  input clk_100;      // 100MHz clock
>  input reset_local;    // a local reset button
>  input din_sd;      // bitstream data input
>  input clk_sd;      // bitstream clock.
>  output [7:0] parallel_out;  // output to send to parallel port
>  output par_msb;     // are we currently sending a most significant byte?
>  output transmitting;    // positive flank for valid outdata
>  reg [7:0] parallel_out;
>  reg par_msb;
>  reg transmitting;
> ...
>  always @(negedge clk_sd or negedge reset_local) // sigma-delta data is
> valid at negative clock edge
>  begin
> ...
> end
>
>
> Thanks,
>
> BÝrge
>
>



Article: 46063
Subject: Re: Modelsim VHDL problem
From: John Williams <j2.williams@qut.edu.au>
Date: Fri, 16 Aug 2002 08:23:28 +1000
Links: << >>  << T >>  << A >>
Thanks everyone for your help,

It seems my original syntax is indeed correct for VHDL '93, but  I had
not explicitly put Modelsim into '93 mode.  By doing so it now works
fine (well it compiles, now I'll find all my logical errors!! )

What confused me is that I'd previously written and run testbenches
using file IO, but had not passed FILE objects as parameters.  I'd had
no problems with Modelsim in it's default configuration before, so I
assumed it was defaulting to VHDL '93.

Strange, but at least it's solved now. 

Thanks again,

John

Article: 46064
Subject: Re: rising_edge detector?
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Thu, 15 Aug 2002 16:04:19 -0700
Links: << >>  << T >>  << A >>

shay wrote:


> I want generate pulse when detect rising_edge of specific signal,
> and supply this pulse to enother box and execute command due to this
> pulse & after off some flag & wait to next rising_edge.
> Note: the 2 boxes (detect rising_edge and execute command) are use
> with different sync.
> (in VHDL)


For syncronized inputs, I detect low to high transitions by invoking
a procedure like this inside a clocked process:

ck_rising(watch      => some_sig,
          last_low   => some_variable_v,
          result     => rising_edge_v  ); 


With the following variable, fuctions and procedure in scope:

variable some_variable_v : boolean;  -- previous level of some_sig


   -- purpose: convert active high bit to boolean
function now_high (std_arg : std_ulogic)  -- input bit
      return boolean is begin
      if std_arg = '1' then return true;
      else return false;
      end if;
end function now_high; -----------------------------------------------------


   -- purpose: convert active low bit to boolean
function now_low (std_arg : std_ulogic)   -- input bit
      return boolean is begin
      return not now_high(std_arg);
end function now_low; ------------------------------------------------------

    --  purpose: synthesizable low to high detection procedure
procedure ck_rising(
                  watch    : in std_ulogic;
                     -- watch this for edge, used on right side only so IN.
                  last_low : inout boolean;
                     -- value last time, used on left and right so INOUT
                  result   : out boolean
                     -- used on left only so OUT.
                        ) is begin
    result := now_high(watch) and last_low;
       -- check for active edge based on variable assigment last time;
    last_low := now_low(watch);  -- last_low used left and right thus inout
        -- assign variable for next time
end procedure ck_rising; ---------------------------------------------------


-- Mike Treseler


Article: 46065
Subject: Re: Xilinx tools: which one? Esp. schematic
From: ryan_rs@c4.com (Ryan)
Date: 15 Aug 2002 20:08:30 -0700
Links: << >>  << T >>  << A >>
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:<ajh6h2$2gcb$1@agate.berkeley.edu>...
> So,
> discounting the memory, the spartan 2 is 6x bigger in slices [than XC4010XL].  The
> memories are a BIG deal however.

Hmmm.  6x is even smaller than I thought.  I'm sure a small 32 bit
core would fit, but I'd like to have more space to play around with. 
I guess if I have to decide if I want to spend an extra $3500 for that
flexibility.  My initial guess is yes... <checks finances> but  maybe
no.  I should stick to hardware.


> ISA I don't know about, I've never looked at it.  Might you not want
> compact flash instead?  Less bandwidth, but you can boot off the card
> with the proper ASIC from xilinx, and microdrives are 1GB.

I like the CF suggestion.  Thanks.


> I'd say use MIPS or a small-register-windowed SPARC as your ISA,
> simply so you don't have compiler issues.  SPARC I know you can
> release, MIPS I think so.  Arm is also nice from an ISA viewpoint, but
> they have patent lawyers and ISA related patents and ENFORCE them
> against ISA clones.

ISA design is one of the funnest parts!  And porting the gcc chain is
also part of the project.

-Ryan

Article: 46066
Subject: Re: Xilinx tools: which one? Esp. schematic
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 16 Aug 2002 03:41:01 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <7299ab58.0208151908.61aa191b@posting.google.com>,
Ryan <ryan_rs@c4.com> wrote:
>> I'd say use MIPS or a small-register-windowed SPARC as your ISA,
>> simply so you don't have compiler issues.  SPARC I know you can
>> release, MIPS I think so.  Arm is also nice from an ISA viewpoint, but
>> they have patent lawyers and ISA related patents and ENFORCE them
>> against ISA clones.
>
>ISA design is one of the funnest parts!  And porting the gcc chain is
>also part of the project.

Use LCC, its much easier to retarget.

Also, how much do you REALLY gain vs having more established tools?
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 46067
Subject: Re: rising_edge detector?
From: leotran@att.net (Loi Tran)
Date: Fri, 16 Aug 2002 03:51:06 GMT
Links: << >>  << T >>  << A >>
In article <c59f97bb.0208150417.39337d91@posting.google.com>, shay@agrologic.com (shay) wrote:
>Hellow!
>I want generate pulse when detect rising_edge of specific signal,
>and supply this pulse to enother box and execute command due to this
>pulse & after off some flag & wait to next rising_edge.
>Note: the 2 boxes (detect rising_edge and execute command) are use
>with different sync.
>(in VHDL)
>Thanks in advance!!!

Try this out.  Be sure to test it completely before you use it.  I just pulled 
it out of my ass.  Basically it's a state machine that will wait, until it 
encounters a high on the SIG_IN and then runs through until it gets to a wait 
state.  This state continually loops until, the user sets CLR to high at which 
time it goes back to the initial ready for next pulse state.

library IEEE;
use IEEE.std_logic_1164.all;

entity re_pulse is
    port (
        CLK: in STD_LOGIC;
        SIG_IN: in STD_LOGIC;
        CLR: in STD_LOGIC;
        PULSE: out STD_LOGIC
    );
end re_pulse;

architecture b_latch_arch of b_latch is

-- BINARY ENCODED state machine: state
type state_type is (A, B, D, C);
attribute enum_encoding : string;
attribute enum_encoding of state_type: type is
        "00 " &         -- A
        "01 " &         -- B
        "10 " &         -- D
        "11 ";          -- C
        
signal state: state_type;
        
begin

process (clk)
begin

if clk' event and clk = '1' then
        case state is
                when A =>
                        if SIG_IN = '1' then
                                state <= B;
                        else
                                state <= A;
                        end if;                 
                when B =>
                        state <= C;
                when C =>
                        state <= D;
                when D =>
                        if CLR = '1' then
                                state <= A;
                        else
                                state <= D;
                        end if;
                when others =>
                        state < = A;
        end case;
end if;
end process;

-- signal assignment statements for combinatorial outputs
OUTPUT <= '1' (when state = B) else '0';

end b_latch_arch;

Article: 46068
Subject: Re: transputers
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Fri, 16 Aug 2002 05:39:04 +0000 (UTC)
Links: << >>  << T >>  << A >>


<hypi@gmx.net> wrote in message
news:3215928b.0208150944.2b5dbb62@posting.google.com...
> "Leon Heller" <leon_heller@hotmail.com> wrote in message
news:<ajdl5a$5co$1@helle.btinternet.com>...
> > <hypi@gmx.net> wrote in message
> > news:3215928b.0208140333.3cc4957c@posting.google.com...
> > > Is the transputer still constructed and used today? Please send us the
> > > name of constructor and latest type of transputer.
> > >
> > > Thank you in advance!
> >
> > I think the last transputer was made about five years ago. I've got an
> > unused development system a friend gave me.
> >
> > A couple of universities are making transputer-like systems with other
CPUs.
> > They are implementing the link engines in an FPGA.
> >
> > Leon
>
> Thank you! And do you know any of these universities you mention?

http://sdl.fit.qut.edu.au/stuprojects/muir_hobson_211101.html

Leon
--
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller




Article: 46069
Subject: Xilinx suppliers in UK
From: wdh@elsec.co.uk (William Hall)
Date: Fri, 16 Aug 2002 07:58 +0100 (BST)
Links: << >>  << T >>  << A >>
I seem to be being quoted silly prices for Virtex-II Pro. Can anyone 
suggest a good supplier for FPGAs in UK.

How much are /you/ paying for 100 off?


William Hall
Remove any X in my email address

Article: 46070
Subject: MicroBlaze processor core
From: "Holger Venus" <Holger.Venus@dlr.de>
Date: Fri, 16 Aug 2002 09:04:58 +0200
Links: << >>  << T >>  << A >>
Hi all,
does any body has experience with embedded processor IP cores in FPGA?
I am especial interested on the behaviour of the Xilinx MicroBlaze usage.
What are the main functions the processor is used for?
What about the code size?
What about the processing power, the FPGA system clock?
How where the own modules connected to the processor core, via the IBM
core connect bus (OPB)?
Where the gnu software tools suitable for development and test / debug?
Would you do it the same way or why not?
Could this way open a path to a V2PRO migration of a family of designs
(start with MicroBlaze and expand to V2PRO if available as needed?

Thanks for any (related) comment,

Holger Venus





Article: 46071
Subject: Re: transputers
From: "Holger Venus" <Holger.Venus@dlr.de>
Date: Fri, 16 Aug 2002 10:07:49 +0200
Links: << >>  << T >>  << A >>
Hi,
I do not know if there exist a real Transputer chip today but there was done
some
development in the space industry. You should perform a WWW search on "1355
space wire".
1355 is the transputer serial bus protocol. See WWW.1355.org
The European Space Agency ESA (ESTEC) supported the development of some
support chips for processor node based systems (parallel processing, fault
tolerance,..).
One example is the MOSAIC board developed by Dornier and used for the deep
space ROSETTA mission.
There were also developed some FPGA implementation of 1355.
Regards,
Holger Venus


<hypi@gmx.net> schrieb im Newsbeitrag
news:3215928b.0208140333.3cc4957c@posting.google.com...
> Is the transputer still constructed and used today? Please send us the
> name of constructor and latest type of transputer.
>
> Thank you in advance!



Article: 46072
Subject: Re: Problem with Xilinx mapper
From: "BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no>
Date: Fri, 16 Aug 2002 11:11:29 +0200
Links: << >>  << T >>  << A >>
Thanks Austin, Josh

any idea how I enter this into the WebPack's verilog editor and compiler?

I'd like to know how to interface the DLLs and use different kinds of
clocks.

I'm sorry I didn't write anything about the frequencies of the clock
signals. clk_100 is 100MHz, clk_sd is 1MHz. So I guess I'm going to follow
Josh's tip and detect the flank in clk_sd manually.

BÝrge

"Austin Franklin" <austin@da98rkroom.com> wrote in message
news:uloa4sigksanc2@corp.supernews.com...
> It appears that the pin you have chosen for the signal is a BUFGP, from
what
> the tool reports, which is what you should be using for a clock pin...but
> you haven't told the synthesis tools that the signal is in fact using a
> BUFGP...  In Synplicity, you would use a synthesis directive on the signal
> declaration as follows:
>
> input clk_sd  /* synthesis xc_clockbuftype = "BUFGP" */ ;
>
> or what ever you want, ..."BUFGDLL" etc.
>
> You can also get an error (warning may be) if you have a clock that is NOT
> on a BUFG...and you would use the directive "/* synthesis syn_noclockbuf =
1
> */" between the declaration and the ";".
>
> Austin
>
>
>
> "BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no> wrote in
> message news:1029424195.442008@halvan.trd.sintef.no...
> > Hi all,
> >
> > I have a problem generating a programming file for my latest Verilog
code.
> > The mapper says that I have an illegal LOC. The pin N2 is connected to a
> > 50-pin header on my SpartanIIe test board. Do you see anything wrong in
> > this?
> >
> > The error message:
> >
> > Release 4.2WP0.x - Map E.35
> > Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
> > Using target part "2s300efg456-6".
> > ERROR:MapLib:93 - Illegal LOC on symbol "clk_sd" (pad signal=clk_sd) or
> > BUFGP
> >    symbol "clk_sd_BUFGP" (output signal=clk_sd_BUFGP), IPAD-IBUFG should
> > only be
> >    LOCed to GCLKIOB site.
> >
> > From the ucf file:
> >
> > # #
> > NET "clk_sd" LOC = "N2";
> > NET "clk_100" LOC = "AB12";
> > NET "din_sd" LOC = "M2";
> > NET "reset_local" LOC = "D8";
> > NET "transmitting" LOC = "F1";
> >
> > From the v file:
> >
> > module bit_transfer (clk_100, reset_local, din_sd, clk_sd, parallel_out,
> > par_msb, transmitting);
> >  input clk_100;      // 100MHz clock
> >  input reset_local;    // a local reset button
> >  input din_sd;      // bitstream data input
> >  input clk_sd;      // bitstream clock.
> >  output [7:0] parallel_out;  // output to send to parallel port
> >  output par_msb;     // are we currently sending a most significant
byte?
> >  output transmitting;    // positive flank for valid outdata
> >  reg [7:0] parallel_out;
> >  reg par_msb;
> >  reg transmitting;
> > ...
> >  always @(negedge clk_sd or negedge reset_local) // sigma-delta data is
> > valid at negative clock edge
> >  begin
> > ...
> > end
> >
> >
> > Thanks,
> >
> > BÝrge
> >
> >
>
>



Article: 46073
Subject: Re: Fun FPGA system
From: "Manfred Kraus" <newsreply@cesys.com>
Date: Fri, 16 Aug 2002 11:29:30 +0200
Links: << >>  << T >>  << A >>
Bill,
If everyone here would promote his products, this NG
would be completly useless. Please think about that
before advertising again.

-Manfred

"Bill Diehls" <billabloke@yahoo.com> schrieb im Newsbeitrag
news:4855d4d8.0208100958.304903e3@posting.google.com...
> Hi all,
> There is an interesting product for the Gameboy that uses a Xilinx
> Spartan FPGA.  It costs $129 for the development kit and it looks like
> a lot of fun to experiment with.  The company (www.charmedlabs.com)
> promotes open-source development and encourages users to write their
> own FPGA bitstreams and software.  Not your typical development
> system, but worth a look.
>
> Bill Diehls



Article: 46074
Subject: Re: Testing the X2S_USB Spartan 2 board
From: "Manfred Kraus" <newsreply@cesys.com>
Date: Fri, 16 Aug 2002 11:41:14 +0200
Links: << >>  << T >>  << A >>
Hi Sani Abacha,

one quick solution:
you could define a 90-Bit ring-shift-register in VHDL and connect each
bit to an output. Initialise the first FlipFlop to '1' and the others to
'0'.
When shifting the '1' round again and again, it can be observed at
the outputs.
Measure with an Oszi or LA whether all I/Os are working correctly.
-Manfred

"Ogah" <oogah@stud.fh-heilbronn.de> schrieb im Newsbeitrag
news:ajc7j0$q44$1@news.BelWue.DE...
> Hello all I am a greenhorn in this area and i was wondering if anyone
could
> help me on the issue of testing the X2S USB board. what would be the
> quickest way of verifying pin functions? please i'd be very grateful for
any
> help on this.
>
> Thanks
> Sani Abacha
>
>





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