Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Take a look at the multipliers page on my website. It doesn't get explained
better anywhere else I am aware of. You need more info on the requirements
before you do the design though: how many clocks per sample are available?
If you can make it several clocks, then the hardware gets simpler.
Kuan Zhou wrote:
> Hi,
> I am going to implement a small MAC (multiply-accumulation) unit on
> FPGA.But I can't find any detailed information on its architecture.All the
> architechtures on the papers are very complicated.I need an easy,small
> implementation.Does anyone know any materials describing it?
>
> Thank you very much!
>
> sincerely
> -------------
> Kuan Zhou
> ECSE department
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47776I read a paper on string matching in FPGAs and (once I figured out all the typos and incorrect algorithms) started using ideas from it, until I started thinking about it and noticed something that didn't make sence. [This paper does not seem to be available online anymore, but it's called Parallel String Matching Algorithms Based on Dataflow. Maybe someone can find it and look at figure 2 and 8.] Figure 2 shows a string travelling through a shift register, after every shift the pattern matcher checks to see if the pattern is in the string. Simple. Figure 8 shows something more complicated, "which is more profitable for exploiting maximum parallelism." Instead of having a register do a shift to advance the string one character, the string is fed through parallel delay lines. One with 0 delays, the next with one delay, the two, etc. These lines are then fed directly to the pattern matcher. The pattern matcher sees the exact same data, but this supposedly removes "dependencies among input arcs to the computation part becaue the [shift register bytes] are connected horizontally ... [which] can be an obstacle for seeking explicit parallelism," whatever that means. Anyone? Okay, fine, they don't bother to explain what the performance difference is but I believed them. Until, I realized that you are still going to need a shift register to feed this circuit the characters one at a time. They've only moved the supposed bottleneck, not removed it. They never explain how this new stream is to be created, but in algortihm 2 they say off-hand the input should be that was "as we discussed so far." So, are they right and I'm just dumb? My questions are: 1) Is there a reason the shift register design would be slower/less parallel? 2) Wont a shift register be just as slow/non-parallel as the FIFO between this circuit and the RAM? Thank you.Article: 47777
Hey, that's about what my module does. I'm not sure whether Arne is reading these replys anymore, since he only responded to the first one. This is probably more efficient than a fifo, does about the same thing, and is more easily portable. BB ========================================= > This isn't what you asked for, but it might be good enough. > > You can get a weighted-average without any memory if you can multiply. > The recent samples get more weight and the weight of older samples decays > exponentialy. > > Formula is: > new-avg = old-avg*(1-w) + sample*w > Where w is less than 1. > > Values of w like 1/8 are typically used in networking code to > "average" out round trip time measurements. >Article: 47778
has anybody used these boards From Alpha-Data ADM-XRC-II Lite ADM-XRC-II From nallatech ... DIME II We are trying to decide which is a more viable investmentArticle: 47779
Hi, I'm trying to run an Altera provided example on their DSP development board and get the following error : "Run time error '8005' : Port already open". Does anyone have a clue what this is about and how can I fix it ? It seems to have something to do with the serial port, but I'm not sure how to fix it. Just to let you know, the serial port seems to be working fine and using another cable was of no use either. Thanks, PrashantArticle: 47780
russelmann@hotmail.com (Rudolf Usselmann) wrote in message news:<d44097f5.0210022345.6eba246d@posting.google.com>... > Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote in message news:<qh8z1hsb85.fsf@ruckus.brouhaha.com>... > > russelmann@hotmail.com (Rudolf Usselmann) writes: > > > The USB 2.0 core is currently being tested by another customer of > > > mine with an Spartan 2e ... > > > > How many LUTs does the USB 2.0 core require? > > > It depends on the configuration of the core. But to > give you a basic idea: > > USB 2.0 with 4 endpoints: > part: xc2s200e pq208-6 > Total LUTs: 2837 (60%) > clk_i 107.2 MHz > phy_clk_pad_i 67.3 MHz (required 60MHz) > > > USB 1.1 (including usb 1.1 PHY, with 8 endpoints but no > endpoint FIFOs): > part: xc2s200e ft256-6 > Total LUTs: 876 (18%) > clk_i 4.2 MHz (required 48MHz) Sorry this should have been 74.2Mhz (not 4.2 ;*) rudi ---------------------------------------------- www.asics.ws - Solutions for your ASIC needs - > > Hope this helps ! > Best regards, > rudi > ---------------------------------------------- > www.asics.ws - Solutions for your ASIC needs -Article: 47781
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<an200d$a6dlf$1@ID-84877.news.dfncis.de>... > "Dongho" <dhan@ecel.ufl.edu> schrieb im Newsbeitrag > news:f6f40449.0209261223.55d8b63a@posting.google.com... > > I intend to implement adaptive FIR(LMS) with 100~600 inputs. > > I need to update within every 100ms, number of filter tap is 10, input > > precision is 8bits, and coef. precision is 8bits. > > Is it hard to implement with ALTERA(especially updating coef.)? How > > about with Stratix? Is it same? > > Wasnt this question around a while ago? As Ray Andraka said, its better to > solve this really slow speed stuff with a conventional DSP, since the tools > and designer for DSPs are much more common available. ;-) > Stratix is DEFENITELY overkill for this. Now I'm trying to update the coefficients in 1ms and there are 100 input channels. If I use two 16x8 LUT and adder for these two LUT to implement FIR for one input channel, do I need to prepare another 99 pairs LUTs and adders for 99 input channels FIR ? And how to update those LUTs after calculating the errors?Article: 47782
Hi Ulises Hernandez, Thank you for your good advice,I will try it just as you propose. Because our programmer is not here now,Maybe I will test the configruation on 8th Oct.I wish you will be here and I will tell you my test result.:o) Another question,in Verilog it seems that there isn't a ROC module,how I can I resolve this problem as you mentioned point 3? Best Regards. CisaArticle: 47783
"skillwood" <skillwood@hotmail.com> wrote in message news:<anhas6$e4ro0$1@ID-159866.news.dfncis.de>... > Hi all, > Can some one give me an introduction to low power SoC design . What is > difference from an ordinary design and low power design in the design stage > . Suppose I am designing a fsm based sequential logic , at which stage the > "LOW POWER " Comes in . > > thanks > skillie Understand first when a CMOS device "burns" power: Each time a node changes level (from 0 to 1; or from 2 to 0). [There is lot more but thats typically controlled by the technology vendor, use a LOW-POWER library if you are doing an ASIC ...] >From the coding aspect, there are two things you can do: 1) Reduce the Clock speed 2) Reduce overall toggle rate To reduce the clock might not be easy if you are in an FPGA. If you are using a DPLL in an FPGA you might be able to change the clock rate. For example from "full speed" to "half speed". Make sure clock change is synchronous and glitch free .... The ultimate in "saving power" would be to turn the clock off all together. This might not always be practical or possible. The second technique, is to reduce toggles in your design. Make sure only registers that *have to* change, change. Make sure there is nothing toggling without any need. Use Clock Enables to enable and disable blocks when they are needed. Specially if you use counters, disable them when not needed. There should be absolutely nothing togeling when you are idle (well, I guess this is design dependent but you get my point ...:*) Hope this helps ! Cheers, rudi ---------------------------------------------- www.asics.ws - Solutions for your ASIC needs -Article: 47784
I am configuring an EP1K30 with a microprocessor. I send all the bytes in the .RBF file, as instructed by their app note. The part comes out of configuration and goes into user mode BEFORE all the bytes are sent; specifically, after the first of the three FFs at the end of the file are sent. This causes a problem because the extra two writes upset the logic. The question is, are those last two FFs necessary? Forget asking Altera; I have gone round and round with them for over a month and can get absolutely NOWHERE. Their tech support is unbelievably incompetent, and even on a promise to 'ask someone who knows', my requests have been dropped/ignored. Sure with I had gone down the Xilinx learning curve instead....Article: 47785
I was in charge of a design that was very similar to yours. You can actually program the FPGA through the ISA bus. There are essentially three was to program the FPGA: JTAG (Byteblaster), EEPROM configuration devices or the parallel method. This still will allow you to have upgradable firmware without the need to re-program EEPROM devices and will get you out from under the issue of dual booting. All of the information on how to do this is contained within the altera documentation. Keith "Ru-Chin Tsai" <m8931612@student.nsysu.edu.tw> wrote in message news:d22f039b.0210031044.2a9c73a4@posting.google.com... > I now emulate ISA bus model and my core design on the FLEX 10k. PC can > communicate with my core design for large testbench. Now the FLEX 10k > act as a I/O card device. It is assigned with a IRQ and a segment of > I/O port address. ISA I/O device must be initialized at 'power on' of > motherboard. And the OS will load my device driver when booting. The > problem is that I use ByteBlaster(LPT) to download programming data of > FPGA. So I must boot twice, one for programming FPGA as a ISA I/O > device(contian ISA bus model and my core design) and the other for > initialing ISA I/O device and loading my device driver. Does I can > program FPGA without PC and ready the ISA I/O device first, then power > on the PC? Which programming method sould I select?Article: 47786
In article <d44097f5.0210031756.65c8d614@posting.google.com>, russelmann@hotmail.com (Rudolf Usselmann) wrote: >"skillwood" <skillwood@hotmail.com> wrote in message > news:<anhas6$e4ro0$1@ID-159866.news.dfncis.de>... >> Hi all, >> Can some one give me an introduction to low power SoC design . What is >> difference from an ordinary design and low power design in the design stage >> . Suppose I am designing a fsm based sequential logic , at which stage the >> "LOW POWER " Comes in . >> >> thanks >> skillie >Understand first when a CMOS device "burns" power: Each time a >node changes level (from 0 to 1; or from 2 to 0). [There is lot >more but thats typically controlled by the technology vendor, >use a LOW-POWER library if you are doing an ASIC ...] > >From the coding aspect, there are two things you can do: >1) Reduce the Clock speed >2) Reduce overall toggle rate > >To reduce the clock might not be easy if you are in an FPGA. If >you are using a DPLL in an FPGA you might be able to change the >clock rate. For example from "full speed" to "half speed". Make >sure clock change is synchronous and glitch free .... >The ultimate in "saving power" would be to turn the clock off all >together. This might not always be practical or possible. > >The second technique, is to reduce toggles in your design. Make >sure only registers that *have to* change, change. Make sure >there is nothing toggling without any need. Use Clock Enables >to enable and disable blocks when they are needed. Specially if >you use counters, disable them when not needed. There should be >absolutely nothing togeling when you are idle (well, I guess this >is design dependent but you get my point ...:*) > >Hope this helps ! > >Cheers, >rudi >---------------------------------------------- >www.asics.ws - Solutions for your ASIC needs - You could also stop the clock going to subsytems that aren't necessary at the time.Article: 47787
Is there any FPGA which has an PROM on it so that we can program with thie PROM instead of an external PROM which makes PCB difficult to do? CPLD is too small for an application anyway.Article: 47788
Hi Cisa, The ROC module is the Reset On Configuration module embedded in some Xiinx devices, I use it when the synthesis tool doesn't infer the reset logic I am looking for. It's not a VHDL magic command at all :o), is a dedicated resource and therefore it can also be instantiated in Verilog, the only thing you need to remember is to add the UNISIM library for simulation proposals. If you don't add the UNISIM library you will get a WARNING in compilation (no problem) and a WARNING or NOTE in synthesis inferring a black box called ROC (no problem), the built tool (Design Manager in ISE) will use the ROC block in the chip with no warnings at all. For more info look in Xilinx: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= 1&getPagePath=4686 Remember to use it active high!! Regards If you need any help let me know. Ulises Hernandez Design Enginner ECS Technology Ltd. www.ecs-tech.com "Cisa" <jjyy@hotmail.com> wrote in message news:ee794a2.5@WebX.sUN8CHnE... > Hi Ulises Hernandez, > > Thank you for your good advice,I will try it just as you propose. > Because our programmer is not here now,Maybe I will test the configruation on 8th Oct.I wish you will be here and I will tell you my test result.:o) > > Another question,in Verilog it seems that there isn't a ROC module,how I can I resolve this problem as you mentioned point 3? > > Best Regards. > > Cisa >Article: 47789
Hi,
I have just been introduced a new Lattice family that is called ispXPGA.
Maybe I shouldn't think this but is a Virtex E like FPGA (BlockRAM, 8 PLLs,
lots of I/O standars, 1.8V Core...) but the biggest difference is that is
non volatile :o) (it also includes 850MBps SERDES channels). It's SRAM based
(volatile) but it also includes an EE memory (NV). They claim that the SRAM
area is programmed in <200us from the EEPROM (not bad) when you boot the
board up and that you can program the EE on the fly, at the same time the
SRAM 'FPGA' is running you can update the EE memory ('reprogram on system
opration - 15 seconds for a big part :( '); this is useful in systems with
multiple images for a single chip.
But...there is an overhead to this, what happens if the power goes off when
you are updating your EE memory :o)? will it boot up next time with a
corrupted image? is there a backup EE memory?
They were uncertain about the answer and wanted to check with technical
support.
It seems quite promising, I don't know about Altera, Atmel...I know Xilinx
doesn't have anything like that with such a number of gates (1.25 Million
gates)
Regards
Ulises Hernandez
Design Enginner
ECS Technology Ltd.
www.ecs-tech.com
"Karl" <Far@East.Design> wrote in message
news:3d9d3652@news.starhub.net.sg...
> Is there any FPGA which has an PROM on it so that we can program with thie
> PROM instead of
> an external PROM which makes PCB difficult to do? CPLD is too small for an
> application anyway.
>
>
>
>
>
>
Article: 47790"Ulises Hernandez" <ulises@britain.agilent.com> writes: > For me the interesting bit is the RTL coding, for a FSM as you said, you can > use one-hot encoding because only one-bit will change every clock (reduces > clock activity which is a killer in power consumption). If you change from One-hot encoding will cause *two* bits to change at each state transition. Grey-encoding will cause only one bit to change. However, in many cases it will be diffucult to make gray code for all state transitions. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 47791
Ray Andraka <ray@andraka.com> writes: > I agree that the C to hardware things have their place. If nothing else, it > lowers the bar for entry into FPGAs. What is missing is the necessary caveat > explaining that there is a lot of performance/density left on the table...and > that is much more than is commonly touted. I think an order of magnitude > wouldn't be far wrong as an average. > I wouldn't argue there! Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 47792
"Tim" <tim@rockylogic.com.nooospam.com> writes: > Martin Thompson wrote: > > > Celoxica have some fairly impressive demos. In particular, the > > ray-tracing one I saw (can't find a reference for it though). > > > Yes, the device may be bigger than required, but if the development > > time is reduced by an order of magnitude, surely that's a gain, in > > some circumstances? Especially in the research realm, where some > > problems may be intractable because a) software isn't fast enough, b) > > the HW solution will take too long to design the traditional way. > > Good point, but AFAIK Celoxica's solution is occam, with a C syntax. > Occam is a reasonable solution to the problem. It is probably not > too difficult to fiddle with the VHDL syntax to make it more C-like, > but you would not be moving the problem forwards. > As I see it (and I'm not an expert in Handel-C by any stretch of the imagination!) the big difference is that Handel-C is serial with explicit parallelism, whereas VHDL is parallel with explicit serialism (you write your own state machine) > Parallel programming, as in hardware design, is much harder than > sequential programming. It is a little optimistic to hope that > we will be able to write a parallel program by > > 1. writing a sequential equivalent > 2. summoning up a magic parallelizer > Funny - just this debate has been going on on comp.arch recently, but I can't find it on google yet. <snip> Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 47793
"Christopher R. Carlen" wrote: > Ken Smith wrote: > > In article <3D9B8FDE.8000405@sandia.gov>, > > Christopher R. Carlen <crcarle@sandia.gov> wrote: > > [....] > > > >>Everything is pretty well thought out so far, I think. The only problem > >>is, the CPLD has 84 IOs available, of which I plan to use up to 40. 32 > > > > > > > > I suggest you spread the I/O connection among the logic blocks in logical > > groups. > > > > If you are fairly certain the other lines will not be needed, you can hook > > pairs of them together so that you have another way to get signals between > > logic blocks or you can wire up a socket for a 22V10 or spare I/O. This > > will help keep your options open. > > Perhaps it will suffice to bring the unused IOs out to vias. Then I can > tie them together later if need be. > > It may even be less trouble to build a new daughterboard for the XCR3256 > chip later on. But the XCR3128 seemed like it would give a lot of room > for growth over the XCR3064 which I originally considered. But the main > problem their was having to share the JTAG pins, which I wanted to avoid > for simplicity. > I don't think there's anything to stop you having multiple alternative connections to the same signal as long as, obviously, all but one are tristated. So pick the best one you can think of for the 40 I/Os and then double up the others until you run out of pins (e.g. allocate the alternates on the other side of the chip from the default). Another thing would be to have multiple `configurations' in the chip at the same time (one per engineer if poss) I.e. each pin's logic function is selectable via a header. Each magic box user would have a plug which they push onto the header to ``personalise'' (or DIP switches or, really slick, a little keypad (*)).You could go further so that when you reach the point where the engineers are re-programming the device they would each have their own code `module' ... (*) At this point you could even start adding some user id checks. If any of the engineers offends you in any way you can cut them out and display a message ``Access denied, please contact magic box administrator'' :-).Article: 47794
Hello, I want to simulate a VHDL code with the modelsim XE but it seems to not manage the IBUF component, described in my VHDL code. If I move the pin connected with the IBUF, i don't see its output moving. Can someone explain me why? Thanks.Article: 47795
Hello, I want to simulate a VHDL code with the modelsim XE but it seems to not manage the IBUF component, described in my VHDL code. If I move the pin connected with the IBUF, i don't see its output moving. Can someone explain me why? Thanks.Article: 47796
rickman <spamgoeshere4@yahoo.com> wrote in message > Your request is not completely clear to me, but I think you are looking > for a way to automatically load the FPGA on boot up. If your design is > a little more stable you can wire a serial EEPROM onto the board and the > FPGA will load directly from that. There are app notes on this at the > Altera web site. Atmel makes some nice reprogrammable parts for this. > I believe one or the other site even has plans on how to connect a > serial memory along with a cable to allow you to reprogram the EEPROM or > the FPGA, your choice, IIRC. > Yes, my purpose is to find re-propramming FPGA device without PC. Becuase the FPGA device will be programed as a ISA I/O device.Article: 47797
You are right Petter, Two bits change at each state in one-hot. I was probably thinking about Grey Code, as you said it's difficult to make grey code for all the transitions. I have heard that in your Memory Map the FW guys can change from binary to Grey Coding very easily in a uP, if your memoy map is massive this could reduce your power consumption, but it makes live more complicated, more difficult debug and more difficult coding in your VHDL. Good correction. Cheers Ulises Hernandez Design Enginner ECS Technology Ltd. www.ecs-tech.com "Petter Gustad" <newsmailcomp3@gustad.com> wrote in message news:m3u1k2vfca.fsf@scimul.dolphinics.no... > "Ulises Hernandez" <ulises@britain.agilent.com> writes: > > > For me the interesting bit is the RTL coding, for a FSM as you said, you can > > use one-hot encoding because only one-bit will change every clock (reduces > > clock activity which is a killer in power consumption). If you change from > > One-hot encoding will cause *two* bits to change at each state > transition. > > Grey-encoding will cause only one bit to change. However, in many > cases it will be diffucult to make gray code for all state > transitions. > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 47798
I don't kwon how works the judicial system in USA, is the last sentence definitive or there is some chance for Clear Logic to come back in business? IMHO, the out of business of Clear Logic is a drawback for the the Altera customers and for Altera same too. LuigiArticle: 47799
David R Brooks wrote: > > Running the Xilinx ISE 4.2i tools, I get a warning > ERROR:NgdBuild:455 - logical net 'N812' has multiple drivers > > Now the meaning is obvious enough, but the problem is, how to locate > this net (it is a synthesiser-generated name) in the hierarchy. The > tools don't give any indication where it is located. It is a large > project, with over 40 VHDL design elements in a deep hierarchy. > > A search of the output files shows none of them contain this string, > except the NGD log, which only contains the error as above. > > This error causes no post-synthesis VHDL file to be generated, else > one could search that file for the net. > > Any ideas? It's the synthesis tool that generates these "wonderful" names. It's probably because that synthesis tool tries to optimize a region of your design and then rename the signals with an internal name that is related to internal operation of optimization programs inside. I would suggest to switch off optimizations as much as possible. That way synthesis tool pays more attention not to change the signal names. It's practically much better to switch off optimizations. Human optimizations might be better than tool optimizations. Synplify has syn_keep and syn_preserve attributes. I use these attributes aggressively in order to keep track of what the tools do. It is also much much easier to find signal name in every phase of my design flow, like finding any signal in Signals Window of my simulator after post-layout simulation has run. Utku
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z