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"geeko" <jibin@ushustech.com> schrieb im Newsbeitrag news:anj552$eetho$1@ID-159027.news.dfncis.de... > Actually i am looking a solution which will internet enable 8 or 16 bit > devices .For applications such as remote sensors which communicate through > TCP/IP. I have doubts if a FPGA is the solution to this. There are a lot of small uCs on the maket with ready to use TCP/IP stuff. LOW power, LOW price, available NOW, almost plug and play. For sensors, which in most cases diver a very small datasteam, the power of a FPGA solution is total overkill. -- MfG FalkArticle: 47801
> implement FIR for one input channel, do I need to prepare another 99 > pairs LUTs and adders for 99 input channels FIR ? If you go this way, yes. But at such low sampling rates, its a good idea to do some multiplexing, means runn your DSP core at a high clock rate and use one MAC unit for multiple channels. > And how to update those LUTs after calculating the errors? There are many ways. You could use the LUTs a dual port distributed RAM. One port is for updating the coefficients, one for read access by the DSP engine. But again. Do a estimation on data throughput (sample rate, bit width of samples), estimate the number of operations needed to recalculate the coefficients, estimate the number of operations neede for the filter itself. Then compare this to common available DSP. THEN it is time to think about using a FPGA or DSP. -- MfG FalkArticle: 47802
"Ulises Hernandez" <ulises@britain.agilent.com> schrieb im Newsbeitrag news:1033720463.137875@cswreg.cos.agilent.com... > I have heard that in your Memory Map the FW guys can change from binary to > Grey Coding very easily in a uP, if your memoy map is massive this could > reduce your power consumption, but it makes live more complicated, more > difficult debug and more difficult coding in your VHDL. Why more difficult? AFAIK every uptodate VHDL compiler offers a setting on how to encode your FSMs. So in the code, you have only state names, NOT encoded vectors. Make the thing much more readable. -- MfG FalkArticle: 47803
<noone@aol.com> schrieb im Newsbeitrag news:amtppucmeahlsaju3pagmh5r1hqi1v0ad0@4ax.com... > I am configuring an EP1K30 with a microprocessor. I send all the > bytes in the .RBF file, as instructed by their app note. The part > comes out of configuration and goes into user mode BEFORE all the > bytes are sent; specifically, after the first of the three FFs at the > end of the file are sent. This causes a problem because the extra two > writes upset the logic. > > The question is, are those last two FFs necessary? Forget asking I suppose the two 0xFF are dummy bytes. AFAIK its similar to Xilinx devices, the FPGA need some (2..8??) additional clock cycles after all configuration data is written to the FPGA to start the FPGA. During this start phase, global reset and tristate lines are released. -- MfG FalkArticle: 47804
"Karl" <Far@East.Design> schrieb im Newsbeitrag news:3d9d3652@news.starhub.net.sg... > Is there any FPGA which has an PROM on it so that we can program with thie > PROM instead of > an external PROM which makes PCB difficult to do? CPLD is too small for an > application anyway. Actel has some. Lattice?? Other may have too. But whats the problem with a external PROM? They are available in tiny SO8 packages. And with serial configuration, just 4 lines go between the FPGA and the PROM. Hardly a PCB design issue. -- MfG FalkArticle: 47805
"Falk Brunner" <Falk.Brunner@gmx.de> writes: > Why more difficult? AFAIK every uptodate VHDL compiler offers a setting on > how to encode your FSMs. So in the code, you have only state names, NOT > encoded vectors. Make the thing much more readable. Your synthesis tool might have to add a lot of redundant bits to the states in order to make this happen. In some cases it might be difficult (for your synthesis tool that is). Imagine 10 states where there is a state transition from every single state to every other state. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 47806
Hi,
I have just been introduced a new Lattice family that is called ispXPGA.
Maybe I shouldn't think this but is a Virtex E like FPGA (BlockRAM, 8 PLLs,
lots of I/O standars, 1.8V Core...) but the biggest difference is that is
non volatile :o) (it also includes 850MBps SERDES channels). It's SRAM based
(volatile) but it also includes an EE memory (NV). They claim that the SRAM
area is programmed in <200us from the EEPROM (not bad) when you boot the
board up and that you can program the EE on the fly, at the same time the
SRAM 'FPGA' is running you can update the EE memory ('reprogram on system
opration - 15 seconds for a big part :( '); this is useful in systems with
multiple images for a single chip.
But...there is an overhead to this, what happens if the power goes off when
you are updating your EE memory :o)? will it boot up next time with a
corrupted image? is there a backup EE memory?
They were uncertain about the answer and wanted to check with technical
support.
It seems quite promising, I don't know about Altera, Atmel...I know Xilinx
doesn't have anything like that with such a number of gates (1.25 Million
gates)
Regards
Ulises Hernandez
Design Enginner
ECS Technology Ltd.
www.ecs-tech.com
"Karl" <Far@East.Design> wrote in message
news:3d9d3652@news.starhub.net.sg...
> Is there any FPGA which has an PROM on it so that we can program with thie
> PROM instead of
> an external PROM which makes PCB difficult to do? CPLD is too small for an
> application anyway.
>
>
>
>
>
>
Article: 47807
A one-hot is pretty much minimal power for a decoded state machine. All the
bits in a state machine necessarily have to have an even number of transitions
in a complete cycle of the state machine. The one-hot puts both transitions in
adjacent states. We've used a shft register style state machine where '1's get
shifted in. Sort of like a sticky one-hot. While this reduces the number of
input terms to each flip-flop, it only postpones the 1 to 0 transition to the
end of the cycle. A grey coded machine is an encoded machine. It has fewer
transitions (one per state instead of two) and less flip-flops so its power is
less. Be aware that any gains in the state machine might be lost in the state
decode, especially if there are not many 'hidden' states. A grey coded machine
becomes difficult to design with many branches unless extra filler states are
added, since every loop in the state diagram must have an even number of states.
Ulises Hernandez wrote:
> Hi,
>
> There are a lot of things to consider in a low power design.
>
> - Your core voltage (1.5V is a good figure)
> - Packaging aspects (lower die tempearature, 'the hotter it runs, the
> quicker it fails' :o)
> - Metal Layers (passive silicon no longer dissipates/sink heat in these days
> because there is no passive stuff)
> - ...
> - RTL code
>
> For me the interesting bit is the RTL coding, for a FSM as you said, you can
> use one-hot encoding because only one-bit will change every clock (reduces
> clock activity which is a killer in power consumption). If you change from
> state A to state B more often than to state C try state A and B encoded with
> low toggle rate ("most likely branch encoding"). Disabling your clock in
> your IDLE state could be interesting (if you have the capability to do it)
> and enable it with the scape condition.
> There are a whole bunch of things you could do.
> This Xilinx paper is quite interesting
> http://www.xilinx.com/xcell/xl38/xcell38_40.pdf
> Google also helps.
>
> Regards
>
> Ulises Hernandez
> Design Enginner
> ECS Technology Ltd.
> www.ecs-tech.com
>
> "skillwood" <skillwood@hotmail.com> wrote in message
> news:anhas6$e4ro0$1@ID-159866.news.dfncis.de...
> > Hi all,
> > Can some one give me an introduction to low power SoC design . What is
> > difference from an ordinary design and low power design in the design
> stage
> > . Suppose I am designing a fsm based sequential logic , at which stage
> the
> > "LOW POWER " Comes in .
> >
> > thanks
> > skillie
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47808
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No, the ROC is a simulation only device. It is there so that your simulation
matches the chip's initialization in the configuration. The xilinx tools remove
it from the netlist.
Ulises Hernandez wrote:
> Hi Cisa,
>
> The ROC module is the Reset On Configuration module embedded in some Xiinx
> devices, I use it when the synthesis tool doesn't infer the reset logic I am
> looking for. It's not a VHDL magic command at all :o), is a dedicated
> resource and therefore it can also be instantiated in Verilog, the only
> thing you need to remember is to add the UNISIM library for simulation
> proposals. If you don't add the UNISIM library you will get a WARNING in
> compilation (no problem) and a WARNING or NOTE in synthesis inferring a
> black box called ROC (no problem), the built tool (Design Manager in ISE)
> will use the ROC block in the chip with no warnings at all.
> For more info look in Xilinx:
> http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
> 1&getPagePath=4686
>
> Remember to use it active high!!
>
> Regards
> If you need any help let me know.
>
> Ulises Hernandez
> Design Enginner
> ECS Technology Ltd.
> www.ecs-tech.com
>
> "Cisa" <jjyy@hotmail.com> wrote in message news:ee794a2.5@WebX.sUN8CHnE...
> > Hi Ulises Hernandez,
> >
> > Thank you for your good advice,I will try it just as you propose.
> > Because our programmer is not here now,Maybe I will test the configruation
> on 8th Oct.I wish you will be here and I will tell you my test result.:o)
> >
> > Another question,in Verilog it seems that there isn't a ROC module,how I
> can I resolve this problem as you mentioned point 3?
> >
> > Best Regards.
> >
> > Cisa
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47809
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video makes for a slick demo. The data rates are not outrageously high (we've
done a fair amount with bit serial designs), updates per pixel are done at even
lower rates and the results look very impressive.
Martin Thompson wrote:
>
> Celoxica have some fairly impressive demos. In particular, the
> ray-tracing one I saw (can't find a reference for it though). The MP3
> decoder which "...took a two man team less than eight weeks to produce
> a working silicon prototype, including implementing a CD-ROM
> controller to allow management of the input data stream."
> http://www.celoxica.com/products/technical_papers/case_studies/cs_001.htm
>
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47810Falk Brunner <Falk.Brunner@gmx.de> wrote: > "Karl" <Far@East.Design> schrieb im Newsbeitrag > news:3d9d3652@news.starhub.net.sg... >> Is there any FPGA which has an PROM on it so that we can program with thie >> PROM instead of >> an external PROM which makes PCB difficult to do? CPLD is too small for an >> application anyway. > > Actel has some. Lattice?? Other may have too. But whats the problem with a > external PROM? They are available in tiny SO8 packages. And with serial > configuration, just 4 lines go between the FPGA and the PROM. Hardly a PCB > design issue. I don't understand this issue either. You have a PCB issue anyway with FPGAs with some hundred I/O pins, or even a BGA package - almost no chance to do with a two layer PCB. An SO8 package for a serial PROM should fit anywhere, even a normal PLCC or SO flat pack Flash PROM. It is just probably a problem for hobbyists who have even difficulties with a two layer PCB. Holger -- Please update your tables to my new e-mail address: holger.veit$ais.fhg.de (replace the '$' with '@' -- spam-protection)Article: 47811
Jan Gray wrote > In the XSOC/xr16 Kit, I used one hardwired channel of DMA to stream in video > data from external RAM. (Necessity (shoehorning the processor, video > controller, and rest of the SoC, into a '4005) being the mother of > invention.) The next step (not taken in xr16) is to add instructions to > programmatically schedule these DMA operations -- addresses, counts, > arbitration. Then you could call it an Alto. Not really, but I hope you are flattered by the comparison :-). Bell and Newell, first edition - the one which does not fit on your bookshelf - notes that the ultimate fate of every processor is to become a DMA controller. Though Cocke's the first ever RISC started out as a sort of DMA (really I/O) machine.Article: 47812
> Can some one give me an introduction to low power SoC design . What is
> difference from an ordinary design and low power design in the design stage
> . Suppose I am designing a fsm based sequential logic , at which stage the
> "LOW POWER " Comes in .
Dependent on the type of design you are planning to design, you might also want
to take a look at asynchronous design methods. If applicable, no synchronous
method can give you less power consumption.
--
greetz, |\_____---_____
Bas |/ (__|||__)
"""
Article: 47813On 25 Sep 2002, Jay wrote: > If your design fits on an 8000 family part, then your talking about a > really tiny design, so it will be a small part in any family. What chip do you suggest to me?? I don't know how big my design is going to be, so bigger fpga would be better, of course. Only thing is, the chip have to work on 2 layers PCB. If you somebody know good web-sites where is design examples about PCB's done for any FPGAs, please send me links!! - Jarmo jarmoma@mail.student.oulu.fiArticle: 47814
Jim Granville wrote: > > Scott Thibault wrote: > > > > Tcl interpreter uses a bytecode compiler internally to improve performance. > > That bytecode is not suitable for hardware implementation, however. We > > designed a special bytecode for this purpose, and yes, the FPGA is like a > > virtual machine for this bytecode. > > > > --Scott > > Sounds interesting - Can you post a small example of the flows ? > - something like tiny source code / intermediate sizes / final speed, > and size of the Tcl engine itself.. ? > > Not everyone here will know Tcl in detail, but the general > application of script handling within FPGA is usefull to get a handle > on. > > - jg Very sensible. Modelsim uses a Tcl bytecode virtual machine, like JVM. A very interesting processor design project. I wonder whether the bytecode instruction set is public or a custom set? UtkuArticle: 47815
Yeah, to be honest I am a hobbyist. I am not sure how I can make a good medium size FPGA on a twin layer PCB. "Holger Veit" <veit@borneo.gmd.de> wrote in message news:slrnapqu7q.ae3.veit@borneo.gmd.de... > Falk Brunner <Falk.Brunner@gmx.de> wrote: > > "Karl" <Far@East.Design> schrieb im Newsbeitrag > > news:3d9d3652@news.starhub.net.sg... > >> Is there any FPGA which has an PROM on it so that we can program with thie > >> PROM instead of > >> an external PROM which makes PCB difficult to do? CPLD is too small for an > >> application anyway. > > > > Actel has some. Lattice?? Other may have too. But whats the problem with a > > external PROM? They are available in tiny SO8 packages. And with serial > > configuration, just 4 lines go between the FPGA and the PROM. Hardly a PCB > > design issue. > > I don't understand this issue either. You have a PCB issue anyway with > FPGAs with some hundred I/O pins, or even a BGA package - almost no chance > to do with a two layer PCB. An SO8 package for a serial PROM should fit > anywhere, even a normal PLCC or SO flat pack Flash PROM. > > It is just probably a problem for hobbyists who have even difficulties > with a two layer PCB. > > Holger > > -- > Please update your tables to my new e-mail address: > holger.veit$ais.fhg.de (replace the '$' with '@' -- spam-protection) >Article: 47816
Have a look at techXclusives on the xilinx website. If I remember correctly, there is a useful artical on PCB design issues for FPGAs Adrian > On 25 Sep 2002, Jay wrote: > > > If your design fits on an 8000 family part, then your talking about a > > really tiny design, so it will be a small part in any family. > > What chip do you suggest to me?? I don't know how big my design is going > to be, so bigger fpga would be better, of course. Only thing is, the > chip have to work on 2 layers PCB. > > If you somebody know good web-sites where is design examples about PCB's > done for any FPGAs, please send me links!! > > - Jarmo > jarmoma@mail.student.oulu.fi > >Article: 47817
Check out this thread: http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&safe=off&threadm=c0f37b00.0209041241.5fbd5be5%40posting.google.com&rnum=7&prev=/groups%3Fq%3Drrr%2540ieee.org%2Bgroup:comp.arch.fpga%26hl%3Den%26lr%3D%26ie%3DUTF-8%26safe%3Doff%26selm%3Dc0f37b00.0209041241.5fbd5be5%2540posting.google.com%26rnum%3D7 Regards -rajeev- ---------------- Dali <dadicool@ifrance.com> wrote in message news:<3D9238B1.6080407@ifrance.com>... > I would look in the file generated by your synthesis tool (edif for > synplicity) because that's where the nets are named with such generic names. > > Then you can then look at the net drivers. What you can do also is to > ask the synthesis tool to preserve hierarchy so you can locate the net > into a module easily. > > Dali > > David R Brooks wrote: > > Running the Xilinx ISE 4.2i tools, I get a warning > > ERROR:NgdBuild:455 - logical net 'N812' has multiple drivers > > > > Now the meaning is obvious enough, but the problem is, how to locate > > this net (it is a synthesiser-generated name) in the hierarchy. The > > tools don't give any indication where it is located. It is a large > > project, with over 40 VHDL design elements in a deep hierarchy. > > > > A search of the output files shows none of them contain this string, > > except the NGD log, which only contains the error as above. > > > > This error causes no post-synthesis VHDL file to be generated, else > > one could search that file for the net. > > > > Any ideas? > >Article: 47818
"Scott Bilik" <sbilik@NOSPAM.mv.com> wrote
> [Disclaimer: I'm employed by ARC, but I'm an engineer, not in
marketing...]
> Regarding your comments about DMA engines, I find most of our
> customers, *especially* on the USB side, are very nervous at first
> about have the peripheral put the data right where you want it (or
> pull it right from memory)
Very interesting comment. This seems like one of those many cases where a
good engineering idea encounters resistance for non-technical reasons.
> > In the xr16 design, I replaced a single PC register with a 16-entry
> > "PC register file" that makes it easy to run multiple threads or do
> > multiple channels of DMA. Datapath cost (n-bit wide datapath): +n
> > LUTs, -n FFs. This idea can save you any number of DMA address
> > counter(s), address mux(es), and the address mux delay(s), elsewhere
> > in the design..
>
> Interesting about the multiple threads: do you rotate the general
> purpose register file of the xr16 (between multiple register files) in
> sync with the PC thread rotation? How do you keep context between the
> threads?
You can of course provide context for multiple threads (e.g. two thread
contexts -> double 16x16 register file to 32x16 entries) but in my area
optimized processors where the 2r1w-LUT-RAM-register file is already 20-30%
of the area, you could argue it might be better just to instantiate another
processor.
(In a design that already keeps the register file in BRAM/ESBs, multiple
thread contexts seem to be a bigger win (higher value at low cost).)
Rather, for xr16, I was thinking of a CPU with multiple PCs, but sharing a
single software partitioned/shared register file. So in a 16-register
design, the two threads might share 2 registers and each have 6-7 private
registers. You could even target that with a C compiler, although the
results wouldn't be too pretty.
In the specific case of xr16, using two thread PCs, but one shared register
file, is straightforward because:
* the only programmer visible state is the PC and the register file;
* the condition codes are implicitly accessed, and only within an
interlocked instruction sequence;
* ditto for the the immediate-prefix instruction's (logical)
immediate-prefix-register state.
The thread switcher/scheduler would have to respect the interlocked
instruction logic. For example, just as with interrupts, we would not
tolerate a thread-switch in the midst of an interlocked instruction
sequence:
imm 0xABC
addi r0,r1,0xD
beq label ;; pc = label if (r1 == -0xABCD)
The biggest problem for making xr16 2-threaded w/o doubling the register
file, is the call instruction:
call 0xABC ;; r15 = pc, pc = 0xABC0;
which implicitly updates r15. Either the second thread would have to take
care to issue the equivalent 2-instruction sequence:
imm 0xABC
jal r13,0 ;; r13 = pc, pc = 0xABC0;
or the call instruction would need to be changed to make the return address
register a function of the current thread index.
> We have two sets of x86 HDL cores -- Classic and Turbo. In our
> Turbo186 we threaded the standard programmable DMA engine tightly into
> the control of the general uProcessor execution engine to eliminate
> arbitration. If there are any DMA channels pending operation, the bus
> cycles are rotated automatically by the execution state machine:
>
> DMA read (1 cycle),
> opcode execution (1 cycle of it),
> DMA write (1 cycle),
> DMA read (1 cycle),
> opcode execution (1 cycle of it),
> DMA write (1 cycle),
> [...]
>
> This way there is no arbitration and the processor can't be starved
> by big DMA movement. The DMA engine needed the dead cycle anyway so
> at least the processor got to do some useful work in between.
Cool. The xr16 in the XSOC/xr16 project similarly allows (and interleaves
with 0 overhead) only 0 or 1 DMA cycles per instruction fetch cycle. This
only works if you can tolerate a little latency (~six-ish cycles worst case,
for the store-byte external RAM instruction, IIRC) between issuing the next
DMA word request and the DMA response. The XSOC video controller can
tolerate 8 cycles of latency before the pixel shift register starts sucking
air, so all is well.
> Have you made progress on the compiler/software side in the past
> couple of years?
I'm not sure what you mean by progress, but in a nutshell, no. The XSOC Kit
(fpgacpu.org/xsoc/) has been stopped at version 0.93 for two years. On the
other hand, besides the documented limitations and issues
(fpgacpu.org/xsoc/issues.html) there have been very few significant issues
reported since then.
The Kit 1.0 release, when and if it eventually happens, will fix a few
little issues, most notably far branch support. But more significantly, the
plan is to split the kit into a software-and-xr16-ISA piece, and a hardware
design piece, the former relicensed under a more liberal license.
(Although XSOC/xr16 is based upon lcc, I maintain that GCC toolchain support
is the prerequisite for widespread interest in and adoption of any new ISA.)
Jan Gray, Gray Research LLC
Article: 47819"Tim" <tim@rockylogic.com.nooospam.com> wrote > Then you could call it an Alto. Not really, but I hope you are > flattered by the comparison :-). It is rather too flattering, but thank you anyway. See also fpgacpu.org/usenet/alto.html. (*My* bookshelf, by the way, holds a Bell and Newell, and also a Siewiorek, Bell, and Newell. There's good stuff in the former that didn't make it into the latter. I am filled with awe and respect for the designers of these many wonderful machines, all built from "stone knives and bearskins", and all of this done before most of us were "knee high to a grasshopper". We're all just cranking the wheel of reincarnation now.) Jan Gray, Gray Research LLCArticle: 47820
See also (!!!): Bell and Newell: http://research.microsoft.com/~gbell/Computer_Structures__Readings_and_Examp les/index.html Siewiorek, Bell, and Newell: http://www.ulib.org/webRoot/Books/Saving_Bell_Books/SBN%20Computer%20Strucut res/ Jan Gray, Gray Research LLCArticle: 47821
It means paths not covered by other constraints. In this case paths not covered by the Clk constraint. Ensoul Chee wrote: > I am using synplify for a test. That is the log file of it. I am not > sure what does the System Line mean? Can any body give me a hand? > > Thanks in advance. > > Requested Estimated Requested Estimated Clock > Starting Clock Frequency Frequency Period Period Slack Type > ---------------------------------------------------------------------------------------------- > Clk 200.0 MHz 192.1 MHz 5.000 5.205 -0.205 inferred > System 200.0 MHz 816.3 MHz 5.000 1.225 3.775 system > ============================================================================================== >Article: 47822
Ru-Chin Tsai, just for completeness, you could also arrange to configure through the ISA interface. After booting the PC, automatically configuring the FPGA. You would probably need some added circuit to reset the FPGA (unless you were in a very controlled environment and could use a non-standard signal to reset the FPGA.) For what it is worth, you may want to look at my MS thesis design of master/slave parallel processing at www.tech-forge.com. Good luck, -Steen "cookielady" <cookieNOlady@insightSPAMbb.com> wrote in message news:<l18n9.39470$dp1.112828@rwcrnsc52.ops.asp.att.net>... > I was in charge of a design that was very similar to yours. You can > actually program the FPGA through the ISA bus. There are essentially three > was to program the FPGA: JTAG (Byteblaster), EEPROM configuration devices > or the parallel method. This still will allow you to have upgradable > firmware without the need to re-program EEPROM devices and will get you out > from under the issue of dual booting. > > All of the information on how to do this is contained within the altera > documentation. > > Keith > > "Ru-Chin Tsai" <m8931612@student.nsysu.edu.tw> wrote in message > news:d22f039b.0210031044.2a9c73a4@posting.google.com... > > I now emulate ISA bus model and my core design on the FLEX 10k. PC can > > communicate with my core design for large testbench. Now the FLEX 10k > > act as a I/O card device. It is assigned with a IRQ and a segment of > > I/O port address. ISA I/O device must be initialized at 'power on' of > > motherboard. And the OS will load my device driver when booting. The > > problem is that I use ByteBlaster(LPT) to download programming data of > > FPGA. So I must boot twice, one for programming FPGA as a ISA I/O > > device(contian ISA bus model and my core design) and the other for > > initialing ISA I/O device and loading my device driver. Does I can > > program FPGA without PC and ready the ISA I/O device first, then power > > on the PC? Which programming method sould I select?Article: 47823
Actually, this was what I was trying to say in my post. Sorry if it wasn't clear. You should not need additional reset circuitry for the FPGA. It automatically resets after configuration. Keith "Steen Larsen" <steen@tech-forge.com> wrote in message news:3e8d96d6.0210040814.29e1fdc6@posting.google.com... > Ru-Chin Tsai, just for completeness, you could also arrange to > configure through the ISA interface. After booting the PC, > automatically configuring the FPGA. You would probably need some > added circuit to reset the FPGA (unless you were in a very controlled > environment and could use a non-standard signal to reset the FPGA.) > > For what it is worth, you may want to look at my MS thesis design of > master/slave parallel processing at www.tech-forge.com. > > Good luck, > -Steen > > "cookielady" <cookieNOlady@insightSPAMbb.com> wrote in message news:<l18n9.39470$dp1.112828@rwcrnsc52.ops.asp.att.net>... > > I was in charge of a design that was very similar to yours. You can > > actually program the FPGA through the ISA bus. There are essentially three > > was to program the FPGA: JTAG (Byteblaster), EEPROM configuration devices > > or the parallel method. This still will allow you to have upgradable > > firmware without the need to re-program EEPROM devices and will get you out > > from under the issue of dual booting. > > > > All of the information on how to do this is contained within the altera > > documentation. > > > > Keith > > > > "Ru-Chin Tsai" <m8931612@student.nsysu.edu.tw> wrote in message > > news:d22f039b.0210031044.2a9c73a4@posting.google.com... > > > I now emulate ISA bus model and my core design on the FLEX 10k. PC can > > > communicate with my core design for large testbench. Now the FLEX 10k > > > act as a I/O card device. It is assigned with a IRQ and a segment of > > > I/O port address. ISA I/O device must be initialized at 'power on' of > > > motherboard. And the OS will load my device driver when booting. The > > > problem is that I use ByteBlaster(LPT) to download programming data of > > > FPGA. So I must boot twice, one for programming FPGA as a ISA I/O > > > device(contian ISA bus model and my core design) and the other for > > > initialing ISA I/O device and loading my device driver. Does I can > > > program FPGA without PC and ready the ISA I/O device first, then power > > > on the PC? Which programming method sould I select?Article: 47824
I second this notion. The typical CMOS clock tree can consume 30% of the total chip power. If you want to cut power, look for ways to reduce the number of clocked elements. Bas Arts wrote: >> Can some one give me an introduction to low power SoC design . What is >>difference from an ordinary design and low power design in the design stage >>. Suppose I am designing a fsm based sequential logic , at which stage the >>"LOW POWER " Comes in . >> > > Dependent on the type of design you are planning to design, you might also want > to take a look at asynchronous design methods. If applicable, no synchronous > method can give you less power consumption. > >
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