Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Here is a schematic of xilinxs parallel download cable: http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/appendixb.html As you can see, you need to enable the output with CTRL=0. To read TDO you need to set PROG=1. The voltage levels are never the less very problematic, as the typical PC parallel port drives the signal quickly to about 1.5V. The Following slope to 5V is extremely slow with a lot of noise added. If the 74HC125 is powered by 3V you are in trouble. Kolja Sulimma "valentin tihomirov" <valentin@abelectron.com> wrote in message news:<3da04990$1_2@news.estpak.ee>... > I've realized one interesting thing, the iMPACT sw forces TDO at POD to be > 5V (logic '1'), while my sequence (reset + IDCODE) forces TDO to 2V (logic > '1') and LPT can't recognize it as '1'. What's a secret of output voltage? > The logic analyzer I've buid is low speed and I can't record the sequence > sent by iMPACT. > I suppose I need to control some more signals than just TDI, TCK and TMS > from PC. There is neened something to enable CPLD->TDO->PC data stream. I > guess that Xilinx has inilially a mode driving TDO from PC to chenk cable > presence and then enables tdo from device. > > Thanks for any advice.Article: 47901
Hi, I am using a Logic which is generated from Xilinx's coregen. I am usign that logic in my design as a black box. In synpify_pro we have to mention the Timing Modles of a black box to perform the correct timing analysis. So, How can i get the stamp files (.mod,.data) for that coregen logic. Best regards, MuthuArticle: 47902
Casey <cjs1977@earthlink.net> wrote in message news:<ee796a7.-1@WebX.sUN8CHnE>... > Hello, > > I'm having problems simulating > a design in Foundation 3.1i using > a Synchronous FIFO core. I'm > receiving an "undetermined input > pin state" error for a pin name > internal to the CORE. All external > signals are defined. > > I've seen other postings with this > same problem but no solutions in > the threads. Does anyone have a > solution/suggestions for this > problem? > > Thanks much, > Casey Hi, You are getting some signals as 'x'. Is that u meant? Best regards, MuthuArticle: 47903
Assuming you're using the MaxPlus2 : -Have a schematic sheet open. file, new, graphic editor file. -right button, enter symbol -mega wizard plugin manager -create a new custom mega function, next -select 'storage' , whatever ..., AHDL (!), give it a filename, next -and so on Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net Sudip Saha wrote: > Hi, > Few days back I posted a message asking help for instantiation > of memory blocks in Altera devices. I got a reply saying it can be > used by using megawizard function. But I am facing a problem, > because it asks for lpm library. which I dont have, can anyone > please say me where can I get lpm library and its components?Article: 47904
Thank you for response. I've seen this schematic before, you reffered me to, but I can't understand the PROG signal. It seems that when it is active, it must pull TDO to 0, right? When PROG is low it passes TDO to LPT, right? But your words and test demonstrate the reverse situation, TDO is suppressed when PROG is low. It's strange. It's even more strange that the chip now responds incorrectly when I set PROG to high. With PROG=low I couldn't sence TDO at LPT; with PROG=high I can sence, but JTAG protocol misbehaves. What am I doing wrong? There is no information I can find explaining Xilinx cable behaviour. Thanks for any advice.Article: 47905
Not really. All of the signals
connected to the FIFO core are
defined. However, when I try
to simulate I get the "undetermined input pin state" for a WE pin on a RAM block that is an internal part of the FIFO core.
Thanks, Casey
Article: 47906"skillwood" <skillwood@hotmail.com> wrote in message news:<anhas6$e4ro0$1@ID-159866.news.dfncis.de>... > Hi all, > Can some one give me an introduction to low power SoC design . What is > difference from an ordinary design and low power design in the design stage > . Suppose I am designing a fsm based sequential logic , at which stage the > "LOW POWER " Comes in . > > thanks > skillie To do a ASIC low power, 1-you choose a technology with a very low voltage around 1V 2-you try to reduce as you can the clock frequency [remember the power is Cp*F*V*V] 3-applied a gated-clock strategy 4-best way gated-power strategy If you want some power computing and so some high speed, try to work with some standart cells define with two voltage, the low voltage for the block-low speed, and the high voltage for the block-high speed (tools from Synopsys can do that) 5-Use PowerCompiler to generate a better netlist after your synthesis (witha VCD-SAIF file) 6-In your code try to reduce the number of register... 7-You can use for FSM the Grey code, the impact is not so important. . Good luck for your design, Regis PS : in the conference ISSCC2001, there is a good presentation on Low Power Technique : "Low Power Design Techniques for Microprocessors " ISSCC, Feb4th 2001 Simon Segard VP Engineerring, ARM Inc.Article: 47907
Nothing like a customer to come to my defense :) You are a tough group. Answering the questions in order starting with Mr. Hays: - Setting the bar low would make for an easy way to meet the objectives. You can imagine that a vendor would like to do that for marketing purposes, however, none of our customers would pay us if we just went and spit out some "acceptable" result. They want a product that meets THEIR expectations and provides some additional benefit over what they are doing today. Otherwise, why change? - The product will duplicate resources when needed depending on the constraints. It is quite possible that having an additional multiplier to meet the performance goal uses less area than the muxing needed to reuse the existing ones. The product will figure that out. - I am obviously selling Forte's products from the standpoint of marketing them. In reality, I'm also a big proponent of the high-level synthesis movement in general -- which is really what I'm selling. I obviously believe we have advantages as well. - We don't directly have a floor planner nor do we plan to. However, the RTL code that comes out can go directly to floor planning, logic synthesis, power estimation, etc. And we can get there in 20% of the time that it takes you to get there by hand. (I know you don't believe me. Would you believe the Chairman of the Board of NEC? They did a design using a behavioral synthesis tool and time-to-RTL savings was 80% on a design of 3x complexity -- see: http://videos.dac.com/videos/39th/k1/k1/index.htm -- his key note address at DAC 2002. - "Perhaps you mean Handel-C?" Please excuse the typo - Neither is ideal in my mind. >> I've been thinking about using Handel-C for the next design as it seemed to me to be getting close enough to a reasonable tool to be worth using. - What advantage do you believe that you will have using any C-based flow? Why would you move from VHDL for a language that is not a lot higher-level than RTL? Why do you consider SystemC not close enough to the hardware? What tolerances in QoR (performance or area) would you allow if the product allowed you to save 3+ months in your time-to-RTL? I guess overall, what are your expectations? I am going to be in Munich on Wednesday are you in that area of Germany? And to Mr. Andraka: - I agree with your assessment. I assure you we are not picking low-end designs. - I'm not convinced that this technology lowers the bar for hardware design. "What tools like this do is lower the bar to make it more accessible for those without the expertise." Would you agree that you are less capable than your predecessors (or perhaps yourself) who were creating hardware using schematics just because you use RTL? Using your argument, this would be true although I'm sure this is not the case. Has it really lowered the barrier or increased the ability of the same hardware designers to create more complex designs. Could you do the complex FPGA you are working on right now using schematics -- yes. Could you do it in a reasonable amount of time to make money on the device, no. Let's keep this going, I think it is a healthy discussion... and it lets you guys beat up the marketing guy for a while - I'll be traveling out of country this week so I apologize for any delays in responses. I'd also like to be able to talk to you one on one, please send me contact information if you think this is appropriate. It is often difficult to get all of the thoughts out in an email. Best regards Brett noSPAM-brett@ForteDS.com.NOSPAM "Thomas Stanka" <thomas@stanka-web.de> wrote in message news:d92cdee8.0210062341.5ca2b3f4@posting.google.com... > Xpost without fllw-up2 > > Ray Andraka <ray@andraka.com> wrote: > > beat the target. The real question is whether you are using the device anywhere > > near its capability. As for comparisons, you need to be careful what you are > > comparing it to. There is an astonishing amount of mediocre or worse design > > going on out there. The fact that the average FPGA user only does one F PGA > > every 18-24 months and the tools/devices are changed at a much faster rate than > > that alone says that a large number of the FPGA designs are being done as > > > As I said, there is a place for such tools, but for the most part, it is > > probably not appropriate for something where cost, power or density is an > > issue. What tools like this do is lower the bar to make it more accessible for > > those without the expertise. It is not a replacement for the expertise, just a > > tool that lowers the bar somewhat. > > I used the toolset from Cynapps which is now DSForte for a system > solving 3sat with dedicated HW and SW. > Using the whole set allows you to describe HW in a syntax very near to > VHDL, which I prefered for my part of the job. > The advantage I saw came from better testbench developing using C++ > and faster simulationspeed. Of course thats not what they want to sell > their tools, because testbench development isn't exactly the theme our > management want to buy *g*. > I seldom found this aspect in the discussion traditional HDL vs C/C++ > based. > > I agree with you, that the tools didn't replace expertise for problems > you need expertise to solve. I didn't believe you will ever be able to > squeeze out the design with high-level synthesis. But more and more > you don't need to. No matter to take the next bigger and faster device > [1]. So work could be done using high-level synthesis without wasting > time for details no one cares about. > > > right. Synthesis allows you to get around that where needed. Does this tool > > also allow it? Some of the other HLL tools do not, so they become very awkward > > to make work when you are pushing into the corners of the envelope. > > Thats an interessting point. The version of the high-level synthesizer > I used was a push-and-go. If the result fits it is the best solution > you can get, if not you loose. I don't think thats a matter of > high-level vs low-level synthesis but a matter of tool philosophy. I > had to use Synplify these days (sadly not the full version) and miss > all the switches Synopsys dc_shell would offer. On the other hand you > don't need to have experience to use Synplify, where I needed weeks > before I got first results from Synopsys [2]. > > bye Thomas > > [1] A bit ironically as most of my work consist of squeezing out > smallest FPGA to the max, but in fact thats way I see all around me. > [2] The first time I used Synopsys was hard :). Today I'm experienced > to get some results but still lack the knowlegde to use the full > potential of the tool. > I wonder if ever someone will be able to use 100% of dc_shell if > necessary.Article: 47908
Spam Hater <spam_hater_7@email.com> writes: > I have not heard any good things about version 5 yet. My big worry > stems from the service pack arriving before the product. Isn't this the rule rather than the exception. It happened with 4.1 (or was it two). It also happened with Quartus 2.1. It could be that the real reason is that it takes forever for the software to be shipped here - so close to the North Pole... Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 47909
In article <ans8gm$77g$1@rex.ip-plus.net>, Caillet <regis.caillet@dspfactory.ch> wrote: >To do a ASIC low power, .... 8- Pipeline and parallelize as much as you damn well can. Since P ~= cv^2F, you want to pipeline heavily, then back off the clock, then take advantage of the lower clock but short stages to drop the voltage even further. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 47910
"Arash Salarian" <arash.salarian@epfl.ch> schrieb im Newsbeitrag news:3da1511a$1@epflnews.epfl.ch... > I remember doing a FPGA based project with 10K100E parts from Altera in > QFP208 packages on a two layer board. We had to solder the pins using a > microscope but finally it was running like a charm! Using PROM did not add To solder a 0.5 mm pitch QFP you dont need a microscope. Just place it carefully, then use a big amount of solder on a big tip and flush the pins. Yes, flush them. The solder-flux will make the trick. After removing the unneeded solder with solder sucker, check the pins with a magnifiying glas. -- MfG FalkArticle: 47911
In article <1Yho9.22834$Mw4.9050@nwrddc01.gnilink.net>, Brett Cline <brett@ForteDS.com.NOSPAM> wrote: >- We don't directly have a floor planner nor do we plan to. However, the RTL >code that comes out can go directly to floor planning, logic synthesis, >power estimation, etc. And we can get there in 20% of the time that it takes >you to get there by hand. (I know you don't believe me. Would you believe >the Chairman of the Board of NEC? They did a design using a behavioral >synthesis tool and time-to-RTL savings was 80% on a design of 3x >complexity -- see: http://videos.dac.com/videos/39th/k1/k1/index.htm -- his >key note address at DAC 2002. You might really want to rethink this design decision. The synthesis tools have an amazing awareness of the datapath, after all, they are constructing the datapath itself. The benefits for placing the datapath can range from 10-30% easily (Say it with me "SIMULATED ANNEALING SUCKS!!!"). Simple datapath creation strategies can include placement and create significantly impressive results. EG, see Tim Callahan's research for some possibilities along these lines, http://brass.cs.berkeley.edu/~timothyc/res.html (Oh, by the way, Tim's on the job market) Another thing which is amazingly low hanging but unplucked fruit in the synthesis world: C-slow retiming and automatic repipelining. It's a big BIG win, and not hard to do (nearly trivial if you already have retiming in your flow). You just have to actually have the tools DO it. >And to Mr. Andraka: >Would you agree that you are less capable than your predecessors (or perhaps >yourself) who were creating hardware using schematics just because you use >RTL? Using your argument, this would be true although I'm sure this is not >the case. Considering that Ray Andraka's design flow is "RTL is textually represented gates" and the heavy use of generators in his workflow [1], I'd say otherwise simply because he hasn't given up the detailed specification abilities present in a schematic flow. But that's just my take on it. [1] Generators are very nice when thinking low level, but rather a weakness in Verilog or schematics (where one needs a separate program), although considerably better in VHDL. Generators, on their own, are a bad system for inputing designs, but are an incredibly useful addition as part of the flow, for building most of the modules in a design. I think Xilinx really missed the boat on not makeing CoreGen have a public API for people to use. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 47912
This is off topic for this newsgroup. These numbers usually mean that the minimum drawn channel length of a transistor ist 130nm or 180nm. Sometimes the effective channel length - which is a little shorter - is listed instead. Kolja Sulimma "xtalca" <xtalca@hotmail.com> wrote in message news:<anrbht$gp6u2$1@ID-159866.news.dfncis.de>... > hi all, > all ic manufacturers says that there IC is made of some .13 micron or .18 > micron technology. what exactly this dimension correspond to ?Article: 47913
Have you taken a look at Actels ProASIC PLUS family? This is a FLASH-based architecture ranging from 75K-1M system gates. Tim "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:ansf0o$guqi1$1@ID-84877.news.dfncis.de... > "Arash Salarian" <arash.salarian@epfl.ch> schrieb im Newsbeitrag > news:3da1511a$1@epflnews.epfl.ch... > > I remember doing a FPGA based project with 10K100E parts from Altera in > > QFP208 packages on a two layer board. We had to solder the pins using a > > microscope but finally it was running like a charm! Using PROM did not add > > To solder a 0.5 mm pitch QFP you dont need a microscope. Just place it > carefully, then use a big amount of solder on a big tip and flush the pins. > Yes, flush them. The solder-flux will make the trick. After removing the > unneeded solder with solder sucker, check the pins with a magnifiying glas. > > -- > MfG > Falk > > > >Article: 47914
Hi there, I am currently undertaking project in my spare time involving string matching/similarity on FPGA's - more specifically on a Virtex based PCI card. I've been researching for a while know - and it appears to be a massive area and quite a popular application for FPGA's. I would like to do something original, but there seems to be so much material already covered. One thing I haven't seen done (or at least I think) is an implementation of the BNDM algorithm, which is supposedly 10 - 40% faster than the boyer-moore method. I'm trying to look at algorithims which would benefit from being able to perfrom several comparsisons in parallel. A lot of search strategies would require run time configuration of the FPGA, as presented in the two papers by Sidhu and Prasanna - which I guess would be quite difficult on a Virtex. If anyone has some ideas or any info on new investigations I would be very appreciative. Many Thanks, JohnArticle: 47915
itsme wrote: > > Hi, > I think my problem is caused by XST vhdl compiler. > I found in the FPGA Editor that the Register which should be > placed in the IOB has a feedback. So it can't be > moved in the IOB. > > In my VHDL code I have some conditional assignments > to the output signal and in some cases it should hold > its old value. > How can I tell the XST not to use the output of > a register also as input? > It should rather use the ClockEnable auf the Register. > I thought the XST Option - Pack I/O Registers into IOBs > will do that. This can be a tough one. There should be guidelines on how to encourage XST to use the clock enable. But if the entire logic block fits into a single LUT, it may not want to use the CE since that would use an extra LUT. In the end you may need to use a pair of FFs, one in the IOB and one in a CLB. You can design the combinatorial logic separate from the sequential logic so that both FFs use the same combinatorial signal as the D input to the FF. Then only the CLB FF will need to be used for the feedback and the other FF can be pushed into the IOB. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47916
When you make the *default* assignment to 0 for P_DR_BANK(0), you are removing the "hold last value" states. So P_DR_BANK(0) no longer needs feedback. But this will make the logic go to a '0' in any case where you do not make an assignment. Obviously this is a different function than the one you had. Make an internal function, P_DR_BANK_INTRNL and use it as a register. Define your logic to its D inputs separately as combinatorial logic explicitly indicating when it should hold the "old" value with an assignment to itself. Then make the same register definition for P_DR_BANK. I think you will find that P_DR_BANK can be pushed into IOBs since P_DR_BANK_INTRNL is the one providing the feedback. itsme wrote: > > Hello, > here is my little "test design" > All I want is that all Outputs P_DR_BANK are packed into registers of an IOB > in a Virtex2. > However all Outputs are Registers only P_DR_BANK(0) is mapped in a IOB > register. > P_DR_BANK(1) uses a Slice FF. > I found in the FPGA Editor that the Register which should be > placed in the IOB has a feedback. So it can't be > moved in the IOB. > > In my VHDL code (see below) I have some conditional assignments > to the output signal and in some cases it should hold > its old value. > How can I tell the XST not to use the output of > a register also as input? > It should rather use the ClockEnable auf the Register which is > also available in IOBs. > I thought the XST Option - Pack I/O Registers into IOBs > will do that. > > please help > peter > > ---------------------------------------------------------------------- > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity TEST_OUT_FF is > Port ( CLK: in std_logic; > REQUEST: in std_logic; > > --- PAD Signals, should be in IOB Register > P_DR_BANK : out STD_LOGIC_VECTOR (1 DOWNTO 0) > > ); > end TEST_OUT_FF; > > architecture Behavioral of TEST_OUT_FF is > > ------------------------------------------------------- > ---------------------------------- State machine > type STATE_TYPE is (S_Idle, S_Active, S_Access); > > signal State: STATE_TYPE; > > BEGIN > ---------Statemachine > FSM:process(CLK) > begin > if Clk'event and clk='1' then > > P_DR_Bank(0)<='0'; -- Use this to get Register in IOB !! Why? > -- P_DR_Bank(1) with no IOB Reg!! > case State is > ------------------ > when S_Idle => > if Request='1' then > State <= S_Active; > end if; > > ------------------- > when S_Active => > P_DR_Bank <= "10"; > State <= S_Access; > > ------------------- > when S_Access => > P_DR_Bank <= "01"; > State <= S_Idle; > > when others => > State <= S_Idle; > > end case; > end if; -- CLK > end process; > > end Behavioral; -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47917
In article <ansipn$d93$1@newsg4.svr.pol.co.uk>, J.Curtis <john@curt02.freeserve.co.uk> wrote: >A lot of search strategies would require run time configuration of the FPGA, >as presented in the two papers by Sidhu and Prasanna - which I guess would >be quite difficult on a Virtex. Try looking for/developing matchers where the string being matched against can entirely be specified/specialized in the contents of fixed LUTs. This enables you to use SRL16s on teh Virtex to load in new contents. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 47918
Spam Hater wrote: > > Hi Tony, > > This is probably not the answer you want, but... > See if you can find a copy of version 4.1. > > I have not heard any good things about version 5 yet. My big worry > stems from the service pack arriving before the product. > > SH7 It seems especically odd that they would provide a service pack along with a new release of the software. Why wouldn't they just bump up the version to 5.2i so you don't have to download the SP? And what's up with the durn x.x"i" thing anyway, didn't they add the i about 4 years ago to indicate "internet capable"? Hasn't it lost its significance by now and can be dropped??? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47919
This is the CMOS process technology used to manufacture that part. Specifically it is the effective gate length of the transistors that make up all the circuitry on the die. Regards "xtalca" <xtalca@hotmail.com> wrote in message news:<anrbht$gp6u2$1@ID-159866.news.dfncis.de>... > hi all, > all ic manufacturers says that there IC is made of some .13 micron or .18 > micron technology. what exactly this dimension correspond to ?Article: 47920
You can use the same approach. First you take the algorithm and ask your self "If I wanted to do this algorithm and I knew the data I was to use how could I reduce the circuit?" Most often you'll end up PE's that are a few registers and a few lookup tables worth of logic. Then ask your self "Is there a way to make each PE so all I have to do is chage the lookup table but keep everything else the same for each different string I want to find?" Once you boil it down to just lookup tables you can create a design that can be updated through the select map interface using partial reconfiguration. Steve "J.Curtis" <john@curt02.freeserve.co.uk> wrote in message news:ansipn$d93$1@newsg4.svr.pol.co.uk... > Hi there, > I am currently undertaking project in my spare time involving string > matching/similarity on FPGA's - more specifically on a Virtex based PCI > card. I've been researching for a while know - and it appears to be a > massive area and quite a popular application for FPGA's. > > I would like to do something original, but there seems to be so much > material already covered. One thing I haven't seen done (or at least I > think) is an implementation of the BNDM algorithm, which is supposedly 10 - > 40% faster than the boyer-moore method. > I'm trying to look at algorithims which would benefit from being able to > perfrom several comparsisons in parallel. > > A lot of search strategies would require run time configuration of the FPGA, > as presented in the two papers by Sidhu and Prasanna - which I guess would > be quite difficult on a Virtex. > > If anyone has some ideas or any info on new investigations I would be very > appreciative. > > Many Thanks, > John > >Article: 47921
I just downloaded the eval of ChipScope, and intend to evaluate it on my Toshiba laptop. In common with many modern laptops, this machine does not have a parallel port. I intend to buy the Keyspan port replicator (USB to serial/parallel) but want to ensure it'll work first. Anybody here used it with success? If not, any other suggestions? Thanks PeteArticle: 47923
No it's not the "effective gate length", its the "drawn gate length".
As the original poster can probably see by now, there never has
been total agreement on this question. The most widely accepted
definition is as I have stated, the "drawn gate length". But,
there are certain manufacturers who from time-to-time like to
spout-off that they have the most advanced technology... then
they give you the "effective channel length".
Definitions:
Drawn Dimensions
- what the design rules tell you, and what you draw in the layout.
Mask Dimensions
- what ends up physically on the mask, after some size adjustments
to compensate for fabrication.
(there are manufacturing variations involved)
Physical Dimensions
- what ends up on the wafer
(more manufacturing variations here too)
Effective Channel Length
- what an electron (or hole) sees... after processing, including
the shortening of the channel due to depletion around the S/D.
(that's what it's been called for the last 25 years at least)
When in doubt, ask... is that the drawn dimension or the physical
gate length? They are usually pretty close. Don't ever accept
the effective channel length dimension.
Jay wrote:
> This is the CMOS process technology used to manufacture that part.
> Specifically it is the effective gate length of the transistors that
> make up all the circuitry on the die.
>
> Regards
>
> "xtalca" <xtalca@hotmail.com> wrote in message news:<anrbht$gp6u2$1@ID-159866.news.dfncis.de>...
>
>>hi all,
>> all ic manufacturers says that there IC is made of some .13 micron or .18
>>micron technology. what exactly this dimension correspond to ?
>>
Article: 47924
It also helps to take into account what else needs to be done in the device. A
DSP, for example might handle the filter fine, but then add in perhaps a
demodulator, the update mechanism and some other stuff, and now it may no longer
fit on a DSP. For very low sample rates (eg, audio samples), it often is more
advantageous to use a multiplier and block rams instead of attempting to do it
with distributed arithmetic. For example, one can use a pair of block rams (one
for coefficient store, one for sample delay) and a pair of accumulators (one
connected as a scaling accumulator multiplier) to get a very effective FIR
filter in a very small amount of chip resources. We do that for the audio
filters at the back end of our FPGA shortwave radio demo.
Falk Brunner wrote:
> > implement FIR for one input channel, do I need to prepare another 99
> > pairs LUTs and adders for 99 input channels FIR ?
>
> If you go this way, yes. But at such low sampling rates, its a good idea to
> do some multiplexing, means runn your DSP core at a high clock rate and use
> one MAC unit for multiple channels.
>
> > And how to update those LUTs after calculating the errors?
>
> There are many ways. You could use the LUTs a dual port distributed RAM. One
> port is for updating the coefficients, one for read access by the DSP
> engine.
>
> But again. Do a estimation on data throughput (sample rate, bit width of
> samples), estimate the number of operations needed to recalculate the
> coefficients, estimate the number of operations neede for the filter itself.
> Then compare this to common available DSP. THEN it is time to think about
> using a FPGA or DSP.
> --
> MfG
> Falk
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z