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"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:y4%m9.1568$pk1.28677390@newssvr21.news.prodigy.com... > This is a bit far fetched, but might work very nicely for your application. > Have you thought of using DVI I/O chips? DVI is a relatively recent > connectivity methodology for computer displays. It is, in escence, > serialized 8 bit RGB. A single link can deliver in the order of 5 or 6 > Gigabits per second, if I recall. The chips (both TX and RX) are less than > ten bucks a piece. You can certainly clock DVI at less then the max single > link 165 MHz rate and transport your data to via a serial link. I think the > chips will go down to 25 MHz clocking. At low data rates you can probably > go many more feet than the standard provides for. Heck, you could have > three redundant links delivered over a commodity cable. > > Anyhow, just a thought. Check out the Silicon Image site for more details: > http://www.siimage.com/home.asp > > > HTH, > > > -- > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > > > "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message > news:anctr2$2brl$1@msunews.cl.msu.edu... > > Hello, > > I am developing an instrument that is currently communicating over a > > special high speed parallel board. The data rate is 6.4 million 8 bit > words > > per second. The board works great but it costs in excess of $1600 US per > > copy. It also occupies a full sized PCI slot. We are considering > > implementing an alternative I/O arrangement such as USB2 or ethernet > > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some > > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or if > > absolutely necessary, Virtex2). > > > > Thanks, > > Theron > > > > > > Ideally, I need something with a standard port in a typical PC. Otherwise, I can't get rid of the $1600 data card. I realize that USB2 is still new and not every PC has one but at least you can go to most any computer store and get one. Does the same apply to DVI? What is the typical cost? Thanks for the advice, Theron HicksArticle: 47951
"Ray Andraka" <ray@andraka.com> wrote in message
news:3DA21E5F.8DD5ED3@andraka.com...
> A while back we considered USB in the FPGA, but when push came to shove,
it was
> cheaper to use an external USB chip. In our case, it was the original
USB, and
> we used a National Semi chip, I think it was a USBN9603 which has both the
> controller and the PHY in one package for about $2.25. When we sized the
USB
> for putting in the FPGA we still needed an external PHY, and it would have
> pushed us into a larger part costing far more than the off the shelf chip.
I
> don't know if the situation is similar for USB2 or not, although I suspect
that
> it is.
>
Ray,
I am beginning to think along the same lines. The chips are about the
same price ($2 to $3 or so) and the USB2 chip is proven. Why re-invent the
wheel, especially when the quantities are so low. Just for grins I priced a
USB2 core from MEMIC and the cost for net list only, was $30000. Then it
takes about 1500 slices to implement it. That would more than quadruple the
gate count on that particular card and we aren't using all that in the first
place.
Has anyone tried out any of the new USB2 chips? Any comments on support and
availability for the small guy? (10 to 12 systems a year or less
initially...) Even experience with USB1 would be of interest as I am
uncertain as to exactly what I might be getting into in terms of degree of
complexity.
Thanks,
Theron
> Theron Hicks wrote:
>
> > Hello,
> > I am developing an instrument that is currently communicating over a
> > special high speed parallel board. The data rate is 6.4 million 8 bit
words
> > per second. The board works great but it costs in excess of $1600 US
per
> > copy. It also occupies a full sized PCI slot. We are considering
> > implementing an alternative I/O arrangement such as USB2 or ethernet
> > (TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some
> > other FPGA friendly technology? Note: target FPGA is a Spartan2E (or
if
> > absolutely necessary, Virtex2).
> >
> > Thanks,
> > Theron
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
>
>
Article: 47952In article <3DA28D5A.4040305@ee.duth.gr>, Kostas Siozios <ksiop@ee.duth.gr> wrote: >Hi, i am trying to implement a simple algorithm into a FPGA. > >I intent to use A C A D E M I C C A D T O O L S. Already i have >found available tools from the UCLA and from Toronto FPGA Reseach group. > >The main dissadvantage for both of them is that they don't have full >design flow. I mean that they don't have synthesizer and bitstream >generator. Not to mention they tend to be designed for experimentation, and therefore use an abstract FPGA model. >I would like to know if anyone has found any fpga tools, apart of two >that mentioned above, that could help me. >The tools must be based on O P E N S O U R C E. What are you trying to accomplish? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 47953
The description of ModelSim for (Xilinx) ISE specifically states that this is not possible. (Probably a licensing issue with Mentor.) I would be very interested if someone could figure out a -legitimate- way around it. SH7 On Tue, 8 Oct 2002 17:18:48 +0200, "Nico Toender" <n.toender@tuhh.de> wrote: >Hi! > >Does anyone have experiences with above topic in ISE 4.x or 5.x? > >How about simulation with ModelSim? > > >Thanks very much! > Nico >Article: 47954
I am wondering how to set flipflop values on initialization, using a Xilinx CoolRunnerXPLA3 CPLD. I read that I can enter them in the constraints file, but if I don't, what will they be? Do they default to 0?Article: 47956
Hi, I was hoping someone would be able to enlighten me on working around the problem of clock routing to the output pads in Virtex 2. I have two IOBs in one tile and there are three clocks. One IOB has a regular OFF driven by one clock, the other has a ddrff to realize a 50% duty cycle driven by two clocks different from the other clock. My clocking scheme at present is //clk_in --> ibufg -+--> dcm_int clk0 --> bufg -----> clk_in // | // +--> dcm_ext -+-> clk0 ----> bufg --> clkExtP --+ // | | // | V // | ddrff-->clk_out // | ^ // | | // +-> clk180 --> bufg --> clkExtN --+ I would appreciate your feedback. Thank you. -sanjay I get following error - ERROR:Place:1721 - The current designer locked placement of the IOBs write_out and clk_out makes this design unroutable due to a physical routing limitation. This device has a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction means that these pairs of pins must be driven by the same signal or one of the signals will be unroutable. Before continuing with this design please unlock or move one of these IOBS to a new location.Article: 47957
> > "Theron Hicks" <hicksthe@egr.msu.edu> > Ideally, I need something with a standard port in a typical PC. Otherwise, > I can't get rid of the $1600 data card. I realize that USB2 is still new > and not every PC has one but at least you can go to most any computer store > and get one. Does the same apply to DVI? What is the typical cost? The DVI approach wouldn't work then. You'd need a custom card on the PC. I misunderstood and thought that you could consider this sort of an approach. Your 6.4 million bytes per second rate pretty much limits your options if you are looking for standard interfaces. USB2 might just be the most sensible way to go. I'd opt for an external USB2 device as oppose to an FPGA implementation. Is your 6.4 MB/s rate a continuous rate or a maximum burst rate? -- Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 47958
Michael Tornow wrote:
> Do you know an arithmetik vhdl-library, where pipelining is available?
> My work is in the early beginning(proof of concept) I don't want to waste
> time with writing arithmetik function for something that maybe dosen't fit
> to my problem...
For proof of concept, just use use ieee.numeric_std.all
operators and add a reasonable number of pipeline levels.
Leo can actually optimize this sort of thing for multiplies.
-- Mike Treseler
Article: 47959Why can’t Xilinx Software be as good as Altera Software? I am an independent consultant developing FPGAs and PLDs using both Xilinx and Altera development software. My clients usually have a preference between Altera and Xilinx. From a hardware perspective, I can do most designs just as well with either part. I just wish that Xilinx could produce development tools that are as a good as those provided by Altera. The Altera tools are such a pleasure to use. The tools are very well integrated into a single Windows program. They have a consistent user across the toolset. Any time an error occurs, a single click brings you to the source of the error. The help files provide useful information. The Xilinx toolset is a hodgepodge of command line tools with a lousy user interface on top of it. The tools don’t talk to each other, the error handling is terrible and the help files are useless. An analogy comes to mind. I would compare the Altera software to a sports car and the Xilinx to a donkey. Both modes of transportation will get you where you want to go. The sports car has an enjoyable ride. The donkey gets you there eventually, but the ride stinks. Here are a few (there are many more) of the typical problems I see when using Xilinx ISE: 1) When an error comes up, it usually has a non-descriptive name. If I double click on the error, most of the time it does not show the source of the error. 2) If it does show me the error, it is usually at some intermediate code, not at the source. For example, if there is a section of the design done in schematic capture, the program will show a VHDL file with an error, rather than pulling up the schematic and showing the source of the error. 3) Sometimes the error message will say that something is off grid (Error point not on primary grid) on the schematic at x=1608 y=1504 and expect me to open the schematic and hunt for the X,Y location. If the program knows the location, it should be able to open the schematic and highlight the error for me. 4) The schematic program has an error checker (Tool| Check Schematic) to help find errors in the schematic. After it you correct them you can run the tool again. Many times it will still show at least one error after all of them have been fixed. If you exit the schematic program, then reopen the schematic, and run the error checker it will show no errors. 5) Since the Xilinx Project Navigator is just a collection of separate programs and third party utilities, they each have a different user interface. Each program requires different keystrokes to do the same thing. For example, in the Schematic program, Zoom-in is F8, in the State Cad program it is CTL+PgUp, in ChipView (F7). 6) Options have to be set within many different separate programs. To set some options you may have to click on the Synthesizer, than the Fitter, then the Program file generator. 7) Sometimes when you edit the pins assignments, save them in Chipview, and then try to recompile the design nothing happens. You have to remember that as long as Chipview is open, the Project Navigator will ignore you and not show any reason why. (Oh yeah, I have to close that program before it will respond). 8) Once you close the program (and you have a file viewed in the main Navigator pane) it still fails to respond. This is because there is a “NOTICE” dialog box asking you if want use the changes you just made. However, this dialog box is not visible on the screen. It is hidden behind the other windows because the programmers failed to make it a global modal dialog box. The only indication (other than Navigator stops responding) is A Notice window on the Windows taskbar at the bottom of the screen. 9) I try to run the included ModelSim simulator. The ModelSim splash screen comes up but nothing happens. The program doesn’t start. The Project Navigator shows no error. After much wasted time, I find that the license for the simulator is tied to the IP address of the computer it is used on. Since I was using a laptop, its IP address depends on where it is plugged in. So I need a license for each IP address my laptop uses. There was no error message (How about “Invalid License!”) from Navigator or ModelSim. This is poor software integration. There are just a few examples of the types of problems that users have to live with. The Xilinx software is certainly usable and I have done many designs with it. It just makes things much harder than they should be. As a consultant, I appreciate well written tools save me time and my clients money. The Xilinx tools are poorly written and integrated. It has been like this for years. The new release (5.1) is not much better. Maybe if you have the major market share like Xilinx does, you don’t have to care about the developers. Many Xilinx users have never tried the Altera software and don’t know what they are missing. The Altera tools have a consistent interface and were written to run in a Windows environment. They have an intuitive feel. The utilities are so well written that you never leave the main program to run them. They all look like part of the same program. There are no programs to open and close in the right sequence. The errors codes give meaningful descriptions. More detailed descriptions can be found be clicking on the help button. Double clicking on an error brings you back to the actual source of the error! All of the options are set within the one main program. I have no interest in encouraging people to use Altera over Xilinx. I want Xilinx to write software that is as good as Altera’s. Since I use both packages, I would rather see Xilinx take the challenge and improve their tools. BobArticle: 47960
Bob, <snip> I am a Xilinx user and I haven't tried Altera software (due to the fact that I only have Xilinx devices!). Why do you think Xilinx does have the major market share? If hardware implementations on FPGA continue to start being developed from a software perspective (Handel-C, System-C etc.), do you think Xilinx will retain their dominance given that software developers (who will apparently eventually being writing software that ends up directly on hardware (!) -) ) are used to advanced, slick GUIs such as Microsoft Visual Studio etc.? Won't they prefer Alteras software then and if designs can be done on either Xilinx or Altera - why not choose the tool they feel most comfortable with? Or will hardware advantages still be the most important factor? I think I remmber Ray Andraka (http://www.andraka.com/) saying (apologies if I am wrong) that he puts Xilinx slightly over Altera for DSP designs due to the so useful SRL16 elements - DSP on FPGA is very much going to explode over the next decade I believe - will DSP related features determine who gets the biggest market share? I don't have your frame of reference to compare the Xilinx tools with their Altera equivalents but I know that I sometimes feel that the tools don't really want to talk to me that much and would rather just be left alone rather than be made to produce bitstreams and provide a pleasant development experience - sort of like a grumpy old man that lives in a cave. Thanks for the post - good to hear real experiences. Cheers, Ken > Maybe if you have the major market share like Xilinx > does, you don't have to care about the developers. Many Xilinx users > have never tried the Altera software and don't know what they are > missing. > > I have no interest in encouraging people to use Altera over Xilinx. I > want Xilinx to write software that is as good as Altera's. Since I use > both packages, I would rather see Xilinx take the challenge and > improve their tools. --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.394 / Virus Database: 224 - Release Date: 03/10/2002Article: 47961
I agree with all of your statements. The new ISE IDE is also worse than the old Foundation IDE. As a special gift, xilinx doesn' t support the synopsys fpga compiler which is a rocket compared to the xilinx synthesis tool. Of course we can use Synplify, but each compiler has its own life. I liked to work with fpga express. The xilinx compiler also has lots of bugs and is not able to handle large projects. And the spartan (4000 architecture) devices aren' t supported any more. I use them in lots of boards with flash size limited microcontrollers for configuration. Furthermore a xilinx FAE told me that the fpga editor also died because of a canceled contract with the manufacturer. This is a core tool which is a must for fast verification of correct synthesis etc. XILINX your chips are the best, but the SW needs lots of improvements ! MIKE "Bob W" <fa@_NO_SPAM_AskTheOracle.com> schrieb im Newsbeitrag news:n096qu88m768a2n6eb5u30b7n8oq1ratkr@4ax.com... > Why can't Xilinx Software be as good as Altera Software? > > I am an independent consultant developing FPGAs and PLDs using both > Xilinx and Altera development software. My clients usually have a > preference between Altera and Xilinx. From a hardware perspective, I > can do most designs just as well with either part. I just wish that > Xilinx could produce development tools that are as a good as those > provided by Altera. > > The Altera tools are such a pleasure to use. The tools are very well > integrated into a single Windows program. They have a consistent user > across the toolset. Any time an error occurs, a single click brings > you to the source of the error. The help files provide useful > information. > > The Xilinx toolset is a hodgepodge of command line tools with a lousy > user interface on top of it. The tools don't talk to each other, the > error handling is terrible and the help files are useless. An analogy > comes to mind. I would compare the Altera software to a sports car and > the Xilinx to a donkey. Both modes of transportation will get you > where you want to go. The sports car has an enjoyable ride. The donkey > gets you there eventually, but the ride stinks. > > Here are a few (there are many more) of the typical problems I see > when using Xilinx ISE: > > 1) When an error comes up, it usually has a non-descriptive name. If I > double click on the error, most of the time it does not show the > source of the error. > > 2) If it does show me the error, it is usually at some intermediate > code, not at the source. For example, if there is a section of the > design done in schematic capture, the program will show a VHDL file > with an error, rather than pulling up the schematic and showing the > source of the error. > > 3) Sometimes the error message will say that something is off grid > (Error point not on primary grid) on the schematic at x=1608 y=1504 > and expect me to open the schematic and hunt for the X,Y location. If > the program knows the location, it should be able to open the > schematic and highlight the error for me. > > 4) The schematic program has an error checker (Tool| Check Schematic) > to help find errors in the schematic. After it you correct them you > can run the tool again. Many times it will still show at least one > error after all of them have been fixed. If you exit the schematic > program, then reopen the schematic, and run the error checker it will > show no errors. > > 5) Since the Xilinx Project Navigator is just a collection of separate > programs and third party utilities, they each have a different user > interface. Each program requires different keystrokes to do the same > thing. For example, in the Schematic program, Zoom-in is F8, in the > State Cad program it is CTL+PgUp, in ChipView (F7). > > 6) Options have to be set within many different separate programs. To > set some options you may have to click on the Synthesizer, than the > Fitter, then the Program file generator. > > 7) Sometimes when you edit the pins assignments, save them in > Chipview, and then try to recompile the design nothing happens. You > have to remember that as long as Chipview is open, the Project > Navigator will ignore you and not show any reason why. (Oh yeah, I > have to close that program before it will respond). > > 8) Once you close the program (and you have a file viewed in the main > Navigator pane) it still fails to respond. This is because there is a > "NOTICE" dialog box asking you if want use the changes you just made. > However, this dialog box is not visible on the screen. It is hidden > behind the other windows because the programmers failed to make it a > global modal dialog box. The only indication (other than Navigator > stops responding) is A Notice window on the Windows taskbar at the > bottom of the screen. > > 9) I try to run the included ModelSim simulator. The ModelSim splash > screen comes up but nothing happens. The program doesn't start. The > Project Navigator shows no error. After much wasted time, I find that > the license for the simulator is tied to the IP address of the > computer it is used on. Since I was using a laptop, its IP address > depends on where it is plugged in. So I need a license for each IP > address my laptop uses. There was no error message (How about "Invalid > License!") from Navigator or ModelSim. This is poor software > integration. > > There are just a few examples of the types of problems that users have > to live with. The Xilinx software is certainly usable and I have done > many designs with it. It just makes things much harder than they > should be. As a consultant, I appreciate well written tools save me > time and my clients money. The Xilinx tools are poorly written and > integrated. It has been like this for years. The new release (5.1) is > not much better. Maybe if you have the major market share like Xilinx > does, you don't have to care about the developers. Many Xilinx users > have never tried the Altera software and don't know what they are > missing. > > The Altera tools have a consistent interface and were written to run > in a Windows environment. They have an intuitive feel. The utilities > are so well written that you never leave the main program to run them. > They all look like part of the same program. There are no programs to > open and close in the right sequence. The errors codes give meaningful > descriptions. More detailed descriptions can be found be clicking on > the help button. Double clicking on an error brings you back to the > actual source of the error! All of the options are set within the one > main program. > > I have no interest in encouraging people to use Altera over Xilinx. I > want Xilinx to write software that is as good as Altera's. Since I use > both packages, I would rather see Xilinx take the challenge and > improve their tools. > > BobArticle: 47962
Hi; Thanks for reading this. I have a schematic (top level) design which has a data bus. This data bus has had IOB(63:0) and separate Ibuf(63:0) and OBUF(63:0) attached to an IO marker (bidirectional) and NOTHING else in the schematic. I get an error on synthesis that says: Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <bcpm_top> on signal <data_obuf_15> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <bcpm_top> on signal <data_obuf_14> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <bcpm_top> on signal <data_obuf_13> not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit <bcpm_top> on signal <data_obuf_12> not replaced by logic Signal is stuck at GND Anybody seen this error??? I am using primitives and not macros for the IOBufs Also I had created this schematic under 4.1 and foolishly upgraded to take "advantage" 5.1... the schematic synthed and routed fine under 4.1 Any Ideas??? Thanks; C.W. ThomasArticle: 47963
Hi Bob,
I use Xilinx Webpack and also use a laptop and have never had any
problem with modelsim.
The licence is hard drive locked but is free so is not a problem.
Regarding the "bugs" you have also mentioned,
I am a relative novice with programmable logic but the benefits greatly
outweigh using discrete logic.
I have had a reasonable response from the apps engineers at Xilinx when
I have encountered problems.
Having been a schematic user with Lattice and now Verilog with Xilinx,
the software transition was painless.
What advantages are there in using Altera hardware over Xilinx?
What are the comparative costs of Silicon?
In my department, the cost of the software outweighs the value of the
silicon.
Unfortunately, time wasted is sometimes ignored in this equation!!
Regards
Dave
"Bob W" <fa@_NO_SPAM_AskTheOracle.com> wrote in message
news:n096qu88m768a2n6eb5u30b7n8oq1ratkr@4ax.com...
> Why can't Xilinx Software be as good as Altera Software?
>
>
> 9) I try to run the included ModelSim simulator. The ModelSim splash
> screen comes up but nothing happens. The program doesn't start. The
> Project Navigator shows no error. After much wasted time, I find that
> the license for the simulator is tied to the IP address of the
> computer it is used on. Since I was using a laptop, its IP address
> depends on where it is plugged in. So I need a license for each IP
> address my laptop uses. There was no error message (How about "Invalid
> License!") from Navigator or ModelSim. This is poor software
> integration.
>
>
> Bob
Article: 47964I'm user of Altera by chance. After having spent 3 weeks or so with MaxPlus2 and countless calls to the support line plus a multiday course I'was somewhat comfortable with their tools, MaxPlus2 and now Quartus. From a developpers point of view they're lacking the last edge of intuitivity. They could be made much simpler to operate. I was never tempted to spend another 3 weeks to become comfortable with Xilinx or Cypress. Their silicon appears to be too similar. Plus, the next time I have a look at these technologies, there is a whealth of new families and devices. To me, the ease of use is paramount. I may not have a look at that stuff for months, and then have to do a project immediately. I cannot read manuals to become comfortable again. It has to be sufficiently intuitive to be used. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net Bob W wrote: > Why can’t Xilinx Software be as good as Altera Software? > > I am an independent consultant developing FPGAs and PLDs using both > Xilinx and Altera development software. My clients usually have a > preference between Altera and Xilinx. From a hardware perspective, I > can do most designs just as well with either part. I just wish that > Xilinx could produce development tools that are as a good as those > provided by Altera. > > The Altera tools are such a pleasure to use. The tools are very well > integrated into a single Windows program. They have a consistent user > across the toolset. Any time an error occurs, a single click brings > you to the source of the error. The help files provide useful > information. < snip >Article: 47965
Hi Mike, I will not go into detail between Altera and Xilinx SW tools since I'm biased, not because of that I work for xilinx but because I have used Altera tools very little. But I know that the FPGA_Editor is still in ISE 5.1 and I don't know of any plans to remove it. Göran Bilski "Mike R." wrote: > I agree with all of your statements. > The new ISE IDE is also worse than the old Foundation IDE. > As a special gift, xilinx doesn' t support the synopsys fpga compiler which > is a rocket compared to the xilinx synthesis tool. > Of course we can use Synplify, but each compiler has its own life. I liked > to work with fpga express. > The xilinx compiler also has lots of bugs and is not able to handle large > projects. > And the spartan (4000 architecture) devices aren' t supported any more. I > use them in lots of boards with flash size limited microcontrollers for > configuration. > Furthermore a xilinx FAE told me that the fpga editor also died because of a > canceled contract with the manufacturer. This is a core tool which is a must > for fast verification of correct synthesis etc. > > XILINX your chips are the best, but the SW needs lots of improvements ! > > MIKE > > "Bob W" <fa@_NO_SPAM_AskTheOracle.com> schrieb im Newsbeitrag > news:n096qu88m768a2n6eb5u30b7n8oq1ratkr@4ax.com... > > Why can't Xilinx Software be as good as Altera Software? > > > > I am an independent consultant developing FPGAs and PLDs using both > > Xilinx and Altera development software. My clients usually have a > > preference between Altera and Xilinx. From a hardware perspective, I > > can do most designs just as well with either part. I just wish that > > Xilinx could produce development tools that are as a good as those > > provided by Altera. > > > > The Altera tools are such a pleasure to use. The tools are very well > > integrated into a single Windows program. They have a consistent user > > across the toolset. Any time an error occurs, a single click brings > > you to the source of the error. The help files provide useful > > information. > > > > The Xilinx toolset is a hodgepodge of command line tools with a lousy > > user interface on top of it. The tools don't talk to each other, the > > error handling is terrible and the help files are useless. An analogy > > comes to mind. I would compare the Altera software to a sports car and > > the Xilinx to a donkey. Both modes of transportation will get you > > where you want to go. The sports car has an enjoyable ride. The donkey > > gets you there eventually, but the ride stinks. > > > > Here are a few (there are many more) of the typical problems I see > > when using Xilinx ISE: > > > > 1) When an error comes up, it usually has a non-descriptive name. If I > > double click on the error, most of the time it does not show the > > source of the error. > > > > 2) If it does show me the error, it is usually at some intermediate > > code, not at the source. For example, if there is a section of the > > design done in schematic capture, the program will show a VHDL file > > with an error, rather than pulling up the schematic and showing the > > source of the error. > > > > 3) Sometimes the error message will say that something is off grid > > (Error point not on primary grid) on the schematic at x=1608 y=1504 > > and expect me to open the schematic and hunt for the X,Y location. If > > the program knows the location, it should be able to open the > > schematic and highlight the error for me. > > > > 4) The schematic program has an error checker (Tool| Check Schematic) > > to help find errors in the schematic. After it you correct them you > > can run the tool again. Many times it will still show at least one > > error after all of them have been fixed. If you exit the schematic > > program, then reopen the schematic, and run the error checker it will > > show no errors. > > > > 5) Since the Xilinx Project Navigator is just a collection of separate > > programs and third party utilities, they each have a different user > > interface. Each program requires different keystrokes to do the same > > thing. For example, in the Schematic program, Zoom-in is F8, in the > > State Cad program it is CTL+PgUp, in ChipView (F7). > > > > 6) Options have to be set within many different separate programs. To > > set some options you may have to click on the Synthesizer, than the > > Fitter, then the Program file generator. > > > > 7) Sometimes when you edit the pins assignments, save them in > > Chipview, and then try to recompile the design nothing happens. You > > have to remember that as long as Chipview is open, the Project > > Navigator will ignore you and not show any reason why. (Oh yeah, I > > have to close that program before it will respond). > > > > 8) Once you close the program (and you have a file viewed in the main > > Navigator pane) it still fails to respond. This is because there is a > > "NOTICE" dialog box asking you if want use the changes you just made. > > However, this dialog box is not visible on the screen. It is hidden > > behind the other windows because the programmers failed to make it a > > global modal dialog box. The only indication (other than Navigator > > stops responding) is A Notice window on the Windows taskbar at the > > bottom of the screen. > > > > 9) I try to run the included ModelSim simulator. The ModelSim splash > > screen comes up but nothing happens. The program doesn't start. The > > Project Navigator shows no error. After much wasted time, I find that > > the license for the simulator is tied to the IP address of the > > computer it is used on. Since I was using a laptop, its IP address > > depends on where it is plugged in. So I need a license for each IP > > address my laptop uses. There was no error message (How about "Invalid > > License!") from Navigator or ModelSim. This is poor software > > integration. > > > > There are just a few examples of the types of problems that users have > > to live with. The Xilinx software is certainly usable and I have done > > many designs with it. It just makes things much harder than they > > should be. As a consultant, I appreciate well written tools save me > > time and my clients money. The Xilinx tools are poorly written and > > integrated. It has been like this for years. The new release (5.1) is > > not much better. Maybe if you have the major market share like Xilinx > > does, you don't have to care about the developers. Many Xilinx users > > have never tried the Altera software and don't know what they are > > missing. > > > > The Altera tools have a consistent interface and were written to run > > in a Windows environment. They have an intuitive feel. The utilities > > are so well written that you never leave the main program to run them. > > They all look like part of the same program. There are no programs to > > open and close in the right sequence. The errors codes give meaningful > > descriptions. More detailed descriptions can be found be clicking on > > the help button. Double clicking on an error brings you back to the > > actual source of the error! All of the options are set within the one > > main program. > > > > I have no interest in encouraging people to use Altera over Xilinx. I > > want Xilinx to write software that is as good as Altera's. Since I use > > both packages, I would rather see Xilinx take the challenge and > > improve their tools. > > > > BobArticle: 47966
"valentin tihomirov" <valentin@abelectron.com> wrote in message news:<3da19c61$1_2@news.estpak.ee>... > Thank you for response. > I've seen this schematic before, you reffered me to, but I can't understand > the PROG signal. It seems that when it is active, it must pull TDO to 0, > right? When PROG is low it passes TDO to LPT, right? But your words and test > demonstrate the reverse situation, TDO is suppressed when PROG is low. It's > strange. It's even more strange that the chip now responds incorrectly when > I set PROG to high. > With PROG=low I couldn't sence TDO at LPT; with PROG=high I can sence, but > JTAG protocol misbehaves. What am I doing wrong? There is no information I > can find explaining Xilinx cable behaviour. The circle at the side of the triangle indicates, that this input is an active low enable. This means that PROG=1 disables the driver and connects TDO to the parallel port. JTAG is quite sensitive to noise. Partly due to the switching voltage problem that I described. I am going to post a parital solution in response to Ricks posting. Using really short cables and trying different PC (or buying two or three different old parallel interface cards on ebay) can also help. Kolja SulimmaArticle: 47967
Peter,
While I don't use VHDL myself (I use Verilog.), I have some
experiences dealing with trying to get XST to pack FFs into IOBs.
You are absolutely correct that setting "Pack I/O Registers into IOBs"
synthesis option to "Yes" should always pack IOB FFs into IOBs, but
for some reason, XST doesn't always do the necessary duplication to
allow the packing.
You are also correct that if output or tri-state enable IOB FF doesn't
have fan-out of 1, that register cannot be pushed into an IOB.
I don't have a Virtex-II datasheet right now, so I am not 100% sure,
but the use of Clock Enable should not cause any problems when dealing
with IOB, so you should feel free to use it.
So, in order to push FFs into IOBs, "normally" (Not always though.)
you need to get XST to duplicate the FFs so that you get FFs with
fan-out of 1.
MAP (The tool that runs after NGDBUILD.) has no power to duplicate IOB
FFs even if you wanted it to, and that's a job of the synthesis tool.
Here are the instructions on how it can your problem can
likely be solved.
First of all, write a synthesis constraint file for XST.
The syntax of the XST constraint file is explained in XST's manual, so
you may want to download a copy of it from Xilinx.
____________________________________________________________________
begin TEST_OUT_FF
attribute offset_out_after of P_DR_BANK : signal is "5ns";
end TEST_OUT_FF;
____________________________________________________________________
Cut and paste the above code to a text editor, and save it as
"TEST_OUT_FF.cst". (I don't care about the file name.)
Go to XST's properties, and click "Synthesis Options" tab.
Click "Synthesis Constraints File," and specify the path
"TEST_OUT_FF.cst" is located.
Also, "Pack I/O Registers into IOBs" to "Auto" instead of "Yes" for
the time being.
Synthesize your design, and make sure XST correctly recognized
"attribute offset_out_after of P_DR_BANK : signal is "5ns";"
The synthesis log file will display that it recognized the above
synthesis constraint, or you should get a warning message.
If everything goes right, near the end of synthesis, XST should tell
you that it duplicated FFs to satisfy the "Pack I/O Registers into
IOBs" option.
If what I wrote didn't help you (XST didn't mention that it duplicated
IOB FFs.), change "Pack I/O Registers into IOBs" option to "Yes," and
replace the synthesis constraint file with the following one.
____________________________________________________________________
begin TEST_OUT_FF
attribute offset_out_after of P_DR_BANK<1> : signal is "5ns";
attribute offset_out_after of P_DR_BANK<0> : signal is "5ns";
end TEST_OUT_FF;
____________________________________________________________________
Resynthesize the design, and when doing so, make sure the
constraint is correctly recognized by XST.
If neither synthesis constraint file worked, try changing the "5ns" to
something smaller (i.e., "3ns") or larger (i.e., "7ns").
The reason "Pack I/O Registers into IOBs" option should be
"Auto" rather than "Yes" and you have to specify offset_out_after's
value is that, I have observed that if they aren't like that, XST
doesn't seem to want to duplicate FFs for some reason.
At this point, I believe it is to your advantage to see
whether or not the synthesis did indeed duplicated IOB FFs.
Assuming that you are using ISE 4.x (4.1 or 4.2), you are might be
aware that XST no longer generates an EDIF netlist of your design, and
instead generates an encrypted NGC netlist.
This has been a huge problem for some power users who want to see what
XST did when it synthesized the design.
To workaround this nasty problem, and to obtain an EDIF netlist, take
a look at this link.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=aceeac%249fj%241%40newsreader.mailgate.org
In case you are using ISE 4.2, you can obtain an EDIF netlist
from ISE's GUI.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=ad2sbv%248u0%2401%241%40news.t-online.com
Wondering why ISE 4.x's XST doesn't normally generate an EDIF
netlist? Here is an answer from a Xilinx employee.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=3D77B576.7166323B%40xilinx.com
When you take a look at the EDIF netlist, if XST correctly
duplicated the FF, you will see something like P_DR_BANK_0 and
P_DR_BANK_0_1 (Same thing will also apply to P_DR_BANK_1. There should
be P_DR_BANK_1 and P_DR_BANK_1_1).
One of the FF should be a complete duplicate that has fan-out of 1.
After you make sure the FFs were duplicated, run NGDBUILD and MAP, and
when running MAP, "Pack I/O Registers/Latches into IOBs" should be
"For Outputs Only" or "For Inputs and Outputs."
MAP's report or floorplanner can tell you if the FFs were indeed
pushed into IOBs.
Hopefully, the above instructions will help solve your
problem, and let me know if it worked or not.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
"itsme" <itsme@gmx.de> wrote in message news:<anrtu8$dia$07$1@news.t-online.com>...
> Hello,
> here is my little "test design"
> All I want is that all Outputs P_DR_BANK are packed into registers of an IOB
> in a Virtex2.
> However all Outputs are Registers only P_DR_BANK(0) is mapped in a IOB
> register.
> P_DR_BANK(1) uses a Slice FF.
> I found in the FPGA Editor that the Register which should be
> placed in the IOB has a feedback. So it can't be
> moved in the IOB.
>
> In my VHDL code (see below) I have some conditional assignments
> to the output signal and in some cases it should hold
> its old value.
> How can I tell the XST not to use the output of
> a register also as input?
> It should rather use the ClockEnable auf the Register which is
> also available in IOBs.
> I thought the XST Option - Pack I/O Registers into IOBs
> will do that.
>
> please help
> peter
>
> ----------------------------------------------------------------------
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
>
>
> entity TEST_OUT_FF is
> Port ( CLK: in std_logic;
> REQUEST: in std_logic;
>
> --- PAD Signals, should be in IOB Register
> P_DR_BANK : out STD_LOGIC_VECTOR (1 DOWNTO 0)
>
> );
> end TEST_OUT_FF;
>
> architecture Behavioral of TEST_OUT_FF is
>
>
> -------------------------------------------------------
> ---------------------------------- State machine
> type STATE_TYPE is (S_Idle, S_Active, S_Access);
>
> signal State: STATE_TYPE;
>
> BEGIN
> ---------Statemachine
> FSM:process(CLK)
> begin
> if Clk'event and clk='1' then
>
> P_DR_Bank(0)<='0'; -- Use this to get Register in IOB !! Why?
> -- P_DR_Bank(1) with no IOB Reg!!
> case State is
> ------------------
> when S_Idle =>
> if Request='1' then
> State <= S_Active;
> end if;
>
> -------------------
> when S_Active =>
> P_DR_Bank <= "10";
> State <= S_Access;
>
> -------------------
> when S_Access =>
> P_DR_Bank <= "01";
> State <= S_Idle;
>
> when others =>
> State <= S_Idle;
>
> end case;
> end if; -- CLK
> end process;
>
> end Behavioral;
Article: 47968Bob W wrote: > > Why can’t Xilinx Software be as good as Altera Software? Interesting discussion and I am surprised at some of the responses. I had a 6 month adventure with Altera MAX Plus and based on that I am surprised that anyone would ever use an Altera tool if they could avoid it. We were adding new features to an existing design in a 10K100A part on a board that had many units in the field. When we tried to implement a design that used 90% of the resources, the software could not handle the job. Even when we reduced the logic to 80% it would not route and meet timing. So we made lots of changes to the code to "optimize" it in ways that the P&R software could not screw up. In the end we got designs that met our timing specs, but would fail on the bench at room temperature. After tons of effort and wasted time we eventually found that the MAX Plus software was not analyzing timning correctly. We had some enable signals that fanned out widely and we suspected that this was the cause. But even after we duplicated logic to reduce fan out, we still had timing related failures on designs that were passing in static analysis. The tool just did not work. I can't say that the Xilinx tools are perfect. But when you do tough designs I find it a lot easier to see what is going on with the P&R and to find ways to deal with any problems. The pushbutton Altera approach seems to get in the way of seeing what is actually happening under the hood of your design. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47969
First of all, sorry that this posting is an off topic posting for news:comp.arch.fpga, but I just noticed that several postings I made to news:comp.arch.fpga through Mailgate.org (http://www.mailgate.org) didn't show up when I did a newsgroup search with Google's newsgroup search engine. So, I checked the message threads at Google, but the messages I posted weren't there at all. Has anyone also noticed this issue? Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.)Article: 47970
yep, I made a similar observation several months ago but never did rectify it !!! Dave "Kevin Brace" <kevinbraceusenet@hotmail.com> wrote in message news:cc7b0b5f.0210081305.16685256@posting.google.com... > First of all, sorry that this posting is an off topic posting for > news:comp.arch.fpga, but I just noticed that several postings I made > to news:comp.arch.fpga through Mailgate.org (http://www.mailgate.org) > didn't show up when I did a newsgroup search with Google's newsgroup > search engine. > So, I checked the message threads at Google, but the messages I posted > weren't there at all. > Has anyone also noticed this issue? > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 47971
In article <anus53$hkp3q$1@ID-92522.news.dfncis.de>, Jensniemann@gmx.de (Jens Niemann) wrote: > is there somewhere a reference design or some information about > booting a SRAM-based FPGA via a USB interface? The newer FTDI devices have a way of doing just this. http://www.ftdichip.com JonArticle: 47972
> That's an interesting comment since its 180 degrees reversed from my > experience! We build the P-III logic Now that I read it twice, I got it. You do not mean Pentium-III ;-) > onto the board so we can just use a standard Centronics extension cable. > In the original version we used > 74LS125 parts powered from 5V and had no end of trouble programming XC18V04s > (and just very occasionally > XC95K CPLDs)! In fact allowing for the Schottky drop and the ATX PSU's 5.1V > it was about 4.8V. Removing > the Schottky made the problem worse. Reverting to HC125s powered from > 3.3V "fixed" it What Xilinx says, is that I works on some mainboard, and it doesn't on other. With a scope you can clearly see that this depends on the output waveform of the parallel port. I do not understand the use of the 100pF capacitors which are one of two unsuccessfull modifications of Xilinx to solve the problem. The corner frequency of the resulting filter is around 100MHz. The slope gets extremly slow at the and, with a lot of high frequency noise added to it. 350mV peak two peak on some boards. So using one of these 50mV Schmitt-Triggers surely won't help. One solution is to lower the switching voltage to switch with the faster slope. LS has a rather low switching voltage. The 74LS125 by fairchild guarantees to accept anything above 2V as a logical 1 if powered with 5.25V. It switches anywhere between 0.8V and 2.0V. So at 4.8V you are pretty sure to have a switching voltage well below 2V. It was 1.2V for the Chip in our Lab. Without the diodes it will be closer to 2V and within the slow region of the slope. A Phillips 74HC125 switches approximately at VCC/2 or about 1.65V in your case, so you are definitely in trouble. This is true for most manufacturers. The ST (SGS Thomson) MC74HC125 Parts switch at 0.28 x VCC which should be safer. You can further lower the switching voltage by a voltage divider between the input and VCC. A better solution is to build a Schmitt-Trigger of your own: Use a resistor to feedback the output of the 74HC125 to its input. We have good results with 1.5K resistors. Wait, you allready fixed the layout for your board using 74HC125 in SO14 package? No problem. Resistors in 0402 Package fit perfectly between Pin 8 and Pin 9 of the chip (for CLK). More for DIN and PROG would not be a bad ideas either. And while you are at it: A weak pullup for PROG and CTRL is a good idea also. Hope that helps, Kolja SulimmaArticle: 47973
Hello Sanjay, I'm sorry but I don't have good news for you. The IOB pairs share clock routing resources, so it is not possible to have more than two output clocks per pair. This is a hardware limitation and there is no work around. More details can be found at: http://support.xilinx.com/techdocs/11747.htm Regards, Bret Wade Xilinx Product Applications S P wrote: > Hi, > > I was hoping someone would be able to enlighten me on working around > the problem of clock routing to the output pads in Virtex 2. I have > two IOBs in one tile and there are three clocks. One IOB has a > regular OFF driven by one clock, the other has a ddrff to realize a > 50% duty cycle driven by two clocks different from the other clock. > My clocking scheme at present is > > //clk_in --> ibufg -+--> dcm_int clk0 --> bufg -----> clk_in > // | > // +--> dcm_ext -+-> clk0 ----> bufg --> clkExtP --+ > // | | > // | V > // | ddrff-->clk_out > // | ^ > // | | > // +-> clk180 --> bufg --> clkExtN --+ > > I would appreciate your feedback. > Thank you. > -sanjay > > I get following error - > ERROR:Place:1721 - The current designer locked placement of the IOBs > write_out > and clk_out makes this design unroutable due to a physical routing > limitation. This device has a shared routing resource connecting > the ICLK > and OTCLK pins on pairs of IOBs. This restriction means that these > pairs of > pins must be driven by the same signal or one of the signals will > be > unroutable. Before continuing with this design please unlock or > move one of > these IOBS to a new location.Article: 47974
First of all, notice that I changed the title slightly.
Bob W wrote:
>
> Why can't Xilinx Software be as good as Altera Software?
>
> I am an independent consultant developing FPGAs and PLDs using both
> Xilinx and Altera development software. My clients usually have a
> preference between Altera and Xilinx. From a hardware perspective, I
> can do most designs just as well with either part. I just wish that
> Xilinx could produce development tools that are as a good as those
> provided by Altera.
>
> The Altera tools are such a pleasure to use. The tools are very well
> integrated into a single Windows program. They have a consistent user
> across the toolset. Any time an error occurs, a single click brings
> you to the source of the error. The help files provide useful
> information.
>
While I agree that Quartus II's help system is better than
ISE's, Altera doesn't seem to have detailed manuals of their software
available for download unlike Xilinx.
> The Xilinx toolset is a hodgepodge of command line tools with a lousy
> user interface on top of it. The tools don't talk to each other, the
> error handling is terrible and the help files are useless. An analogy
> comes to mind. I would compare the Altera software to a sports car and
> the Xilinx to a donkey. Both modes of transportation will get you
> where you want to go. The sports car has an enjoyable ride. The donkey
> gets you there eventually, but the ride stinks.
>
I use ISE's GUI flow rather than running tools from a batch
file, so what you are saying is not a issue to me at all.
> Here are a few (there are many more) of the typical problems I see
> when using Xilinx ISE:
>
> 1) When an error comes up, it usually has a non-descriptive name. If I
> double click on the error, most of the time it does not show the
> source of the error.
>
> 2) If it does show me the error, it is usually at some intermediate
> code, not at the source. For example, if there is a section of the
> design done in schematic capture, the program will show a VHDL file
> with an error, rather than pulling up the schematic and showing the
> source of the error.
>
> 3) Sometimes the error message will say that something is off grid
> (Error point not on primary grid) on the schematic at x=1608 y=1504
> and expect me to open the schematic and hunt for the X,Y location. If
> the program knows the location, it should be able to open the
> schematic and highlight the error for me.
I find Xilinx's error messages adequate for tracking down
problems.
I don't use Xilinx's schematic tool, so I don't really have any
comments about it.
> 6) Options have to be set within many different separate programs. To
> set some options you may have to click on the Synthesizer, than the
> Fitter, then the Program file generator.
>
I like the fact that ISE's built-in synthesis tool XST has far
more synthesis options supported than Altera's built-in synthesis tool
(Okay, I can also use LeonardoSpectrum-Altera, but when I tried to run
it through Quartus II's NativeLink feature, I was not able to set
synthesis options from Quartus II. If I wanted to tinker with
synthesis options, I had to run LS-Altera separately.).
Personally, I prefer that the options are broken up, and assigned to
different programs (NGDBUILD, MAP, PAR, etc.).
> 7) Sometimes when you edit the pins assignments, save them in
> Chipview, and then try to recompile the design nothing happens. You
> have to remember that as long as Chipview is open, the Project
> Navigator will ignore you and not show any reason why. (Oh yeah, I
> have to close that program before it will respond).
>
I assign pin assignments through a UCF file, so what you
mentioned is not a issue.
Don't you also assign pin assignments through a CSF file in Quartus
II?
> 9) I try to run the included ModelSim simulator. The ModelSim splash
> screen comes up but nothing happens. The program doesn't start. The
> Project Navigator shows no error. After much wasted time, I find that
> the license for the simulator is tied to the IP address of the
> computer it is used on. Since I was using a laptop, its IP address
> depends on where it is plugged in. So I need a license for each IP
> address my laptop uses. There was no error message (How about "Invalid
> License!") from Navigator or ModelSim. This is poor software
> integration.
>
I usually run ModelSim XE-Starter by itself, not through ISE.
> There are just a few examples of the types of problems that users have
> to live with. The Xilinx software is certainly usable and I have done
> many designs with it. It just makes things much harder than they
> should be. As a consultant, I appreciate well written tools save me
> time and my clients money. The Xilinx tools are poorly written and
> integrated. It has been like this for years. The new release (5.1) is
> not much better. Maybe if you have the major market share like Xilinx
> does, you don't have to care about the developers. Many Xilinx users
> have never tried the Altera software and don't know what they are
> missing.
>
Here are my complaints of Quartus II.
1) When running Quartus II on a Windows 98 PC, it drains System
Resources rapidly that, I often have hard times running it along with
another program (i.e., Internet browser).
When the System Resources drain gets so bad, I often have to exit
Quartus II, and restart it again, which is irritating.
This problem doesn't happen with ISE, and ISE keeps the System
Resources usage to a minimum (10% to 15% at the most.), so I don't
have to restart it so many times.
Sure, I can get Windows 2000 or XP, but I personally pay anymore OS
tax to Microsoft (I am sure switching to Windows 2000 or XP will
improve my productivity because the OS will crash less often . . . ).
2) The Quartus II text editor doesn't allow the user to edit the text
under search while I am searching for a keyword. This really irritates
me because I have to close the search box just to edit the text. ISE's
editor doesn't suffer from this problem.
3) Quartus II built-in synthesis tool doesn't support important
synthesis options like IOE FF duplication and "keep" attribute to
preserve a wire. Because of these problems, I am pretty much forced to
use LeonardoSpectrum-Altera instead which I don't like.
4) The Fitter is broken. I have seen many cases of questionable
placement of LE. I have seen a FF that will connect to an output pin
being placed soooo far away from the output pin that the routing delay
was something like 7ns . . . (The target device was a FLEX10KE
EP10K100EFC484-1.) I personally have never seen Xilinx's PAR do
something similar to that even if I didn't use an IOB output FF.
Wasting 7ns in routing makes my life pretty hard when I am trying to
meet 33MHz PCI's Tval < 11ns because you also need to consider the
FF's Clock-to-Output (Tco), an output pin delay and clock skew.
5) While Xilinx's floorplanner isn't perfect, it still works far
better than Altera's. In Altera floorplanner, I cannot easily see
whether or not a LUT or FF of a LE is utilized. In Xilinx's one, I can
see visually whether or not a FF or a LUT within a CLB is utilized.
6) Besides the GUI issue of Altera floorplanner, when I make an
assignment of a certain LUT to a certain LAB, I have seen the fitter
duplicate the LUT which I don't want it to duplicate, and
automatically place the LUT somewhere (i.e., LUT ix7423 gets
duplicated as ix7423~1, and the placement information for ix7423 gets
ignored when the fitter places ix7423~1.). This LUT duplication issue
is one of the reason why I stopped dealing with Quartus II because it
makes the floorplanner totally useless.
7) Another problem of Altera's floorplanner/fitter. A few months ago,
I placed four FFs to a LAB, two of the FFs going to one pin
(Obviously, an output and an OE FF.) and rest of the two FFs going to
another pin. For some reason, the fitter will stop the fitting, and
will display an error message that I cannot have four FFs within a LAB
(I believe the fitter worked okay when I removed one of the FF from a
LAB, and moved it to another LAB.). I never figured out a way to fit
these four FFs, and this issue also makes the floorplanner useless in
Quartus II.
8) Altera doesn't offer a low level tool like FPGA Editor in Quartus
II. Because of that, users cannot see how the fitter routed the chip.
> The Altera tools have a consistent interface and were written to run
> in a Windows environment. They have an intuitive feel. The utilities
> are so well written that you never leave the main program to run > them.
While it is good that floorplanner is integrated within
Quartus II unlike ISE, I personally don't mind the floorplanner is
separate in ISE.
I suppose it is a matter of personal preference, I find ISE's GUI more
intuitive than Quartus II's.
> They all look like part of the same program. There are no programs to
> open and close in the right sequence. The errors codes give meaningful
> descriptions. More detailed descriptions can be found be clicking on
> the help button. Double clicking on an error brings you back to the
> actual source of the error! All of the options are set within the one
> main program.
>
> I have no interest in encouraging people to use Altera over Xilinx. I
> want Xilinx to write software that is as good as Altera's. Since I use
> both packages, I would rather see Xilinx take the challenge and
> improve their tools.
>
> Bob
I personally will like to see Altera fix the problems I just
mentioned, especially the issues with fitter and floorplanner which
are fatal.
Until these issues are solved, I personally won't enjoy using Quartus
II.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
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