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naderimisc@yahoo.com (Masoud Naderi) wrote: > 1 - Proposed methods such as TMR (majority) have very high overhead > (despite their potential problems). As you know, in classical > fault-tolerant design techniques overhead is not the main issue, at > least it is not the most important one. TMR has not the overhead you might think of it. Normal TMR means you need three ff and a 4:1mux instead of each ff. As here allready stated, there are processes allready including TMR-FF, so the overhead is very minimal. TMR is important if SEU could occure. SEU are mostly introduced by x-rays and electromagnetic waves. That's not the problem on earth that you face in space, but that's still a problem here on earth. Instead of TMR you could use error correcting codes (hammingcodes). I did a few benchmarks for a process with "expensive ff". And found it still better to use TMR instead of ecc because of the large xor-trees. Both for timing and place. > 2 - The other problem is due to PHYSICAL implementation of a VHDL > code. How is it implemented and how designers can control mapping > process precisely without involving in too much details. Please note, > in traditional design methodes mapping is done by designner rather > than by a machine, therefore so many factors would be under control. I didn't agree with you. In cellbased designflow you _might_ spend a lot more manpower for mapping, but thats not necessary a matter of choosen technology. Noone fobidds you to spend the same effort and manpower for physical layout of fpgas. If it's that critical you will spend the same efford. > 3 - There are systems that require high availabity without radiation > hardness or other special effects. For example, in Telecomm. %99.999 > availability is of concern. What about designing for these systems? You wrote, your familiar with traditional methods. Why not telling us the methods you know and we tell you how to do them in FPGA ;). As I'm doing telecomm for satellites I do 100% availability (almost *g*) The most important point is, that your design has to recover without reset from every state you could reach by error. > 4 - In classical methodes "fault masking" is more important than > "fault detection", What faults? A error in data first needs to be detected, before its corrected. > "Steve Casselman" <sc@vcc.com> wrote [fullqoute deleted] Please, delete all lines you don't respond directly to. It's bad style to make fullquotes. bye ThomasArticle: 46926
In addition to what Markus wrote: be sure to end the original simulation with a 'quit' or 'quit -sim' command. If you don't, you will not be able to open the .wlf file next time because it hasn't been closed properly. -- Marten "Markus Sponsel" <msponsel@nospam.profichip.com> wrote in message news:almm7j$1qve5o$1@ID-40100.news.dfncis.de... > Hi Yan, > > > It is possible to save simulation results with modelsim, instead of running > > the simulation again when needed? > > Yan > > Yes, it is possible. Modelsim saves the result of the simulation in a > file called *.wlf (typically "vsim.wlf" if you do not choose another > file name for it). You can load this file with "vsim -view <filename>.wlf". > To view this file choose the signals and add them with "add wave <signal>" > (typically done with a little *.do file which also preserves the signal > ordering". > > Hope this helps, > > Markus Sponsel > > (To answer me directly remove "nospam" from the e-mail address) > > > ################################################# > profichip GmbH > Einsteinstraße 6 > 91074 Herzogenaurach > Germany > > Tel.: +49.9132.744-205 > Fax: +49.9132.744-204 > > email: MSponsel@profichip.com > www: www.profichip.com > ################################################# > > > "Yan" <chan_jurgens@planet.nl> schrieb im Newsbeitrag news:allf4h$qek$1@reader13.wxs.nl... > > Hi, > > It is possible to save simulation results with modelsim, instead of running > > the simulation again when needed? > > Yan > >Article: 46927
Hi Chan, Markus left everything clear. Another thing you can do with Modelsim is to capture the activity in the Value Change Dump (VCD) format. This is a standard format for describing simulation activity (I don't think is a true standard anyway). This file is use in tools like Power Stimator Tolls (XPower or PowerTheater). You type: env / vcd file sim.vcd "Run the simulation" vcd flush I hope it helps. Ulises Hernandez ECS Technology Limited "Yan" <chan_jurgens@planet.nl> wrote in message news:allf4h$qek$1@reader13.wxs.nl... > Hi, > It is possible to save simulation results with modelsim, instead of running > the simulation again when needed? > Yan > > >Article: 46928
Sorry I skipped a line: Add your TOP level I/Os to your waveform window Then you type: > env / > vcd file sim.vcd > vcd add -r * Then run the simulation When it stops, type: > vcd flush Regards Ulises Hernandez ECS Technology Limited "Ulises Hernandez" <ulises@britain.agilent.com> wrote in message news:1031822299.477177@cswreg.cos.agilent.com... > Hi Chan, > > Markus left everything clear. Another thing you can do with Modelsim is to > capture the activity in the Value Change Dump (VCD) format. This is a > standard format for describing simulation activity (I don't think is a true > standard anyway). This file is use in tools like Power Stimator Tolls > (XPower or PowerTheater). > > You type: env / > vcd file sim.vcd > "Run the simulation" > vcd flush > > I hope it helps. > > > Ulises Hernandez > ECS Technology Limited > > > "Yan" <chan_jurgens@planet.nl> wrote in message > news:allf4h$qek$1@reader13.wxs.nl... > > Hi, > > It is possible to save simulation results with modelsim, instead of > running > > the simulation again when needed? > > Yan > > > > > > > >Article: 46929
I am not 100% what your problem is but my guess is that your external bus does not appear to be tristated. There is sometimes a problem when a tristate is inferred in a module that is not the top level in your design. If this is the case you will probably find that you have internal TBUFs in your design. The TBUF outputs will pass through to the I/O cells where they are driven out constantly. If you are not expecting internal tristates examine your map report to see if there are any in the design. Alternative look at the logic in FPGA Editor. A quick look at the I/O cells will show if no tristates are present. John Adair Enterpoint Ltd. "Anjan" <anjanr@yahoo.com> wrote in message news:5a5faf7b.0209102007.6fe3260b@posting.google.com... > Hi > I am interfacing a xilinx virtex with DSP over a tristatable bus. > InPAR simulation the data bus goes to the final value after > propagating over few X for small time(10 ns). There is no bus conflict > also. The sample code is as follows > if enable > bus<=mem(conv_int(address_input)); > else > bus Z > what could be the source of problem and will it cause problem in h/w.Article: 46930
"Govind Kharbanda" <govind.kharbanda@sli-institute.ac.uk> wrote in message news:2f5db38d.0209040616.64aeee66@posting.google.com... > I have solved the 'undeclared identifier' problem by: > > * removing the 'par' statement around the variable declaration > * declaring the variables in main as well as in the macro procs. > > However I now get a new error: 'object cannot be assigned to'. This Remember that you are not allowed to assign to bit selects regards Alan <snip> -- -- Alan Fitch [HDL Consultant] DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 46931
Prashant wrote: > I can view the signals of my testbench in modelsim. If I try to view > the internal signals in the gate level netlist, Modelsim tries to load > all the internal signals, which is in thousands. Basically, this > loading has been running for hours and I'm not sure if it will ever > get loaded. I have simulated netlists generated using the Xilinx tools before and I'm assuming the flows are similar. You have two options: 1. Make sure that you are not trying to view the source in the MTI window as if your netlist is flat then this will take a long time to load. You can also just add the signals you want to look at. So instead of doing a 'log -r /*' you can use 'add wave <signal_name>' but that assumes that the signal names haven't been changed during synthesis which is unlikely. 2. With the Xilinx tools I can produce a Verilog netlist from the first stage of the tools flow (from the ngd file if you're familiar with it) that retains the hierarchy. This makes it much easier to search for the signals you are interested in. Shareef.Article: 46932
"Govind Kharbanda" <govind.kharbanda@sli-institute.ac.uk> wrote in
message news:2f5db38d.0209060707.5bddf638@posting.google.com...
> Usually when for loops are put into HandelC, it's best to recode
them
> as a while loop as the index variable can be incremented in
parallel
> with whatever action is performed on each iteration.
>
> I've got a bit of an odd for loop here, and I'm not sure if I've
done
> it right. Here it is:
>
> unsigned trigwidth T; /* index to init->trig */
> unsigned log2n stages; /* number of butterfly stages */
>
> unsigned log2n i,j; /* index variables for loops */
>
> stages = log2n - 5; /* n = 256 usually, so stages = 3 */
> /* log2n defined as a macro expr */
>
> /*
> * Following lines are a little tricky:
> * originally stated:
> *
> * for (i=1; --stages>0; i++){
> * for (j=0; j<(1<<i);j++)
> *
mdct_butterfly_generic(T,x+(points>>i)*j),points>>i,4<<i);
> * }
> *
Firstly, you might want to try this option.
A for loop
for (i = 0; i<10; i++)
{
statements;
}
can be replaced with
for (i = 0; i < 10) par {
i++;
statements;
}
which speeds up the execution of a for loop.
Secondly, if you use the value of i inside a nested loop, you need
to be very
careful to make sure that if you use the outer loop variable in an
inner loop,
you are using the correct value (because in Handel-C the variables
may update
in parallel rather than sequentially as in C).
<snip complicated code>
> Also the compiler is throwing up width errors, for instance
width '8'
> doesn't match width '4'. For instance
>
> while (j<(1<<i))
>
> j is of width 8, how come 1<<i is being inferred to have a width
of 4?
>
In your code, i is declared the same as j, i.e. a width of 8, so I
guess i and
j have the same width!
However the value '1' is not known. Try using
while (j < (unsigned 8)(1 << i))
or declaring a constant to represent the number 1 of the correct
width, e.g.
static const unsigned 8 ONE = 1;
and then using
ONE << i
regards
Alan
--
Alan Fitch
[HDL Consultant]
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire,
BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com
This e-mail and any attachments are confidential and Doulos Ltd.
reserves
all rights of privilege in respect thereof. It is intended for
the use of
the addressee only. If you are not the intended recipient please
delete it
from your system, any use, disclosure, or copying of this
document is
unauthorised. The contents of this message may contain personal
views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 46933The signal "sk_wroffset_ctr_en" must be put in the process sensitive list. Jianyong -- "Nikhil Bhatia" <rite2nikhil@ieee.org> wrote in message news:ee78d72.-1@WebX.sUN8CHnE... > Hi, > > In the following code, synplicity removes the "sk_wroffset_ctr_en " i.e optimises away. > > I have kept the syn_keep attribute on it but to no effect. I have found out that the conv_integer function is the problem. Caue When I dont use the conv_integer function then this optimising problem isnt there. > > Can someone suggest how synplicity can be made to take this function. > > cheers > > nikhil > ######################################################################## > > skwoc_p : process (clk20, rst) > begin > if rst = '1' then sk_wroffset_ctr_en <= (others => '0'); > elsif clk20'event and clk20 = '1' then > > > for i in 0 to 83 loop > if ((buffer_en(i) = '1') and ((conv_integer(sk_timeslot_ctr_val(i))) = i)) then > sk_wroffset_ctr_en(i) <= '1'; > else > sk_wroffset_ctr_en(i) <= '0'; > end if; > end loop; > end if; > end process skwoc_p; > > ####################################Article: 46934
Coolrunner: 5V-3.3V io tolerant Coolrunner-II 3.3V io toleranr internal hardwire divisor high-speed You need a XPLA3 CPLD Dev. kit, try the Chameleon POD on http:/www.amontec.com Regards Laurent Gauch John wrote: > What are the fundamental differences between Xilinx's CoolRunner XPLA3 > and CoolRunner-II? And which family tends to use the least power? >Article: 46935
I am using a XC2V6000 in a BF957 package with the output configured for LVCMOS33,slew limited, and with a 4ma drive. All the other outputs configured the same way produce good 0V-3.3V outputs. Two of these outputs generate signals that are -200mv to 400mv. I measured the resistance to ground of a good output and its about 1.5MOhms while a bad output is 4.6MOhms. Does this seem like a bad solder joint or a bad output? Thanks in advance BillArticle: 46936
In article <2g%f9.282256$_91.324863@rwcrnsc51.ops.asp.att.net>,
"William L Hunter Jr" <wlhunterjr@attbi.com> writes:
|> I am using a XC2V6000 in a BF957 package with the output configured for
|> LVCMOS33,slew limited, and with a 4ma drive. All the other outputs
|> configured the same way produce good 0V-3.3V outputs. Two of these outputs
|> generate signals that are -200mv to 400mv. I measured the resistance to
|> ground of a good output and its about 1.5MOhms while a bad output is
|> 4.6MOhms. Does this seem like a bad solder joint or a bad output?
The negative voltage suggests a thermoelectric/electrochemical effect and thus a
very bad solder joint...
BTW: I find it better to measure the voltage drop across the internal protection
diodes (ie. probing with the diode tester's minus clip at the pin vs. plus at
GND). Usually you get a drop of about 500-600mV, you can also find out shorts and
even different pin types (general IO vs. DONE/INIT etc). If the voltage drop
changes significantly when pressing at the chip or bending the PCB a bit, then
it's clear...
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 46937My division problem is as follows: Dividend(numerator) Sign+16bits Divisor(denominator) Sign+14bits Valid range of answer -13.00 to +13.00 (otherwise flag an error) Desired accuracy 8 fractional bits The pipelined divider core takes 16+8+4+3=31 clocks to do this. Now theoretically a divider can pump out 1 bit per clock. And I'm looking for Sign+4 integer+8 fractional =13 bits. Is there some way to make use of the known range of answers to do this division faster (without unduly bloating the divider) ? Thanks in advance for any help or suggestions ! -rajeev-Article: 46938
I'm running an example with 4 clocks per division and 31 clock latency. What I see in the simulator is Input_Presented_At_Clock 3 4 5 6 7 8 9 Output_Ready_At_Clock 35 35 39 39 39 39 43 which seems to say the divider takes data on clocks 4,8,12 etc, and delivers the output 31 cycles later. So far so good. But there's no sync(or RFD or RESET etc) signal on the pipelined divider to tell where it's reference edge is. So the safe thing to do seems to be to wait 31+3=34 clocks. But I'm wondering if I there's a good way to access the appropriate internal signal from the Core ? I figure I might be able to find the signals and do this in the FPGA editor, but that could get painful if I have to repeat it every time I spin the design... Any thoughts or suggestions ? Anybody been down this road before ? Thanks in advance ! -rajeev-Article: 46939
Hi, I appreciate all your responses. Its been very useful in building my confidence in the approach I'm using. I do my RTL simulations in Modelsim-Altera, but have been facing trouble with gate level sims. Hence I have had to switch to Quartus 2 for gate level simulations. Thanks all, Prashant "Matjaz Finc" <matjaz.finc@fe.uni-lj.si> wrote in message news:<alpg0m$576$1@planja.arnes.si>... > I have been using Quartus II design flow as you described. It works fine. If > you want just the RTL simulation set Processing->Simulator > settings->Functional simulation. Actually, it's not "true" RTL simulation - > it simulates the synthesized output, but works much faster than timing > simulation. I had no major troubles so far, but haven't tried very large > designs. I work with Nios processor and simulate only the peripherals. For > simulation, you don't have to compile the design - just run > check&synthesize. Works faster after changing source code. I have also had > some problems with Modelsim speed - seems to work quite slow for designs > with lots of signals... and the custom and trial versions are additionally > slowed down on purpose, just to force you buy the full licensed version... > > Matjaz > > > "Prashant" <prashantj@usa.net> wrote in message > news:ea62e09.0209110814.2178ee93@posting.google.com... > > Hi, > > > > I'm trying to develop a design and prototype on the A15E board from > > Altera. This is the design flow I plan to follow. > > > > 1. Write RTL. > > 2. Synthesize RTL in Quartus 2. > > 3. Simulate the design using Quartus 2 simulator. > > 4. After the simulation looks correct, program the device on the > > board. > > > > I have seen a lot of people recommend Modelsim for simulations and > > Leonardo/Synplicity for synthesis. I understand the reasons for using > > these tools. > > > > But, instead if I followed the route of synthesis, place & route and > > simulation in Quartus 2, would my design work in the FPGA on the board > > ? I believe it should. Is there anything I should be careful about ? > > > > Do let me know. > > > > Thanks, > > PrashantArticle: 46940
Hello, I have never used FPGA before. Could anybody tell me if it is possible to make a 2-D resistor array (N*M) using FPGA? The power input of each resistor needs to be controlled individually. It is preferrable that the FPGA board has built-in array of cavities. Thank you! -metaArticle: 46941
"John_H" <johnhandwork@mail.com> wrote in message news:3D7FBAFE.C1582F72@mail.com... > (4.1i) Constraints Guide, TSidentifier, Defining Intermediate Points (UCF) > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/cgd/t11.html#1018081 > Just saw it - had to share. > - John_H > > Jan Gray wrote: > > [Xilinx: please confirm that a timespec can have more than one 'thru' and > > yet the "right thing" happens (constraint only applies to those paths that > > go through all the 'thru' points).] Yes, thanks, I found the same reference. Unfortunately, my experience of several hours of careful experiments, demonstrates that the feature does not seem to work reliably near carry-chains, leading to both failed time constraints (when the slack-relaxed timespec-thru-thru path did not constrain the net that it should have) and, much worse, missed timing constraints (when the slack-relaxed timespec-thru-thru path applied to a net that it should not have). I conclude that non-trivial addmux-structure scenarios (not between registers) do not seem usable given current limitations in the timing analyzer. I'll give it another try when 5.1i arrives. In my scenarios, it seems the only way to make timing, safely, is to replace the addmux (1 LUT/bit) with add then mux (2 LUTs/bit). Like the non-support of XC4000E free-H-muxes, this seems to be another case where the silicon is willing but the tools aren't, to the tune of ~20% area penalties and ~20% (unnecessary extra net and Tilo) cycle time penalties. I reiterate the helpful suggestions in my first posting in this thread. Jan Gray, Gray Research LLCArticle: 46942
Hi I am developing a Xilinx XC2S150 design using Mentor FPGA Advantage (Leonardo Level II and Modeltech PE). I need to run a post-synthesis simulation to verify my design with my test bench. Does anyone have a "cook-book" method to do this? I am in a hurry and would like to learn the details later. Any help would be greatly appriciated. Thanks Much Mike D.Article: 46943
Have you looked at the 18 x 18 signed combinatorial multipliers in Virtex-II ? I would think that you can do a successive approximation division with far fewer clock cycles... Just an idea... Peter Alfke ========================= Rajeev wrote: > I'm running an example with 4 clocks per division > and 31 clock latency. What I see in the simulator > is > > Input_Presented_At_Clock 3 4 5 6 7 8 9 > Output_Ready_At_Clock 35 35 39 39 39 39 43 > > which seems to say the divider takes data on clocks > 4,8,12 etc, and delivers the output 31 cycles later. > So far so good. But there's no sync(or RFD or RESET etc) > signal on the pipelined divider to tell where it's > reference edge is. > > So the safe thing to do seems to be to wait 31+3=34 > clocks. > > But I'm wondering if I there's a good way to access the > appropriate internal signal from the Core ? I > figure I might be able to find the signals and do this > in the FPGA editor, but that could get painful if I have > to repeat it every time I spin the design... Any thoughts > or suggestions ? Anybody been down this road before ? > > Thanks in advance ! > -rajeev-Article: 46944
Yan wrote:
> It is possible to save simulation results with modelsim, instead of running
> the simulation again when needed?
You can also share waveforms as email
attachments without requiring modelsim as
a viewer.
Print selected waveforms to a .ps file from modelsim
then converting to .pdf using pstill or distill.
-- Mike Treseler
Article: 46945"Neil Franklin" <neil@franklin.ch.remove> ha scritto nel messaggio news:6u7kht5vv0.fsf@chonsp.franklin.ch... > So I doubt you will find an FPGA with > hardwired DAC circuits. There are the FPAAs, or "analog FPGA". For example: www.anadigm.com By the way, has anyone used this kind of devices? I'm not even able to download their trial software (the connection is always reset before the end, and after few retries their web server apparently bans my IP). -- LorenzoArticle: 46946
In article <allf4h$qek$1@reader13.wxs.nl>, chan_jurgens@planet.nl (Yan) wrote: > Hi, > It is possible to save simulation results with modelsim, instead of > running > the simulation again when needed? > Yan As well as keeping the waveform file as others have said, you may also want to learn about the checkpoint command. JonArticle: 46947
I have a Virtex design with an internal tristate bus. I know it isn't REALLY a tristate bus, but emulated with OR's feeding to ANDs, etc. However, is thereany way at all I can view the real logic built by the PAR tool (ISE 4.2i). The editor only shows TBUFs, but this isn't real silicon. Or am I wishing for the impossible? TIA, Niv.Article: 46948
Hiya, Just to make sure that everyone knows my bias: I have worked for both Mentor Graphics and Altera (and work for neither at the moment). While at Altera I have pushed hard for the Linux port and a whole bunch of other improvements in Quartus (IBIS support etc) so I'm following development closely. I have been checking out the improved HDL support in Quartus 2.1 and I must say I am impressed with the stability of the parser. I have run several designs that Leonardo is having problems with (from generating wrong logic to downright crashes) through Quartus to see whether I could get one of those "Internal Error" things to pop up, and so far it has eaten everything I thew at it. As to logic optimization, that's another story. I am not saying that the optimizer is particularily bad, but generally speaking I would say that Leonardo and Synplify are definitely doing a better job. I'm too busy doing other things to run proper benchmarks, but on average I would guesstimate that the Quartus optimizer generates logic that is 10-15% larger and between 5 and 10% slower than what the Big Two cough up, but part of that really depends on your design. Data path operations seem to clearly be done more efficiently by Leonardo, while control stuff seems to be pretty much on par. Best regards, BenArticle: 46949
One additional point: > >2) Has the VHDL parser/syntax checker been re-written more robustly? > > "The Quartus II version 2.1 development software also includes improvements > to the integrated synthesis tool. This new synthesis technology also > includes language extractors licensed from Verific Design Automation Inc.". > The link is http://biz.yahoo.com/prnews/020715/sfm041_1.html. Verific's link > is www.verific.com Looking at the board of directors, these guys (Rob Dekker, Ewald Detjens) were some of the hardcore technology wizards at Exemplar Logic before the company was bought by Mentor. They're good. Ben
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