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Marcel <marcelgl@hatespam.xs4all.nl> wrote: : Maybe slightly off topic, but sombody here know where to get Xilinx FPGA in : europe in small quantities for a reasonable price ? catalogue distributors: www.rs-components.de. www.farnell.de, www.schukat.de, www.segor.de Distributors are SILICA and Impact Memec. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 47276
"Bruce" <bruce@bytes.co.za> schrieb im Newsbeitrag news:ee790ca.-1@WebX.sUN8CHnE... > I am a newcomer to VHDL and I need to design an MP3 decoder. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ I dont think this two statements mix well. -- MfG FalkArticle: 47277
"Laurent Gauch" <laurent.gauch@amontec.com> schrieb im Newsbeitrag news:3D8825C8.90009@amontec.com... > Now my problem is to connect and to use my last GCLK pin like a standard > input. > Is There a way to use a GCLK pin without passing through an IBUFG. If > yes, which constraint will do that for me. In Foundation (which uses FPGA-Express for VHDL synthesis) you need to constrain the use of NO clock buffer. This is done using the systhesis constraint editor. On the GUI, ther are two view on the left window, the first (standard) contains all source files, the second the different versions. If you click you version with the right mouse button, a pop-up menu will contain an entry about synthesis options (Iam not sure, it can also be implementations options.) This opens the constaints editor. In one of the lists you can select the use of BUFGs for all signals. Just set the entry for this specific signal to NONE. -- MfG FalkArticle: 47278
In Altera, if you load the program into the configurators, you always need to power cycle, since the configurators only "boot" upon application of power. If you program the part directly via jtag, instead of programming the configurators and letting them program the part, then you don't need to power cycle. I don't know anything about xilinx parts, though. "Tony Dean" <td@emu.com> wrote in message news:33aa9b10.0209212030.73e929f4@posting.google.com... > I've just spent the last week in hell, baffled as to why my FPGA > design was not working. Was I really THAT bad of a VHDL coder? > > To make a long and painful story short, it wasn't my fault. And it > wasn't Synplicity's fault (sorry about that call to tech support). It > is Xilinx's fault. I don't mean to bash Xilinx, as their products are > great, but they blew this one. > > The problem: > When using JTAG to configure a Spartan II FPGA (and perhaps Virtex > too), the first configuration after power up will work, but subsequent > ones will not. > > Worse, the re-configurations may APPEAR to work, because something did > get downloaded, and the Impact programmer chirps "PROGRAM SUCCEEDED". > But after 3 days of dissecting your code and backing all the way out > to a trivial case (e.g. hard set a few output pins to 01010101 or some > such), you'll find as I did that the part just did not get > reprogrammed correctly. > > The problem is that the FPGA needs to have its configuration memory > cleared before starting a new download, and the JTAG configuration > inexplicably neglects to do this. Whether this is an oversight in the > Impact downloader and can be fixed in a subsequent release (I'm using > 4.2wP3.x), or whether it is an oversight in the chip design, I don't > know. > > What you have to do is this: before reprogramming the FPGA via JTAG, > you must pull the PROGRAM_BAR pin low (that clears the memory), and > then bring it back high (if you leave it low, Impact will give you an > error, saying the boundary-scan chain test failed). > > That you can't just use the JTAG pins to reprogram the part, and have > to do this little dance with the PROGRAM pin is a flat out bug in my > opinion. It should be fixed, or this workaround printed in 24-point > red letters in the user's manual. > > I sincerely hope this posting helps some future poor sap(s) from > wasting as much time as I did. > > -tdArticle: 47279
Uwe Bonnes wrote: > > Duane, what is your option to download the bitstream to the FPGA under Linux? > > I looked hard at running impact.exe under wine, but as impact probably uses > a windriver.sys file to access the parallel port, it seems not feasable > with wine. Err.. well I will have to hedge slightly on that one ;) Here at my office, pretty much all of the bitfile downloads I do are done via the PCI bus on PCI boards, using non-Xilinx tools. The ones I am using work fine on Linux. I had been doing some work at a customer's location, and they were using WebPack on NT, which is why I recently became interested in running WebPack and the ISE project manager (which is very similar to WebPack) under wine. At the customer site, I download using iMPACT on NT :( Oh well. The parallel port interface is pretty simple though. I have seen several postings in this newsgroup in the past about doing this under Linux. Here is one example, though I have not personally tried it: http://www.fpga-faq.com/FAQ_Pages/0028_Downloading_a_Bitstream_under_Linux.htm -- My real email is akamail.com@dclark (or something like that).Article: 47280
Depends. If Bruce is an experienced hardware designer, then he
can apply his experience and be quite successful working in VHDL
(there is a learning curve, but it is not insurmountable if you
have the hardware design background). However, learning hardware
design, VHDL and MP3 specs all at the same time is a huge task,
and one which I would assign a very low probability of success if
it must be done in a reasonable amount of time.
<RANT>
I strongly advocate learning hardware design before learning VHDL
as the basics are required whether you work in VHDL, schematics,
or stone and chisel. All too often these days, people are
learning only to program in VHDL and then assuming that they are
qualified to be hardware designers. All too often, I have to
clean up their messes. All too often, I have to deal with upset
managers who can't understand why it is cheaper to start over from
scratch than to patch up the garbage generated by these
neo-hardware designers.
</RANT>
Falk Brunner wrote:
> "Bruce" <bruce@bytes.co.za> schrieb im Newsbeitrag
> news:ee790ca.-1@WebX.sUN8CHnE...
> > I am a newcomer to VHDL and I need to design an MP3 decoder.
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> I dont think this two statements mix well.
>
> --
> MfG
> Falk
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47281
I believe Maxim and Dallas Semi both have something that will work for this.
Rick Filipkiewicz wrote:
> Ray Andraka wrote:
>
> > Not reliably. The HC7404 works because it is used as an amplifier, which can
> > be done with a simple inverter. An FPGA has too many gain stages between the
> > pins to be abused as an amplifier in an oscillator circuit. While it may work
> > on the bench, it will not reliably start and maintain the fundamental
> > frequency with variations in temp, process, and voltage. Why not use an
> > integrated xtal oscillator instead of a simple crystal? The costs are nearly
> > the same.
> >
>
> Do you happen to know if there's a 32.??Khz xtal osc. that uses sufficiently
> little power that it can run off a 3V coin cell ? or with some power-down mode ?
> The reason I ask is that I'd dearly like to replace the PIIX4 southbridge +
> CombiIO functions in an FPGA/CPLD and about the only thing that's hard is the real
> time clock. I've already got a CPLD on board so it could be replaced by a
> CoolRunner (II ?) to take the RTC function.
>
> Maybe this is just to perfectionist & I'll just bite the bullet and find a
> stand-alone PC-compatible RTC.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47282
If you have a spare pin on the FPGA, you can connect that to the /program
pin and then use the JTAG to first hit the program pin then reprogram.
Tony Dean wrote:
> I've just spent the last week in hell, baffled as to why my FPGA
> design was not working. Was I really THAT bad of a VHDL coder?
>
> To make a long and painful story short, it wasn't my fault. And it
> wasn't Synplicity's fault (sorry about that call to tech support). It
> is Xilinx's fault. I don't mean to bash Xilinx, as their products are
> great, but they blew this one.
>
> The problem:
> When using JTAG to configure a Spartan II FPGA (and perhaps Virtex
> too), the first configuration after power up will work, but subsequent
> ones will not.
>
> Worse, the re-configurations may APPEAR to work, because something did
> get downloaded, and the Impact programmer chirps "PROGRAM SUCCEEDED".
> But after 3 days of dissecting your code and backing all the way out
> to a trivial case (e.g. hard set a few output pins to 01010101 or some
> such), you'll find as I did that the part just did not get
> reprogrammed correctly.
>
> The problem is that the FPGA needs to have its configuration memory
> cleared before starting a new download, and the JTAG configuration
> inexplicably neglects to do this. Whether this is an oversight in the
> Impact downloader and can be fixed in a subsequent release (I'm using
> 4.2wP3.x), or whether it is an oversight in the chip design, I don't
> know.
>
> What you have to do is this: before reprogramming the FPGA via JTAG,
> you must pull the PROGRAM_BAR pin low (that clears the memory), and
> then bring it back high (if you leave it low, Impact will give you an
> error, saying the boundary-scan chain test failed).
>
> That you can't just use the JTAG pins to reprogram the part, and have
> to do this little dance with the PROGRAM pin is a flat out bug in my
> opinion. It should be fixed, or this workaround printed in 24-point
> red letters in the user's manual.
>
> I sincerely hope this posting helps some future poor sap(s) from
> wasting as much time as I did.
>
> -td
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47283"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag news:3D8DF226.2E87E41C@andraka.com... > If you have a spare pin on the FPGA, you can connect that to the /program > pin and then use the JTAG to first hit the program pin then reprogram. But this looks very much like a crude workaround. I would we carefull, since pulling PROGRAM to LOW will also kill (reset) the JTAG controller. I noticed this problem a long time ago and always did a manual reset when working with our demobaords. -- MfG FalkArticle: 47284
I've recently started to use Xilinx ISE 4.2 (I used to use Foundation 2.1) and I'm learning quite fast, but I still have some problems with Modelsim XE. Am I using it in a wrong way, or it's just an "abstract simulator" that doesn't care nothing about real (or at least, realistic) timing specifications of the device under test? For example, if I try to simulate a simple ADD16 from Xilinx standard library with a VirtexE device (speed grade -8), I get a 300 ps propagation delay with Modelsim. This is obviously wrong; if I run timing analyzer I get something like 10 ns, a lot more realistic (is it?). The question is simple: can I integrate timing analyzer and Modelsim in order to get realistic, graphical timing analysis? (just like I could do with Foundation 2.1 and post-fit simulation, by the way). -- LorenzoArticle: 47285
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> schrieb im Newsbeitrag news:xnmj9.74239$Hc7.617967@twister1.libero.it... > simulator" that doesn't care nothing about real (or at least, realistic) > timing specifications of the device under test? > > For example, if I try to simulate a simple ADD16 from Xilinx standard > library with a VirtexE device (speed grade -8), I get a 300 ps > propagation delay with Modelsim. This is obviously wrong; if I run > timing analyzer I get something like 10 ns, a lot more realistic (is > it?). It all depends on the simulation mode you are running. For a VHDL-Testbench for a FPGA designflow, you have these 4 simulation levels, which can be selected in the "Process view" window. a) behavioural VHDL, a plain functional simulation, every logic will have (almost) zero delay) b) post translate, dont know at all, very similar to post mapping c) post mapping, the delays of LUTs are embedded in the simulation, also clock_2_out times of FlipFlops etc. BUT routing delay is NOT accounted d) post Place & route, all delays are included in the simulation (can be seen as post mapping + routing delay simulation) > The question is simple: can I integrate timing analyzer and Modelsim in > order to get realistic, graphical timing analysis? (just like I could do > with Foundation 2.1 and post-fit simulation, by the way). Simply run a post place&rout simulation. But there was a discussion some time ago about the sense of a P&R simulation. If you have a strict synchronous design, you can get away with a plain behavioural simulation (which is MUCH faster) and let the timing analyzer figure out your max. frequency you design is capable of. -- MfG FalkArticle: 47286
Lorenzo Lutti wrote: > I've recently started to use Xilinx ISE 4.2 (I used to use Foundation > 2.1) and I'm learning quite fast, but I still have some problems with > Modelsim XE. Am I using it in a wrong way, or it's just an "abstract > simulator" that doesn't care nothing about real (or at least, realistic) > timing specifications of the device under test? > > For example, if I try to simulate a simple ADD16 from Xilinx standard > library with a VirtexE device (speed grade -8), I get a 300 ps > propagation delay with Modelsim. This is obviously wrong; if I run > timing analyzer I get something like 10 ns, a lot more realistic (is > it?). > > The question is simple: can I integrate timing analyzer and Modelsim in > order to get realistic, graphical timing analysis? (just like I could do > with Foundation 2.1 and post-fit simulation, by the way). > > -- > Lorenzo Lorenzo, To do a timing simulation you need: o A post MAP/PAR `gate' level netlist for your complete design. This is based on the `simprims' library. o an SDF timing back-annotation file to go with it [for post MAP this will not have any routing delays, just logic]. These 2 are produced by running NGDANNO on the .ncd file to get a .nga, followed by NGD2<VER|VHDL> to get the netlist & SDF. o Compiled `simprims'. o Compiled `Coregen' sim lib, if you have any Coregen cores. [+ of course your testbench]. I don't know if the last 2 are included with ModelSim XE, if not then doing it yourself it will probably blow the XXX line limit and slow down drastically. Onec you've glued this all together you set the clock period to what the timing analyser says should work, push the go button, and the simulation should pass all the same scripts you used for RTL. Remember to make sure that the simulator resolution is set right, 10ps or less. However full post route timing sim is pretty tedious and is generally regarded as unnecessary if (a) You've done a post-synth sim [or post-NGD]. (b) your timing constraints are accurate and comrehensive. (c) You haven't tripped over a hidden NGD/MAP/PAR/TRCE bug!. This happens, I found one only last November in 3.3i MAP that needed a post MAP sim and 3 hrs delving down into the netlist to find.Article: 47287
Tony Dean <td@emu.com> wrote: > The problem is that the FPGA needs to have its configuration memory > cleared before starting a new download, and the JTAG configuration > inexplicably neglects to do this. Whether this is an oversight in the > Impact downloader and can be fixed in a subsequent release (I'm using > 4.2wP3.x), or whether it is an oversight in the chip design, I don't > know. This might well be a bug, like you say, but there are certain issues that you should be aware of before jumping to conclusions. What you're describing seems to me to be a consequence of Xilinx's attempts at making the SpartanII partially reconfigurable. Indeed, you can imagine how it might be a problem when partially reconfiguring a chip for the config memory to be automatically cleared. However, I'm not sure how this should affect your chip if you are inputing a full bitstream, which should be reconfiguring the entire space and overwriting previous configuration data. > What you have to do is this: before reprogramming the FPGA via JTAG, > you must pull the PROGRAM_BAR pin low (that clears the memory), and > then bring it back high (if you leave it low, Impact will give you an > error, saying the boundary-scan chain test failed). This procedure is in fact documented in many places that speak of the configuration procedure, amongst others in the Spartan-II data sheet under the heading "Initiating Configuration", right next to a flow chart describing the proper configuration flow. I must admit, however, that few people need to know such details, and that it should have been taken care of elsewhere in the automated configuration flows, but there is always a fine line to walk between allowing the majority the easiest use of a product, and the minority to test its limits with a minimum of extra effort. Pierre-OlivierArticle: 47288
Are you loading the .sdf file and associating it with the top level entity when simulating. Brijesh Lorenzo Lutti wrote: > I've recently started to use Xilinx ISE 4.2 (I used to use Foundation > 2.1) and I'm learning quite fast, but I still have some problems with > Modelsim XE. Am I using it in a wrong way, or it's just an "abstract > simulator" that doesn't care nothing about real (or at least, realistic) > timing specifications of the device under test? > > For example, if I try to simulate a simple ADD16 from Xilinx standard > library with a VirtexE device (speed grade -8), I get a 300 ps > propagation delay with Modelsim. This is obviously wrong; if I run > timing analyzer I get something like 10 ns, a lot more realistic (is > it?). > > The question is simple: can I integrate timing analyzer and Modelsim in > order to get realistic, graphical timing analysis? (just like I could do > with Foundation 2.1 and post-fit simulation, by the way). > > -- > Lorenzo > >Article: 47289
While 65C is hot to touch, this is well within normal operating temperature. Here are some tests you could try, after re-checking that you dont have I/O contention (output connected to output). A) Power the board but dont configure the FPGA. It should be cold. B) Power the board but dont clock the FPGA. It should be cold. C) Create a dummy design that drives the outputs with alternating 0 and 1, but bulk of chip is empty. It should be cold to warm. If any of these run hot, you need to figure out why. For B and C, you could selectively disable output till you find out which one is having contention issues (if that is the problem) Philip On 19 Sep 2002 14:55:31 -0700, pierrotlafouine@hotmail.com (Pierre Lafrance) wrote: >Hi all >I respined a product, changing the old Xilinx XV-300 with a XCV-600E. >Of course, I had to change voltage regulator from 2.5 to 1.8 volts, >and few 5 volts CPLD to 3.3v. > >The problem is : the XCV-600E overheat, and 1 of the prototype just >died. >I tried to find any hardware signal that would exceed voltage but >couldn't. Hardware seems to be just fine. I suspect the chips itself >to overheat. I just put a heatseak temporarly, but would like to >solve the problem if I can. > >Simulation with XPower estimate the chips temperature to be 50C, but I >measure up to 65C. > >The disign use 75% of BRAM, and 75% of FF of the XCV-600E. >Clock is 82MHz. > >Anybody experienced overheat with 600E ? > >Cheers ! > >Pierre Philip Freidin FliptronicsArticle: 47290
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> wrote: >I've recently started to use Xilinx ISE 4.2 (I used to use Foundation >2.1) and I'm learning quite fast, but I still have some problems with >Modelsim XE. Am I using it in a wrong way, or it's just an "abstract >simulator" that doesn't care nothing about real (or at least, realistic) >timing specifications of the device under test? > >For example, if I try to simulate a simple ADD16 from Xilinx standard >library with a VirtexE device (speed grade -8), I get a 300 ps >propagation delay with Modelsim. This is obviously wrong; if I run >timing analyzer I get something like 10 ns, a lot more realistic (is >it?). > >The question is simple: can I integrate timing analyzer and Modelsim in >order to get realistic, graphical timing analysis? (just like I could do >with Foundation 2.1 and post-fit simulation, by the way). Yes this is possible and routinely done. You need to annotate the delays from P&R results into your gate level simulations to see actual timing. When you run P&R you get a fully mapped, placed & routed netlist and an associated delay file (usually a SDF file). You should read both of these into your simulator to do back-annotated simulations. Muzaffer FPGA/ASIC DSP Design/Verification Consulting http://www.dspia.comArticle: 47291
Does anybody knows of any online M.Sc level engineering programs from a reputable university? My area of interest may be Analog/digital IC design, ASIC, and embedded signal processor. Thanks. Kelvin ---------------------------------------------------- "Simon" <news@gornall.net> wrote in message news:3D8F5BB0.3010104@gornall.net... > Boris wrote: > > Hello SH7, > > > > Thanks for your reply. My HDL skill level is relatively limited... I > > did a few small Verilog projects years back, and now have taken some > > interest in VHDL; I've went over a few tutorials and think need to get > > my hands on something and do some experimentation. > > > > I've looked at the boards you suggested, and the Xilinx board seems > > interesting as it has clock, LCD, LEDs, switches (?), etc. I think > > this stuff might facilitate doing some learning development. On the > > other hand, the Cypress seems like a steal because it includes the > > book too. > > > > Incidentally, on both boards, are the CPLDs/FPGAs actually mounted on? > > Not that its a problem, but I suppose it just means some extra is > > needed. > > > > Has anyone had any experience with Vendor or "for profit" training? > > I've been skeptical about how much you could actually learn in three > > to five days, but I won't be closed minded until given reason to be. > > :-) > > > > Thanks, > > > > Boris > > > > spam_hater_7@email.com (Spam Hater) wrote in message news:<3d8c95c1.1188082@64.164.98.7>... > > > >>Hi Boris, > >> > >>What is your current HDL skill level? > >> > >>If you're a beginner, I'd suggest the Cypress Warp ISR kit. Includes > >>software, a demo board, and a good introductory text. CY3620R62 is > >>their part number. (I'm currently designing an add-on board for their > >>demo board to make it more useful.) > >> > >>If you're more advanced, I recommend the SpartanII evaluation kit from > >>Insight Electronics. And the book "The Designer's Guide to VHDL by > >>Peter J. Ashenden." > >> > >>There are a few good tutorials on the net. A google search will turn > >>them up. > >> > >>Best of Luck. > >> > >>SH7 > >> > >> > >>On 20 Sep 2002 20:20:30 -0700, boris@optimumtrainer.com (Boris) wrote: > >> > >> > >>>I'm interested in some VHDL training to bring my design skills back up > >>>to date. I'm considering either formal and self-study. > >>> > >>>Which formal (seminar, vendor-based, lecture, online college...) > >>>courses have people had success with? I'm not in a major center so I > >>>would have to travel to attend, making an informed decision even more > >>>important. > >>> > >>>Also, as far as self-study material, what material have people found > >>>most useful. I've heard that the IEEE VHDL self-study course was > >>>good, but, was told that it was discontinued by the IEEE. > > I was looking recently at the (http://www.sli-institute.ac.uk/) > distance-learning course, which can ultimately lead to an MSc, if you > want. I've decided to wait and see what MIT give away on the 30th > September (when their open-courseware site at web.mit.edu goes online.) > > MIT are promising to have all course lectures/notes/whatever available > for anyone online as a philanthropic exercise in getting the 'net back > to its' roots. It's going to take 10 years though, they estimate, so > we'll have to see what's available from the end of the month. > > Simon. >Article: 47292
"Frank Adalater" <localfun66@hotmail.com> wrote in message news:<ami2co$5pb3f$1@ID-34826.news.dfncis.de>... > Hi, > > i want to take a look at the fpga systems to learn something more about. So > I want to buy a development package but they are all so expensive. Isnīt > there any cheap development package where i donīt to spent so much money or > maybe a computer simulation of such an fpga chip? > It is often less expensive to get started with CPLDs instead of FPGAs. Although they are internally different, the design flows are similar and you use the same tools (e.g. WebPack or Quartus/Max Plus II). You might be interested in the boards at http://www.al-williams.com/pldhome.htm (one for Xilinx and one for Altera). Also, be sure to read the free tutorials at http://tutor.al-williams.com -- there are several for Xilinx and one for Altera (more to come as I can get to them). Al Williams AWCArticle: 47293
I have seen the same exact behaviour on XCV1000E while using JTAG for the second time after power-up. I first thought, I was doing something wrong but I figured out that even though the software reports a successful programming, it is not. Outputs seem locked in a state where they are alternatively pulled up/down. Never really bathered to report this to Xilinx as JTAG is not the way to go for multiple programming sequences in general. It is a practical way to work-around a too small serial EEprom ;) Dali Tony Dean wrote: > I've just spent the last week in hell, baffled as to why my FPGA > design was not working. Was I really THAT bad of a VHDL coder? > > To make a long and painful story short, it wasn't my fault. And it > wasn't Synplicity's fault (sorry about that call to tech support). It > is Xilinx's fault. I don't mean to bash Xilinx, as their products are > great, but they blew this one. > > The problem: > When using JTAG to configure a Spartan II FPGA (and perhaps Virtex > too), the first configuration after power up will work, but subsequent > ones will not. > > Worse, the re-configurations may APPEAR to work, because something did > get downloaded, and the Impact programmer chirps "PROGRAM SUCCEEDED". > But after 3 days of dissecting your code and backing all the way out > to a trivial case (e.g. hard set a few output pins to 01010101 or some > such), you'll find as I did that the part just did not get > reprogrammed correctly. > > The problem is that the FPGA needs to have its configuration memory > cleared before starting a new download, and the JTAG configuration > inexplicably neglects to do this. Whether this is an oversight in the > Impact downloader and can be fixed in a subsequent release (I'm using > 4.2wP3.x), or whether it is an oversight in the chip design, I don't > know. > > What you have to do is this: before reprogramming the FPGA via JTAG, > you must pull the PROGRAM_BAR pin low (that clears the memory), and > then bring it back high (if you leave it low, Impact will give you an > error, saying the boundary-scan chain test failed). > > That you can't just use the JTAG pins to reprogram the part, and have > to do this little dance with the PROGRAM pin is a flat out bug in my > opinion. It should be fixed, or this workaround printed in 24-point > red letters in the user's manual. > > I sincerely hope this posting helps some future poor sap(s) from > wasting as much time as I did. > > -tdArticle: 47294
The costs are the same? Au contrair mon friar. According to my price book the crystal by itself is about 50 cents and the full up oscillator is $1.50, thats a dollar difference. So if is a low quantity, $1000 Vertex kinda thing, buy the can, but its high volume and real price sensitive, engineer and test your own. Ray Andraka <ray@andraka.com> wrote in message news:<3D8C886A.5EC5478C@andraka.com>... > Not reliably. The HC7404 works because it is used as an amplifier, which can > be done with a simple inverter. An FPGA has too many gain stages between the > pins to be abused as an amplifier in an oscillator circuit. While it may work > on the bench, it will not reliably start and maintain the fundamental > frequency with variations in temp, process, and voltage. Why not use an > integrated xtal oscillator instead of a simple crystal? The costs are nearly > the same. > > Dan wrote: > > > Hello, > > > > My design has a common low cost crystal oscillator. It uses two inverters > > HC7404 and a few caps & two res. > > > > Can the inverter chip be replace by the FPGA. Can I simply put the crystal > > across two IO pins ( I am using a Spartan IIE ) and configurae them as an > > inverter ( while keeping the caps and the res(s) ) ? > > > > Sincerely > > Dan > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 47295
Hello, I am interested in integrating a virtual cpu that can take instructions from a pc and then compute them within the fpga, then return the computed result back to the computer. I would like to know if anyone could suggest a fpga evaluation kit that would be ideal for this situation. Thank you.Article: 47296
Yes, I have experienced a very similar problem. To program my Spartan 2 FPGA properly via JTAG I have to cycle the power first. And yes it did have me fooled for a while, parts of the design would work but other parts did not. I found an SRL16E init = X"0001", output fed back to input was a good test case. I went through the exercise of opening a webcase with Xilinx. I was impressed with the very fast response but we did not solve the problem. I was told that I should not be seeing this behaviour. So it would be interesting to know if this is a bug/feature or not...Article: 47297
Does anybody knows of any online M.Sc level engineering programs from a reputable university? My area of interest may be Analog/digital IC design, ASIC, and embedded signal processor. Thanks. Kelvin ---------------------------------------------------- "Simon" <news@gornall.net> wrote in message news:3D8F5BB0.3010104@gornall.net... > Boris wrote: > > Hello SH7, > > > > Thanks for your reply. My HDL skill level is relatively limited... I > > did a few small Verilog projects years back, and now have taken some > > interest in VHDL; I've went over a few tutorials and think need to get > > my hands on something and do some experimentation. > > > > I've looked at the boards you suggested, and the Xilinx board seems > > interesting as it has clock, LCD, LEDs, switches (?), etc. I think > > this stuff might facilitate doing some learning development. On the > > other hand, the Cypress seems like a steal because it includes the > > book too. > > > > Incidentally, on both boards, are the CPLDs/FPGAs actually mounted on? > > Not that its a problem, but I suppose it just means some extra is > > needed. > > > > Has anyone had any experience with Vendor or "for profit" training? > > I've been skeptical about how much you could actually learn in three > > to five days, but I won't be closed minded until given reason to be. > > :-) > > > > Thanks, > > > > Boris > > > > spam_hater_7@email.com (Spam Hater) wrote in message news:<3d8c95c1.1188082@64.164.98.7>... > > > >>Hi Boris, > >> > >>What is your current HDL skill level? > >> > >>If you're a beginner, I'd suggest the Cypress Warp ISR kit. Includes > >>software, a demo board, and a good introductory text. CY3620R62 is > >>their part number. (I'm currently designing an add-on board for their > >>demo board to make it more useful.) > >> > >>If you're more advanced, I recommend the SpartanII evaluation kit from > >>Insight Electronics. And the book "The Designer's Guide to VHDL by > >>Peter J. Ashenden." > >> > >>There are a few good tutorials on the net. A google search will turn > >>them up. > >> > >>Best of Luck. > >> > >>SH7 > >> > >> > >>On 20 Sep 2002 20:20:30 -0700, boris@optimumtrainer.com (Boris) wrote: > >> > >> > >>>I'm interested in some VHDL training to bring my design skills back up > >>>to date. I'm considering either formal and self-study. > >>> > >>>Which formal (seminar, vendor-based, lecture, online college...) > >>>courses have people had success with? I'm not in a major center so I > >>>would have to travel to attend, making an informed decision even more > >>>important. > >>> > >>>Also, as far as self-study material, what material have people found > >>>most useful. I've heard that the IEEE VHDL self-study course was > >>>good, but, was told that it was discontinued by the IEEE. > > I was looking recently at the (http://www.sli-institute.ac.uk/) > distance-learning course, which can ultimately lead to an MSc, if you > want. I've decided to wait and see what MIT give away on the 30th > September (when their open-courseware site at web.mit.edu goes online.) > > MIT are promising to have all course lectures/notes/whatever available > for anyone online as a philanthropic exercise in getting the 'net back > to its' roots. It's going to take 10 years though, they estimate, so > we'll have to see what's available from the end of the month. > > Simon. >Article: 47298
I want to simulate the Xilinx RAM16x1D
using Modelsim, but all Writes fail.
After writing to the RAM the Data in the Ram is invalid (DPO='X').
I get Timing Errors:
# ** Warning: */RAM16X1D SETUP High VIOLATION ON WE WITH RESPECT TO WCLK;
# Expected := 0.01 ns; Observed := 0 ns; At : 20 ns
# Time: 20 ns Iteration: 3 Instance: /test_sram/prg_ram
But I like to do just funktional simulation.
So Setup und Hold times should not be checked
and the Functional Model should not rely on any Setup or Hold Times
Maybe I use the wrong LIBs?
Can anyone help?
thanks peter
Here is my VHDL source:
----------------------------------------------------------------
----------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
use UNISIM.all;
entity test_sram is
end test_sram;
architecture Behavioral of test_sram is
----------------------------------------------------------------
component RAM16X1D
generic (
TimingChecksOn: Boolean := TRUE;
InstancePath: STRING := "*";
Xon: Boolean := True;
MsgOn: Boolean := False);
port (
WE : in std_logic;
D : in std_logic;
WCLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
SPO : out std_logic;
DPO : out std_logic
);
end component;
signal WE : std_logic;
signal D: std_logic;
signal CLK:std_logic;
signal A:std_logic_vector(3 downto 0);
signal DPA:std_logic_vector(3 downto 0);
signal DPO:std_logic;
signal SPO:std_logic;
begin
----------------------------------------------------------------
PRG_RAM: RAM16X1D
generic map(MsgOn => True)
port map (
WE => WE,
D => D,
WCLK =>CLK,
A0 =>A(0),
A1 =>A(1),
A2 =>A(2),
A3 =>A(3),
DPRA0 => DPA(0),
DPRA1 => DPA(1),
DPRA2 => DPA(2),
DPRA3 => DPA(3),
SPO => SPO,
DPO => DPO);
process
begin
wait for 5 ns;
CLK <='0';
wait for 5 ns;
CLK <='1';
end process;
process
begin
D<='1';
A <="0001";
DPA<="0000";
WE<='0';
wait until CLK'event and CLK='1';
wait until CLK'event and CLK='1';
-- Write '1' to Location 1
D<='1';
WE<='1'; -- 1 auf adr 1 schreiben, Adr 0 lesen
wait until CLK'event and CLK='1';
WE<='0';
wait until CLK'event and CLK='1';
-- here I get a 'X' as SPO !!!???
wait until CLK'event and CLK='1';
-- Read Location 1
-- Here I get 'X' on DPO
-- but I want to see here '1'
DPA<="0001";
wait until CLK'event and CLK='1';
wait until CLK'event and CLK='1';
wait;
end process;
end Behavioral;
Article: 47299
On Mon, 23 Sep 2002 11:31:17 +0200, "itsme" <itsme@gmx.de> wrote:
>I want to simulate the Xilinx RAM16x1D
>using Modelsim, but all Writes fail.
>After writing to the RAM the Data in the Ram is invalid (DPO='X').
>I get Timing Errors:
>
># ** Warning: */RAM16X1D SETUP High VIOLATION ON WE WITH RESPECT TO WCLK;
># Expected := 0.01 ns; Observed := 0 ns; At : 20 ns
># Time: 20 ns Iteration: 3 Instance: /test_sram/prg_ram
>
>But I like to do just funktional simulation.
>So Setup und Hold times should not be checked
>and the Functional Model should not rely on any Setup or Hold Times
>Maybe I use the wrong LIBs?
>Can anyone help?
Hi Peter,
You can do a number of things to fix this. The best two (IMO) are:
1. Run vsim with the +notimingchecks option.
2. Instantiate your rams as:
PRG_RAM: RAM16X1D
generic map(
TimingChecksOn => FALSE,
MsgOn => True
)
port map (
WE => WE,
...
You will probably also want 'translate_off' pragmas around the generic
map.
Regards,
Allan.
>thanks peter
>
>Here is my VHDL source:
>----------------------------------------------------------------
>----------------------------------------------------------------
>LIBRARY ieee;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
>
>library unisim;
> use UNISIM.all;
>
>entity test_sram is
>end test_sram;
>
>architecture Behavioral of test_sram is
>
>----------------------------------------------------------------
>component RAM16X1D
> generic (
> TimingChecksOn: Boolean := TRUE;
> InstancePath: STRING := "*";
> Xon: Boolean := True;
> MsgOn: Boolean := False);
> port (
> WE : in std_logic;
> D : in std_logic;
> WCLK : in std_logic;
> A0 : in std_logic;
> A1 : in std_logic;
> A2 : in std_logic;
> A3 : in std_logic;
> DPRA0 : in std_logic;
> DPRA1 : in std_logic;
> DPRA2 : in std_logic;
> DPRA3 : in std_logic;
> SPO : out std_logic;
> DPO : out std_logic
> );
>end component;
>
>signal WE : std_logic;
>signal D: std_logic;
>signal CLK:std_logic;
>signal A:std_logic_vector(3 downto 0);
>signal DPA:std_logic_vector(3 downto 0);
>signal DPO:std_logic;
>signal SPO:std_logic;
>
>
>begin
>
>
>----------------------------------------------------------------
> PRG_RAM: RAM16X1D
> generic map(MsgOn => True)
>
> port map (
> WE => WE,
> D => D,
> WCLK =>CLK,
> A0 =>A(0),
> A1 =>A(1),
> A2 =>A(2),
> A3 =>A(3),
> DPRA0 => DPA(0),
> DPRA1 => DPA(1),
> DPRA2 => DPA(2),
> DPRA3 => DPA(3),
> SPO => SPO,
> DPO => DPO);
>
>process
>begin
> wait for 5 ns;
> CLK <='0';
> wait for 5 ns;
> CLK <='1';
>end process;
>
>process
>begin
> D<='1';
> A <="0001";
> DPA<="0000";
> WE<='0';
> wait until CLK'event and CLK='1';
> wait until CLK'event and CLK='1';
>
> -- Write '1' to Location 1
> D<='1';
> WE<='1'; -- 1 auf adr 1 schreiben, Adr 0 lesen
> wait until CLK'event and CLK='1';
> WE<='0';
> wait until CLK'event and CLK='1';
> -- here I get a 'X' as SPO !!!???
> wait until CLK'event and CLK='1';
>
> -- Read Location 1
> -- Here I get 'X' on DPO
> -- but I want to see here '1'
> DPA<="0001";
> wait until CLK'event and CLK='1';
> wait until CLK'event and CLK='1';
>
> wait;
>end process;
>
>end Behavioral;
>
>
>
>
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