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We use that quite a bit to reduce fanout on clock enable to get the performance up. We more or less try
to avoid using clock enables except on small slices of the design, then the ce becomes locally generated
and controlled and the design can smoke (sometimes almost literally, looks like we've got another heatsink
with fans design going now). As you point out, it can also save lots of routing, which for really high
fanout nets can kill the timing unbelievably.
Marc Randolph wrote:
> newman5382@aol.com (newman) wrote in message news:<e6038423.0206241853.57847ecf@posting.google.com>...
>
> > Ray Andraka <ray@andraka.com> wrote in message news:<3D175C91.A17D20D6@andraka.com>...
> > > Nope, non that I am aware of. The clock nets are designed for low skew, but not
> > > necessarily low delay. I suspect even if you coerced the tools into letting you abuse
> > > the global clock distribution that you would find the delay unacceptable. The clock
> > > nets are wired just to the flip-flop clock inputs with an ability to get off the clock
> > > net onto the general routing.
> > >
<snip>
>
> BTW, Ray, thanks for the ideas on the clock enable. I don't have
> trouble meeting timing with it, but it does chew up routing resources
> unnecessarily.
>
> Marc
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44651
Not necessarily. It is quite possible in current FPGAs to put a design in there that will dissipate over 20W. We've got one board on the bench here with a pair of V2000e's on it that are dissipating about 14W each. It is internally clocking at 160 MHz, and uses about 90% of the flip-flops and LUTs (check that in
the power estimator spreadsheet) We're working on another design using a 2V6000 that preliminary power estimates are putting at well over 20W. I have soldering irons in the lab that dissipate less power than these designs do. Needless to say, the designs won't run very long without heatsinks and a healthy
airflow. And yes, they will leave the part number on your finger if you tough them when running without a heatsink, they also turn boards brown that way. With a socket-7 type fan cooler glued to the top of each, they run quite happily.
sunny wrote:
> if the device gets that hot something is wrong.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44652
Use the IOB registers. Then all the parallel bits have nearly identical
delays (tens of ps max differences) to the clock.
spyng wrote:
> hi,
> any one know is it possible to control the skew betwen different
> signal on Virtex2. for i.e, between i_data[0], i_data[1]
> ....i_data[7].
>
> from what I understand NET "i_data[*]" MAXSKEW = 4 ns, will only
> constraint the skew of the individual signal.
>
> the problem I have is that my external data(5 bit) and clock is not
> align properly (don't ask me why, I have try that), so we are trying
> to sample the input data with 8 different phase of the internal clock
> and then determind which phase is the best to use.
>
> so there will be 8 set of input data sample register and they can not
> be in the IOB. But we will have to make sure that all the 5 bit input
> data have the same delay to all the 8 set of data sample reg.
>
> Xilinx actually have a app note on this (xapp 255), but I am not
> convince that they are able to control the skew between different
> signal. correct me if I am wrong.
>
> any help?
> thanks
> pyng
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44653Falk Brunner wrote: > "Steven Elzinga" <steven.elzinga@xilinx.com> schrieb im Newsbeitrag > news:3D13B101.19B27843@xilinx.com... > >> Faulk, >> >> See comments below: If you have successfully created EDIF files for >> modules B, C and D and successfully instantiated them as black >> boxes then all that is required is to have all of the EDIF files in >> the same directory when NGDBuild is run. NGDBuild will recognize >> the missing components in each EDIF file as it is read in. In this >> case the default behavior of NGDBuild is to look in the project >> directory to fill in the missing components with some type of >> netlist (EDIF, NGO, NGC). If NGDBuild can not do this then it will >> fail with an unexpanded error meaing it can not expand (translate) >> the component (which is a black box) that is not defined. > > > This was the solution!!! Thanks a lot. Just a very minor nitpick. It is not necessary for the black box files to be in the same directory as the top level. I prefer to leave them in the directories where they are put by Synplify, and point ngdbuild to them with multiple "-sd" parameters. Then I know I am always using the latest ones. -- My real email is akamail.com@dclark (or something like that).Article: 44654
Hi the quartus II tell me that is the design can run at 22.04 Mhz and I use an 20Mhz clock if this timing will change while the device getting too hot? about the cause of the hot, I think it is because I use alot of ESB in APEX to construct 8KB cache for my design(a microprocessor-- nnarm) ae <> wrote in message news:<ee7785a.3@WebX.sUN8CHnE>... > On another note: even if your device is not operating at an abnormal temperature, it *is* possible that for a tightly timed design you could actually have a problem at 'normal' temperatures. If you find that the heat dissipation you are creating is not a problem then you might want to check to see if you are close in timing... if so, try nudgind down the close constraints a little, by a couple nanoseconds maybe.Article: 44655
Duane Clark wrote:
>
>
> Just a very minor nitpick. It is not necessary for the black box files
> to be in the same directory as the top level. I prefer to leave them in
> the directories where they are put by Synplify, and point ngdbuild to
> them with multiple "-sd" parameters. Then I know I am always using the
> latest ones.
From ISE's GUI, that will be called Macro Search Path.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44656I can obviously not sepak for Altera, but I cannot imagine that any modern FPGA will have high power consumption when driven by a 20 MHz clock. That's something we did ten years ago,at 5 V, and no thought of a heatsink. You have never quantified what you mean by "hot". Remember, I gave you the fingertip thermometer... :-) Peter Alfke, Xilinx Applicatins ================== ssy wrote: > Hi > > the quartus II tell me that is the design can run at 22.04 Mhz and I > use an 20Mhz clock > if this timing will change while the device getting too hot? > > about the cause of the hot, I think it is because I use alot of ESB in > APEX to construct 8KB cache for my design(a microprocessor-- nnarm) > > ae <> wrote in message news:<ee7785a.3@WebX.sUN8CHnE>... > > On another note: even if your device is not operating at an abnormal > temperature, it *is* possible that for a tightly timed design you > could actually have a problem at 'normal' temperatures. If you find > that the heat dissipation you are creating is not a problem then you > might want to check to see if you are close in timing... if so, try > nudgind down the close constraints a little, by a couple nanoseconds > maybe.Article: 44657
Ray: What I did was a standard X4 muldiplier (P77&P82) provided by the Spartan-II handbook, it worked. Third X2 is in the third DLL place (P185) but I connected the output from X4 to P185 with a wire. It seemed the third DLL isn't work. I like this is because I need a single 100MHz clock to test an ASIC. My function generator maximum output 16MHz. Also I want to know where can I get a 80MHz clean clock out of 16MHz too? Synchronization among X2 X4 & X8 is insignificant. -- Best Regards, ----------------------------------------------------------------- Xu Qijun Engineer OKI Techno Centre (S) Pte Ltd Tel: 6770-7081 Fax: 6779-2382 Email: qijun677@oki.com "Ray Andraka" <ray@andraka.com> wrote in message news:3D17EB84.987B90B1@andraka.com... > Min frequency for the DLL input is 25 MHz for reliable operation. That falls > out from the length of the delay line used in there. Additionally, Xilinx does > not recommend cascading more than 2 DLLs because each adds jitter, and more than > 2 in a line can lead to problems with excessive jitter in the last one, although > if you keep your power supply clean, the input clock with low jitter and don't > switch to many single ended I/O on the same bank as the clock input, you can > probably get away with a cascade of 3. > > The placer can figure out how to put the DLLs if they are connected to do a > clockx4. Anything more than that you will have to either place in the > floorplanner, in the UCF file or in the source using LOC constraints because the > placer can't figure out how to put them. > > XU QIJUN wrote: > > > I could make it with 16MHz and times 4, but 8X is problematic, > > > > -- > > Best Regards, > > ----------------------------------------------------------------- > > Xu Qijun > > Engineer > > OKI Techno Centre (S) Pte Ltd > > Tel: 6770-7081 Fax: 6779-2382 > > Email: qijun677@oki.com > > "XU QIJUN" <qijun677@oki.com> wrote in message > > news:3d12919d$1@news.starhub.net.sg... > > > Hi, > > > > > > I am using a Spartan-II 100K to do some experiments on clock > > multiplication. > > > I successfully made a X2 and X4, then problem occurs when I coded one > > extra > > > DLL to make it 8. Following is the bug, > > > Whats your comments? > > > > > > ERROR:Place:1726 - Could not find an automatic placement for the following > > > components: > > > CLKIN of type GCLK IOB is placed at P77. > > > dll2x of type DLL is unplaced. > > > clk2xg of type GCLK BUFFER is unplaced. > > > dll4x of type DLL is unplaced. > > > clk4xg of type GCLK BUFFER is unplaced. > > > dll8x of type DLL is unplaced. > > > clk8xg of type GCLK BUFFER is unplaced. > > > lckpad of type GCLK BUFFER is unplaced. > > > ERROR:Place:1727 - Xilinx requires using locate constraints to preplace > > such > > > connected GCLK/GCLKIO/DLL components. > > > Total REAL time to Placer completion: 2 secs > > > Total CPU time to Placer completion: 1 secs > > > > > > ----------------------------------------------------------------- > > > > > > Following are the codes: > > > > > > module dll_standard (CLKIN, CLK2X, CLK4X, CLK8X, LOCKED); > > > input CLKIN; > > > output CLK2X, CLK4X, CLK8X, LOCKED; > > > > > > wire RESET; > > > wire CLKIN_w, RESET_w, CLK2X_dll, CLK4X_dll, LOCKED2X, LOCKED4X; > > > wire LOCKED2X_delay, RESET4X; > > > wire LOCKED4X_delay, RESET8X; > > > wire logic1; > > > assign RESET = 1'b0; > > > > > > assign logic1 = 1'b1; > > > > > > assign CLKIN_w = CLKIN; > > > assign RESET = RESET_w; > > > > > > CLKDLL dll2x (.CLKIN(CLKIN_w), .CLKFB(CLK2X), .RST(RESET_w), > > > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > > > .CLK2X(CLK2X_dll), .CLKDV(), .LOCKED(LOCKED2X)); > > > BUFG clk2xg (.I(CLK2X_dll), .O(CLK2X)); > > > SRL16 rstsrl (.D(LOCKED2X), .CLK(CLK2X), .Q(LOCKED2X_delay), > > > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1)); > > > assign RESET4X = !LOCKED2X_delay; > > > > > > CLKDLL dll4x (.CLKIN(CLK2X), .CLKFB(CLK4X), .RST(RESET4X), > > > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > > > .CLK2X(CLK4X_dll), .CLKDV(), .LOCKED(LOCKED4X)); > > > BUFG clk4xg (.I(CLK4X_dll), .O(CLK4X)); > > > SRL16 rstsr2 (.D(LOCKED4X), .CLK(CLK4X), .Q(LOCKED4X_delay), > > > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1)); > > > assign RESET8X = !LOCKED4X_delay; > > > // assign CLK4X_B = ~ CLK4X; > > > > > > CLKDLL dll8x (.CLKIN(CLK4X), .CLKFB(CLK8X), .RST(RESET8X), > > > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > > > .CLK2X(CLK8X_dll), .CLKDV(), .LOCKED(LOCKED_dll)); > > > BUFG clk8xg (.I(CLK8X_dll), .O(CLK8X)); > > > > > > BUFG lckpad (.I(LOCKED_dll), .O(LOCKED)); > > > > > > endmodule > > > > > > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 44658
Synchronization is not the issue. Jitter is. If the jitter is too much, the
DLL will fail to lock. Use an 80 MHz crystal and divide down rather than trying
to multiply up.
XU QIJUN wrote:
> Ray:
>
> What I did was a standard X4 muldiplier (P77&P82) provided by the Spartan-II
> handbook,
> it worked. Third X2 is in the third DLL place (P185) but I connected the
> output from X4 to P185
> with a wire. It seemed the third DLL isn't work. I like this is because I
> need a single 100MHz clock
> to test an ASIC. My function generator maximum output 16MHz.
> Also I want to know where can I get a 80MHz clean clock out of 16MHz too?
> Synchronization
> among X2 X4 & X8 is insignificant.
>
> --
> Best Regards,
> -----------------------------------------------------------------
> Xu Qijun
> Engineer
> OKI Techno Centre (S) Pte Ltd
> Tel: 6770-7081 Fax: 6779-2382
> Email: qijun677@oki.com
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3D17EB84.987B90B1@andraka.com...
> > Min frequency for the DLL input is 25 MHz for reliable operation. That
> falls
> > out from the length of the delay line used in there. Additionally, Xilinx
> does
> > not recommend cascading more than 2 DLLs because each adds jitter, and
> more than
> > 2 in a line can lead to problems with excessive jitter in the last one,
> although
> > if you keep your power supply clean, the input clock with low jitter and
> don't
> > switch to many single ended I/O on the same bank as the clock input, you
> can
> > probably get away with a cascade of 3.
> >
> > The placer can figure out how to put the DLLs if they are connected to do
> a
> > clockx4. Anything more than that you will have to either place in the
> > floorplanner, in the UCF file or in the source using LOC constraints
> because the
> > placer can't figure out how to put them.
> >
> > XU QIJUN wrote:
> >
> > > I could make it with 16MHz and times 4, but 8X is problematic,
> > >
> > > --
> > > Best Regards,
> > > -----------------------------------------------------------------
> > > Xu Qijun
> > > Engineer
> > > OKI Techno Centre (S) Pte Ltd
> > > Tel: 6770-7081 Fax: 6779-2382
> > > Email: qijun677@oki.com
> > > "XU QIJUN" <qijun677@oki.com> wrote in message
> > > news:3d12919d$1@news.starhub.net.sg...
> > > > Hi,
> > > >
> > > > I am using a Spartan-II 100K to do some experiments on clock
> > > multiplication.
> > > > I successfully made a X2 and X4, then problem occurs when I coded one
> > > extra
> > > > DLL to make it 8. Following is the bug,
> > > > Whats your comments?
> > > >
> > > > ERROR:Place:1726 - Could not find an automatic placement for the
> following
> > > > components:
> > > > CLKIN of type GCLK IOB is placed at P77.
> > > > dll2x of type DLL is unplaced.
> > > > clk2xg of type GCLK BUFFER is unplaced.
> > > > dll4x of type DLL is unplaced.
> > > > clk4xg of type GCLK BUFFER is unplaced.
> > > > dll8x of type DLL is unplaced.
> > > > clk8xg of type GCLK BUFFER is unplaced.
> > > > lckpad of type GCLK BUFFER is unplaced.
> > > > ERROR:Place:1727 - Xilinx requires using locate constraints to
> preplace
> > > such
> > > > connected GCLK/GCLKIO/DLL components.
> > > > Total REAL time to Placer completion: 2 secs
> > > > Total CPU time to Placer completion: 1 secs
> > > >
> > > > -----------------------------------------------------------------
> > > >
> > > > Following are the codes:
> > > >
> > > > module dll_standard (CLKIN, CLK2X, CLK4X, CLK8X, LOCKED);
> > > > input CLKIN;
> > > > output CLK2X, CLK4X, CLK8X, LOCKED;
> > > >
> > > > wire RESET;
> > > > wire CLKIN_w, RESET_w, CLK2X_dll, CLK4X_dll, LOCKED2X, LOCKED4X;
> > > > wire LOCKED2X_delay, RESET4X;
> > > > wire LOCKED4X_delay, RESET8X;
> > > > wire logic1;
> > > > assign RESET = 1'b0;
> > > >
> > > > assign logic1 = 1'b1;
> > > >
> > > > assign CLKIN_w = CLKIN;
> > > > assign RESET = RESET_w;
> > > >
> > > > CLKDLL dll2x (.CLKIN(CLKIN_w), .CLKFB(CLK2X), .RST(RESET_w),
> > > > .CLK0(), .CLK90(), .CLK180(), .CLK270(),
> > > > .CLK2X(CLK2X_dll), .CLKDV(), .LOCKED(LOCKED2X));
> > > > BUFG clk2xg (.I(CLK2X_dll), .O(CLK2X));
> > > > SRL16 rstsrl (.D(LOCKED2X), .CLK(CLK2X), .Q(LOCKED2X_delay),
> > > > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1));
> > > > assign RESET4X = !LOCKED2X_delay;
> > > >
> > > > CLKDLL dll4x (.CLKIN(CLK2X), .CLKFB(CLK4X), .RST(RESET4X),
> > > > .CLK0(), .CLK90(), .CLK180(), .CLK270(),
> > > > .CLK2X(CLK4X_dll), .CLKDV(), .LOCKED(LOCKED4X));
> > > > BUFG clk4xg (.I(CLK4X_dll), .O(CLK4X));
> > > > SRL16 rstsr2 (.D(LOCKED4X), .CLK(CLK4X), .Q(LOCKED4X_delay),
> > > > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1));
> > > > assign RESET8X = !LOCKED4X_delay;
> > > > // assign CLK4X_B = ~ CLK4X;
> > > >
> > > > CLKDLL dll8x (.CLKIN(CLK4X), .CLKFB(CLK8X), .RST(RESET8X),
> > > > .CLK0(), .CLK90(), .CLK180(), .CLK270(),
> > > > .CLK2X(CLK8X_dll), .CLKDV(), .LOCKED(LOCKED_dll));
> > > > BUFG clk8xg (.I(CLK8X_dll), .O(CLK8X));
> > > >
> > > > BUFG lckpad (.I(LOCKED_dll), .O(LOCKED));
> > > >
> > > > endmodule
> > > >
> > > >
> > > >
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44659I'm going with the guy thats saying something is wrong. Check I/O's to make sure that you aren't shorting and unused I/O or something like that. What is the frequency of your clock? Are you operating your design at or below the reported speed from Quartus? shengyu_shen@hotmail.com (ssy) wrote in message news:<f4a5f64f.0206241730.5b32e814@posting.google.com>... > Hi everyone > > i am using an APEX20k400e, and my design use lots of ESB memory in it, > > the design function correctly when power up, but if I run for a very > long time(about 5 min), it will behavir in an error way, > > if I reset, the design still in error > > if I power down and then up immediatly, the design still in error, > > I think it is because the device is too hot, I touch the device with > my finger, it is very very very hot, > > so if any one have any sugession?Article: 44660
Petter Gustad wrote: > "Kevin Neilson" <kevin-neilson@removethistextattbi.com> writes: > > > I know Xilinx says that they don't yet support XP, but I've been using it > > and have had no problems (other than those I would normally have). On the > > contrary, I'm much happier, because instead of rebooting ~6 times per day on > > ME I'm rebooting once every six days. > > Even though SUN's are expensive they are very stable: > > scims:pegu $uptime > 3:28pm up 91 day(s), 39 min(s), 4 users, load average: 1.02, 1.01, 1.01 > > 91 days ago they had to remove the power in the entire office > building. I think that's more down to the O/S than the computer. Until recently my 1995 P-1 PC running BSDI Unix 4.2 had its up time limited only by the annual Christmas shutdown when I took it apart and vacuumed out all the accumulated fluff or local power failures. Sadly it seems like after long service the machine's finally going flakey on me when the temperature in the flat is high.Article: 44661
I am using Amplify with block regions to optimize a Virtex XCV800
implementation with TOP.
Compiling is OK : no error in Synplify log file.
(.... Region regrgn5 : TOPS successfull.....)
But when running Xilinx tools i get this messages in map.mrp
Anyone know what's wrong?
Charles
Section 1 - Errors
------------------
ERROR:Pack:679 - Unable to obey design constraints (LOC=CLB_R40C60.S1)
which
require the combination of the following symbols into a single slice
component:
XORCY symbol "rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_s_1"
(Output Signal
= Target.Design.DESIGN.CONNECT.y2_0<1>)
LUT symbol "rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_axb_0"
(Output Signal
= Target.Design.DESIGN.CONNECT.y2_0<0>)
LUT symbol "rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_axb_1"
(Output Signal
= rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_axb_1)
MUXCY symbol "rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_cry_1"
(Output
Signal = rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_cry_1/O)
The function generator
rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_axb_0 is
unable to be placed in the F position because the output signal
doesn't match
other symbols' use of the F signal. The signal
rgn9/Target.Design.DESIGN.CONNECT.G8/un4_y_axb_1 already uses F.
Please
correct the design constraints accordingly.
Article: 44662Hi, What are the consequences, if any, of applying an external voltage(4.3V max) to FPGA(Spartan II, XC2S50-5PQ208C) I/O pins for an extended period of time(seconds/minutes/hours), while the FPGA VCCO and VCCINT are not powered? When I apply 4.3V to a single FPGA I/O I get VCCO coming up to around 0.58V and VCCINT stays at 0V. On page 1 of module 3(DC and Switching Characteristics) of the data sheet, under Absolute Maximum ratings, the relevant specifications seem to be 1)Vin - Input voltage relative to GND, -0.5v to 5.5V for 5V tolerant I/O which I meet, and -0.5 to VCCO +0.5 for non-5v tolerant I/O which I do not meet. But I'm not sure if my I/O are classed as 5V tolerant or not when there is no power supplied to VCCO and VCCINT? 2)Note 3 says Vin should not exceed VCCINT by more than 3.6v over extended periods of time, which again I fail to meet. Do I have a problem? I think I understand why spec 1) exists. The high side output FET of an FPGA I/O has an inherent diode from the FPGA I/O pin to VCCO?(or perhaps not for LVTTL). If the FPGA I/O pin gets driven too high then this diode can conduct excessive current? Is this correct? Thanks in advance. AndrewArticle: 44663
Yury wrote: > Greetings all, > in VHDL we have the following way of telling the simulator/synthesis > tool where to find the description of components that have not been > explicitely declared within the source code: > ------------------------------------------- > library myLibrary; > use myLibrary.my_package.my_component; > ------------------------------------------- > > How do I do the same in Verilog? > > Thanks. For simulation with ModelSim I don't need this at compilation time since I use the -L flags on the simulator startup line to point to the pre-compiled libs needed to satisfy references. On those occasions where I want to vary the definitions used for different instantiation of the same component in the same source I resort to the `uselib directive (but I think this is ModelSim specific) ? For synthesis there are 2 options: One way is to add something like this at the end of your source file, after the last "endmodule": `include "<path_to_libfile>/libfile.v"; If the components are e.g. Xilinx primitives then your synth tool vendor should provide "libfile.v", it may depend on the device family. The other is simply to add the "libfile" to the list of sources you give to the synth tool. The Verilog `include mechanism is not as flexible since you cannot, without some difficulty, change the external definitions for the same component from entity to entity within the same source file, at least for synthesis ... but then how often is that an actual real life requirement ?Article: 44664
Falk, Thanks very much. I am happy with this business now - I realise that to pass data between "sample rate domains" I do not have to cross "clock domains". This makes life easier! Thanks for your time, Ken > -- clock enable generation > > process(clk) > begin > if clk='1' and clk'event then > if cnt=0 then > cnt <= div-1; > clk_en <= '1'; > else > cnt <= cnt -1; > clk_en <='0'; > end if; > end if; > end process; > > -- use clock enable to slow down clocking > > process(clk) > begin > if clk='1' anc clk'event then > if clk_en='1' then > > -- place your statements here > > end if; > end if; > end process; > > > > > I get the feeling I am a small snippet of code away from making the leap! > > You are. ;-) > > -- > MfG > Falk > > > >Article: 44665
Hello ! I would like to get hold of an IBIS simulator (simulator only) Any advice where I could get a good one ? Regards. Philippe.Article: 44666
Dear, I am doing Xilinx Virtex-E(XCV1000E) readback to capture register states. When I have compared "mydesign.rbb" to "readbackdata.bin" under "mydesign.msk" according to the Xilinx application note, it has failed. In other words, I have failed to verify the configuration data. It seems that the device works ok when I have probed some signals using Logic Analyzer. I have designed my C program according to the xilinx application note. Anybody has an idea why I have failed to verify configuration data or anybody has a customized C program that compares *.rbb and *.msk to the readback data? -- *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*- Young-Su Kwon, Ph. D Student VLSI Systems Lab, KAIST yskwon@vslab.kaist.ac.kr *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-Article: 44667
Hello, I am just writing a presentation in part of which I explain the benefits of pipelining in FPGAS - increased clock rates due to short critical paths means higher bandwidth in terms of spectrum and throughput etc. etc... It occurred to me however that, because registers are "free" in Xilinx slices, why would there ever be a case where we would want to not use the registers? I know that we might not need to since the required system rate may be low but that would not stop us from using them? Is it a power consumption issue? So the questions: Under what circumstances would it be advantageous to not use the registers? Under what circumstances is it unavoidable that we must not use the registers? Thanks for your time, KenArticle: 44668
Rick Filipkiewicz <rick@algor.co.uk> writes: > Petter Gustad wrote: > > > "Kevin Neilson" <kevin-neilson@removethistextattbi.com> writes: > > > > > I know Xilinx says that they don't yet support XP, but I've been using it > > > and have had no problems (other than those I would normally have). On the > > > contrary, I'm much happier, because instead of rebooting ~6 times per day on > > > ME I'm rebooting once every six days. > > > > Even though SUN's are expensive they are very stable: > > > > scims:pegu $uptime > > 3:28pm up 91 day(s), 39 min(s), 4 users, load average: 1.02, 1.01, 1.01 > > > > 91 days ago they had to remove the power in the entire office > > building. > > I think that's more down to the O/S than the computer. Until recently my 1995 P-1 > PC running BSDI Unix 4.2 had its up time limited only by the annual Christmas > shutdown when I took it apart and vacuumed out all the accumulated fluff or local > power failures. I agree. I have a 486 running Linux as a Web and mail server for three domains. Never had a crash. My point was that a SUN (and HP) are the only alternative platform for the entire Xilinx toolset. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 44669
Hi We had similar problems using Virtex-1000 devices (not Virtex E). I guess your refer to Xilinx appnote 138, which explains the comparison of the original and the readback bitstream. If I remember right, its quite a while since then, there were 2 problems: a) the bitstream that is read back from the board starts with a spurious superflous word. Although Xilinx confirmed that certain devices show this behavior, we did not find out, what this additional word actually means, so we just ignored it. b) there was/is an error in xapp 138. According to xapp 132 the rbb file starts with a header and a padding word, which must be skipped (32 bytes). What xapp 138 does _not_ tell you, is that this header is followed by a pad frame and a padding word (156 bytes in the case of a XVC1000) which must _also_ be skipped. For the maskfile we also assume also that tehre is an error in the documentation. xapp138 tells you to skip the header (28 bytes for XVC1000). Again, we found that xapp138 doesnt tell that this header is again followed by a padding word (4bytes) and a padframe+paddingword (once again 156 bytes for a XVC1000) which must also be skipped. After correcting these 2 problems verification of the readback bitstream worked for us. I will send you the C-code that worked for us, by private mail. Regards, Chris Young-Su Kwon wrote: > Dear, > > I am doing Xilinx Virtex-E(XCV1000E) readback to capture register states. > When I have compared "mydesign.rbb" to "readbackdata.bin" under > "mydesign.msk" according to the Xilinx application note, it has failed. > In other words, I have failed to verify the configuration data. > It seems that the device works ok when I have probed some signals > using Logic Analyzer. > I have designed my C program according to the xilinx application note. > Anybody has an idea why I have failed to verify configuration data > or anybody has a customized C program that compares *.rbb and *.msk > to the readback data? > > > -- > > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*- > Young-Su Kwon, > Ph. D Student > VLSI Systems Lab, KAIST > yskwon@vslab.kaist.ac.kr > *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*- -- Christian Plessl remove 'remove' from email-address when replyingArticle: 44670
Thank you, Ray. -- Best Regards, ----------------------------------------------------------------- Xu Qijun Engineer OKI Techno Centre (S) Pte Ltd Tel: 6770-7081 Fax: 6779-2382 Email: qijun677@oki.com "Ray Andraka" <ray@andraka.com> wrote in message news:3D193D79.3F9D5597@andraka.com... > Synchronization is not the issue. Jitter is. If the jitter is too much, the > DLL will fail to lock. Use an 80 MHz crystal and divide down rather than trying > to multiply up. > > XU QIJUN wrote: > > > Ray: > > > > What I did was a standard X4 muldiplier (P77&P82) provided by the Spartan-II > > handbook, > > it worked. Third X2 is in the third DLL place (P185) but I connected the > > output from X4 to P185 > > with a wire. It seemed the third DLL isn't work. I like this is because I > > need a single 100MHz clock > > to test an ASIC. My function generator maximum output 16MHz. > > Also I want to know where can I get a 80MHz clean clock out of 16MHz too? > > Synchronization > > among X2 X4 & X8 is insignificant. > > > > -- > > Best Regards, > > ----------------------------------------------------------------- > > Xu Qijun > > Engineer > > OKI Techno Centre (S) Pte Ltd > > Tel: 6770-7081 Fax: 6779-2382 > > Email: qijun677@oki.com > > "Ray Andraka" <ray@andraka.com> wrote in message > > news:3D17EB84.987B90B1@andraka.com... > > > Min frequency for the DLL input is 25 MHz for reliable operation. That > > falls > > > out from the length of the delay line used in there. Additionally, Xilinx > > does > > > not recommend cascading more than 2 DLLs because each adds jitter, and > > more than > > > 2 in a line can lead to problems with excessive jitter in the last one, > > although > > > if you keep your power supply clean, the input clock with low jitter and > > don't > > > switch to many single ended I/O on the same bank as the clock input, you > > can > > > probably get away with a cascade of 3. > > > > > > The placer can figure out how to put the DLLs if they are connected to do > > a > > > clockx4. Anything more than that you will have to either place in the > > > floorplanner, in the UCF file or in the source using LOC constraints > > because the > > > placer can't figure out how to put them. > > > > > > XU QIJUN wrote: > > > > > > > I could make it with 16MHz and times 4, but 8X is problematic, > > > > > > > > -- > > > > Best Regards, > > > > ----------------------------------------------------------------- > > > > Xu Qijun > > > > Engineer > > > > OKI Techno Centre (S) Pte Ltd > > > > Tel: 6770-7081 Fax: 6779-2382 > > > > Email: qijun677@oki.com > > > > "XU QIJUN" <qijun677@oki.com> wrote in message > > > > news:3d12919d$1@news.starhub.net.sg... > > > > > Hi, > > > > > > > > > > I am using a Spartan-II 100K to do some experiments on clock > > > > multiplication. > > > > > I successfully made a X2 and X4, then problem occurs when I coded one > > > > extra > > > > > DLL to make it 8. Following is the bug, > > > > > Whats your comments? > > > > > > > > > > ERROR:Place:1726 - Could not find an automatic placement for the > > following > > > > > components: > > > > > CLKIN of type GCLK IOB is placed at P77. > > > > > dll2x of type DLL is unplaced. > > > > > clk2xg of type GCLK BUFFER is unplaced. > > > > > dll4x of type DLL is unplaced. > > > > > clk4xg of type GCLK BUFFER is unplaced. > > > > > dll8x of type DLL is unplaced. > > > > > clk8xg of type GCLK BUFFER is unplaced. > > > > > lckpad of type GCLK BUFFER is unplaced. > > > > > ERROR:Place:1727 - Xilinx requires using locate constraints to > > preplace > > > > such > > > > > connected GCLK/GCLKIO/DLL components. > > > > > Total REAL time to Placer completion: 2 secs > > > > > Total CPU time to Placer completion: 1 secs > > > > > > > > > > ----------------------------------------------------------------- > > > > > > > > > > Following are the codes: > > > > > > > > > > module dll_standard (CLKIN, CLK2X, CLK4X, CLK8X, LOCKED); > > > > > input CLKIN; > > > > > output CLK2X, CLK4X, CLK8X, LOCKED; > > > > > > > > > > wire RESET; > > > > > wire CLKIN_w, RESET_w, CLK2X_dll, CLK4X_dll, LOCKED2X, LOCKED4X; > > > > > wire LOCKED2X_delay, RESET4X; > > > > > wire LOCKED4X_delay, RESET8X; > > > > > wire logic1; > > > > > assign RESET = 1'b0; > > > > > > > > > > assign logic1 = 1'b1; > > > > > > > > > > assign CLKIN_w = CLKIN; > > > > > assign RESET = RESET_w; > > > > > > > > > > CLKDLL dll2x (.CLKIN(CLKIN_w), .CLKFB(CLK2X), .RST(RESET_w), > > > > > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > > > > > .CLK2X(CLK2X_dll), .CLKDV(), .LOCKED(LOCKED2X)); > > > > > BUFG clk2xg (.I(CLK2X_dll), .O(CLK2X)); > > > > > SRL16 rstsrl (.D(LOCKED2X), .CLK(CLK2X), .Q(LOCKED2X_delay), > > > > > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1)); > > > > > assign RESET4X = !LOCKED2X_delay; > > > > > > > > > > CLKDLL dll4x (.CLKIN(CLK2X), .CLKFB(CLK4X), .RST(RESET4X), > > > > > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > > > > > .CLK2X(CLK4X_dll), .CLKDV(), .LOCKED(LOCKED4X)); > > > > > BUFG clk4xg (.I(CLK4X_dll), .O(CLK4X)); > > > > > SRL16 rstsr2 (.D(LOCKED4X), .CLK(CLK4X), .Q(LOCKED4X_delay), > > > > > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1)); > > > > > assign RESET8X = !LOCKED4X_delay; > > > > > // assign CLK4X_B = ~ CLK4X; > > > > > > > > > > CLKDLL dll8x (.CLKIN(CLK4X), .CLKFB(CLK8X), .RST(RESET8X), > > > > > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > > > > > .CLK2X(CLK8X_dll), .CLKDV(), .LOCKED(LOCKED_dll)); > > > > > BUFG clk8xg (.I(CLK8X_dll), .O(CLK8X)); > > > > > > > > > > BUFG lckpad (.I(LOCKED_dll), .O(LOCKED)); > > > > > > > > > > endmodule > > > > > > > > > > > > > > > > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759 > > > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 44671
Sometimes clock latency is an issue, for example if you have a DSP design with
a feedback loop, the feedback has to arrive at the input on the correct sample
time. Sometimes that has to be the next sample, which precludes pipelining
more than one sample interval.
Ken Mac wrote:
> Hello,
>
> I am just writing a presentation in part of which I explain the benefits of
> pipelining in FPGAS - increased clock rates due to short critical paths
> means higher bandwidth in terms of spectrum and throughput etc. etc...
>
> It occurred to me however that, because registers are "free" in Xilinx
> slices, why would there ever be a case where we would want to not use the
> registers? I know that we might not need to since the required system rate
> may be low but that would not stop us from using them? Is it a power
> consumption issue?
>
> So the questions:
>
> Under what circumstances would it be advantageous to not use the registers?
>
> Under what circumstances is it unavoidable that we must not use the
> registers?
>
> Thanks for your time,
>
> Ken
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44672?? my previous post went missing ? anyway yes, this will most probably be the way we will be doing, having the FF in IOB, and sample 4 time with diff phase clock. having 1 set of input register in the IOB should be better then having 8 set of 5bit input register not in the IOB. but then we need aleast 4 clocks ( phase 0, 45, 90 , 135), a 4-1 mux to select which clock to use, and we can't use the BUFGMUX cause there are 12 5-bit input channel from 12 different boards, need to calibrate each channel = 3 *12 BUFG MUX. one slice will be needed for the 4-1 MUX and the skews between the 4 clock has to be control, right? we could indirectly control the skew of the clock by setting a small maxdelay, and max skew on the individual clock net. short delay indirectly lead to small skew..... I hope. It will be great as Falk as point out if only we have min delay... have a 8 time clock and sample the input data into a shift reg is out too, because the data is coming at 100 Mhz ddr with a data window of 3 ns, therefore need 400 Mhz, but x2v4000 -4 DCM max out at 360 Mhz, aleast this is what the data sheet say. sure hope we have define the interfacing spec better ..... pyng Ray Andraka <ray@andraka.com> wrote in message news:<3D191666.F66F4736@andraka.com>... > Use the IOB registers. Then all the parallel bits have nearly identical > delays (tens of ps max differences) to the clock. > > spyng wrote: > > > hi, > > any one know is it possible to control the skew betwen different > > signal on Virtex2. for i.e, between i_data[0], i_data[1] > > ....i_data[7]. > > > > from what I understand NET "i_data[*]" MAXSKEW = 4 ns, will only > > constraint the skew of the individual signal. > > > > the problem I have is that my external data(5 bit) and clock is not > > align properly (don't ask me why, I have try that), so we are trying > > to sample the input data with 8 different phase of the internal clock > > and then determind which phase is the best to use. > > > > so there will be 8 set of input data sample register and they can not > > be in the IOB. But we will have to make sure that all the 5 bit input > > data have the same delay to all the 8 set of data sample reg. > > > > Xilinx actually have a app note on this (xapp 255), but I am not > > convince that they are able to control the skew between different > > signal. correct me if I am wrong. > > > > any help? > > thanks > > pyng > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 44673
I use Innoveda's Hyperlynx (now owned by Mentor) We also use Cadence SpectraQuest, but I find it more difficult to use, yet it is more powerful. Austin Philippe Robert wrote: > Hello ! > > I would like to get hold of an IBIS simulator (simulator only) > Any advice where I could get a good one ? > > Regards. > Philippe.Article: 44674
"spyng" <ospyng@yahoo.com> schrieb im Newsbeitrag news:b34a8c79.0206260526.18c87c8@posting.google.com... > we could indirectly control the skew of the clock by setting a small > maxdelay, and max skew on the individual clock net. short delay > indirectly lead to small skew..... I hope. > > It will be great as Falk as point out if only we have min delay... > > have a 8 time clock and sample the input data into a shift reg is out > too, because the data is coming at 100 Mhz ddr with a data window of 3 > ns, therefore need 400 Mhz, but x2v4000 -4 DCM max out at 360 Mhz, > aleast this is what the data sheet say. Man, if you have a Virtex2 (I didnt realize this at first) you can use a DCM to make a fixed phase shift on your clock. Adjust it to you needs and you will be fine. No need for oversampling etc. > sure hope we have define the interfacing spec better ..... @100 Mhz, you better know what you are doing. -- MfG Falk
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