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Riccardo Rubini wrote: > > Hello all, > > I am a newbie in electronics...and I have a quite big problem. I am in > urgent need of cloning a TIBPAL20L8 device I have on a custom board, > whose author unfortunately passed away. I would like to have a spare > before the irreparable occurs and I have to kiss the board goodbye for > good. These program using .JED files, - have a search in your PCB/SCH archives for this extension, then scan again for the source file. One of the better Chip programmers will read this device _IF_ it has not been secured. A few seconds loan is all that's needed :) If it has been secured, then you can work away with a text editor, and your schematics, and create a test vector file, and test that against the working device. ( using a vector Test capable Programmer ) > How should I proceed ? Is there any free PAL/GAL programmer available > on the net that could help me reading the contents of the 20L8 and > then burn it on another PAL or a compatible GAL ( 20V8 comes to my > mind ) ? > > If I can't read the contents of the PAL, I have the schematics of the > PCB where this device is placed, but I don't know if this is > sufficient to understand and trace the equations of the PAL device. Not sufficent, but much better than nothing :) It will give you all the pin names, and connections, and from that, plus the uC/uP source code you can start to map the expected logic. -jgArticle: 44576
Austin Lesea escribió: > > Ted, > > What you are asking for is very old technology (anything > 5V is larger than > 0.35u). > > I doubt it exists anymore. > > Austin > Hi all, I agree with Austin. It seems that 5V is more expensive, now and in near future, than 3.3V ... and lower voltages are cheaper and probably unavoidable. I think that FPGAs are similar to SHUTTLEs: 100 cells, 1000 cells, 10K cells, 100Kcells, (earth orbit ;-), 1Mcells (the Moon is far back), 10Mcells (out of solar system!), ... The same happens with packages: PLCC44, PLCC84, TQFP144, CB228, ..., CG1156, ... And the same with frequencies, and so on. I think that telephone companies would be happy, because a whole city controller fits in one chip, but what happens with small domestic/industrial applications? Lots of small domestic/industrial applications need only 1K~10K cells for one or two processors and peripheral devices, only 20~44 pins and only 1~10 MHz ... but less than 1~3$ per chip. These requirements are found on specific microcontrollers that would be replaced by generic CPLD/FPGAs, but ... Good luck on your search Ted. Probably a 3.3 volt (5V tolerant) CPLD would fit your I/O needs. Maybe the Xilinx XCR3256XL in TQFP144 would be a good choice. Best regards, Santiago (sanpab@eis.uva.es). > ted_jmt@zapta.com wrote: > > > >> > > >> 2. Must work on 5V (or higher) > > > > > >Interesting request - How much higher - and for what loads ? > > > > 10V will be optimal. Current requirements are very very low (250uA is > > more than enough) > > > > > > > >150 i/o is a lot in one package - what is this driving ? > > >( are all the loads in one place ? ) > > > > > >Is the IO by Serial or parallel BUS, 8 or 16 bits wide ? > > > > > >Better may be 32 io in 44 pin packages, and use 5 packages spread on the > > >board(s). > > >CPLDs come in 32/64/128/.. macrocells, the better ones can pack a shift > > >and latch > > >into one macrocell. Prices are appx $1/32MC > > > > Is the price per IO pin goes up with larger CPLD's (e.g. >100 pins) or > > is it cheaper to have one big CPLD ? We can go both ways depending on > > which option is cheaper. > > > > >> > > >> 5. Can be easily converted to a mask based equivalent chip (a full > > >> ASIC is not possible at this stage, maybe for second generation). > > >> > > >> 6. Cost of the masked version is very critical (and having a > > >> reasonable conversion/tooling cost is also very nice to have). > > > > > >So too are the volumes :) - what is the budget per I/O pin ? > > > > 1c per I/O in large quantities will be OK.Article: 44577
Hallo All! I'm looking for recipe how to truncating or rounding stages in CIC filter. Every documents says that clue is in E. B. Hogenauer article: "An ecomical class of digital filters for decimationand interpolation". But I can't find this document at all. Can You help me? Best regards furiaArticle: 44578
does anybody know of lecture books on place&route and mapping techniques thanx ThomasArticle: 44579
Jim Granville wrote: > > > If it has been secured, then you can work away with a text editor, and > your schematics, and create a test vector file, and test that against > the working device. ( using a vector Test capable Programmer ) > Even that might not be straightforward if the PAL design used any async feedback sample and hold tricks: output = !clr & (set # output); Before I'd start doing this I'd scour the company file systems and backup tapes from one end to the other looking for anything with a .abl, .pld, .tt<1 | 2 | 3>, .jed, .<whatever the CUPL extension was>. I had to do something similar once but without the excuse that the designer had passed away, since it was me who had managed to lose the source.Article: 44580
Hi FPGA-NG, for learning purpose, I would like to program some old CPLD's from Lattice former AMD/Vantis. I had download the ispDesigner from the Lattice ftp server but found, that no design could be created with MACH211, MACH4-64/32 or MACH4-64/64 CPLD's as they are obsolete. Using the old Vantis SW Synario 2.3 or 3.1 I'm running in the problem that either Mach2 nor MACH4 devices could be programed due to different libraries. Scanning the directories of the SW installed, I found all kinds of CPLD's definition files, also for MACH211 and MACH4-64/32, but I'm not able to select them in the project navigator either in the new ispDesigner sw nor in the Synario SW. It's seems to be a configuration problem of some installation scripts or some config files in the directory structure. Could you please give me some hints how to enable the desired CPLD's types in the ispDesigner or in the Synario software. Many thanks in advance. Markus ============================================= Markus Wolfgart DLR ============================================= PS.: remove the xx_ from email adr. to replay =============================================Article: 44581
John_H <johnhandwork@mail.com> wrote in message news:<3D16825F.BA4705EB@mail.com>... > I thought gbufs only - repeat ONLY - went to clocks or immediately to > secondary routing. Has this changed since Virtex such that a global > signal is available for more than just clocks? A clock enable or > synchronous reset would be too nice. > > I've done my share of poking down into the VirtexE and Virtex-II with > the FPGA editor program and didn't see any new global resource > connectivity (other than clocks) but I wasn't looking hard at the time. I see the same thing John does. I have a widely used clock enable that I would like to be on a global net, but looking in FPGA editor on my Virtex-II design appears to reveal the clock enable being tapped off right after the BUFG driver and using local routing to travel across the chip and back. This actually ends up with worse timing than not having the BUFG in there at all because you have to incur the delay of the BUFG. Knowing Xilinx, there is probably a magic environment varible that enables GCLK routing to non-clk inputs. Marc > newman wrote: > > > > In a previous post, I mentioned something about a gbuf driving a > > synchronous reset in a VirtexE device. It was actually an > > asynchronous reset driven by a flip-flop in the same clock domain that > > got routed/synthesized by the tools via a gbuf. I was in a hurry, and > > still had 2 spare gbufs, so I did not investigate this phenomenon as > > much as I would have liked to, but it worked like a champ. > > > > NewmanArticle: 44582
Riccardo wonders? > help me reading the contents of the 20L8 and >then burn it on another PAL or a compatible GAL ( 20V8 comes to my >mind? the other posts all have useful suggestions - the best of which may be find the source, or get the JED file out of the device. You can visit the Lattice website - search for PAL2GAL.exe- this executable -runs in DOS or command prompt window - will convert existing PAL jed files to the best fit GAL equivalent. A 20L8 is combinatorial logic only, no registers on that device. Fits into 20V8 and is pin compatible. Another file to scour the net for would be JED2AHDL - this will convert JED files from PALs/GALs to ABEL equation format. Once in ABEL, use existing tools on the website - ispLEVER - free!- to compile and target the apporpriate device. Good Luck and welcome to "our world" Michael Thomas LSC SFAE New York/New Jersey 631-874-4968 fax 631-874-4977 michael.thomas@latticesemi.com for the latest info on Lattice products - http://www.latticesemi.comArticle: 44583
If I remember right, the following book should provide some information on that: Architecture and CAD for deep-submicron FPGAs / Vaughn Betz, Jonathan Rose, Alexander Marquardt. Boston [etc.] : Kluwer Academic Publishers ; cop. 1999.. XI, 247 S. ; 25 cm : Ill.. (The Kluwer international series in engineering and computer science ; 497) Regards, Chris Thomas Buerner wrote: > does anybody know of lecture books on place&route and mapping techniques > thanx > > ThomasArticle: 44584
Hello folks,
The VHDL at the end describes a clock divider that will divide the input CLK
by any integer DIV and produce a clock pulse on CLKDIV that has the same
duration of CLKs period. The clock pulse on CLKDIV happens every DIV clock
edges of CLK (obviously :-) )
After synthesis in Synplify (targetting Xilinx Spartan-II) it looks pretty
good - very small and should run well over 100MHz apparently.
So, the questions:
It is my intention to pass data between two clock domains: CLK and CLKDIV -
can I use the VHDL below to synthesise CLKDIV and use this as the source
clock for the CLKDIV domain?
Will this avoid metastability issues?
Will I have to specify CLKDIV as having special status as a clock so that
the tools will put it on the global clock lines (hope that is the right
terminology)?
Any other issues my inexperience has allowed me to miss?
Am I on the right lines here in general or have I got the wrong end of the
stick?
Thanks in advance for your time,
Ken
PS - I know I could use an asynchronous FIFO to cross the domain but I want
the smallest solution possible in terms of slices and want to avoid state
machines...
// START VHDL code
library IEEE;
use IEEE.std_logic_1164.all;
entity eMetastabilityTesting is
port (
CLK : in STD_LOGIC;
CLKDIV : out std_logic
);
end eMetastabilityTesting;
architecture aMetastabilityTesting of eMetastabilityTesting is
constant DIV : integer := 5;
signal cnt : integer range 0 to DIV := 0;
begin
process(clk)
begin
if rising_edge(clk) then
if cnt <= (DIV-1) then
cnt <= cnt + 1;
else
cnt <= 1;
end if;
end if;
end process;
process(cnt)
variable tmp : std_logic;
begin
if cnt <= (DIV-1) then
tmp := '0';
else
tmp := '1';
end if;
clkdiv <= tmp;
end process;
end architecture;
// END VHDL code
Article: 44585> But I can't find the driver. > > I try to use the setup application under the directory "drivers" in the path > where I installed MaxPlus+II > but it looked useless. > > any other ideas? or Maxplus just doesn't support WinXP? AFAIR you should manually install ByteBlaster driver for NT selecting it as 'sound card' or joystick. Description is available on www.altera.com jerryArticle: 44586
In article <3D16A20C.2809B2A3@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >I also do not understand exactly how the CPU heats up as you do >"computation". Have they changed the OS so that the CPU stops when you >don't give it something to do? Does the clock slow down when running >the IDLE task? I suppose that memory accesses are reduced since you >should get more cache hits, but I don't see how the CPU heat will change >significantly. The P4 uses alot of gated clocks, so large hunks of the datapath aren't clocked unless they are in use. Power consumption is very computation dependant on the P4. >But even if 1% of the machines are running workhorse code, it would be >immediately recognized if they were slower than other machines with much >lower clock ratings. In my last position we had a bank of servers to >crunch FPGA work and we would have known there was a problem. We had >one P4 which was used by the group designing in the largest FPGAs we >were using. We did not see a problem and this 1 GHz machine ran faster >than the 750 MHz P3s. I can't belive Intel is making a chip or that >DELL, etc are making machines that slow down running "normal" FPGA >apps. The INITIAL P4s ran very hot, and some people did notice the slowdown happening on cases with poor cooling, notably on Quake and similar sustained processor intensive tasks. It actually doesn't slow the clock, it just switches on and off at a 2 us period, so a roughly 50% duty cycle, using the existing STOPCLOCK ability. Do a google search for "P4 thermal diode" and a lot of the flameage still remains. The newer ones (post process shrink) run significantly cooler, and the cooling has also somewhat improved, and the understanding of the importance of cooling it. http://developer.intel.com/technology/itj/q12001/pdf/art_4.pdf Is a paper on it. An interesting observation: they wanted to reduce power 20%, but reduce the thermal design point by 40%. As such, they wanted the cooling to be omre in line with expected, and high expected, not peak cooling. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 44587
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3D16A304.F767D0F@yahoo.com... > Duane Clark wrote: > > > > Marcel wrote: > > > Hi, > > > > > > I`m using Xilinx webpack and am quite new to VHDL, at the marked line I have > > > to place three times end if, > > > otherwise a syntag error is generated. > > > > > > Why do I have to place 3 times end if here instead 1 end if ? > > > > > > Any ideas ? > > > > > > > > > > > > process( SEL, D ) > > > begin > > > if ( SEL = "0000" ) then > > > TCK <= D(0); > > > else if ( SEL = "0001" ) then > > > > "elsif" instead of "else if". > > > Marcel, > > Now you are supposed to say, "never mind"... :) > I`ll just say thanks....Tried 'elseif' but this didn`t work, but without the 'e' works fine :-)Article: 44588
Hello there, I am designing a PCB and I need to connect an FPGA (Virtex-II) to memory devices. They are all 16bits x 64Meg devices. The aim is to make a 16-bit bank as big as possible. I need to work out the maximum number of devices the FPGA can drive. The input capacitance of the memory is 4pF. Could someone help me to work out the number of memory devices that I can connect to the FPGA ? Thanks a lot. Philippe.Article: 44589
Problem:
In my VHDL-code I have the follwing construct:
if (clk='0') then
....
end if;
Normally this would generate a latch.
However my target technology is Altera APEX20KE which doesn't contain
any latches.
My synthesizing tool (Mentor Leonardo / Exemplar LeonardoSpectrum)
uses a combinational loop, but in such a way that it causes
oscillations.
Is there a way to synthesize the above construct without generating
oscillations?
Thank you for your help.
Article: 44590It's vary hard to test _everything_ in any kind of ASIC. Mostly you test for stuck-at-faults, where node is stuck at a one or a zero, and local shorts. There are a group of faults called bridging faults that have a piece of metal bridging non-local areas. These are hard to find as the number of test vectors goes up (2^n) if you including testing every piece of metal to every other piece. You should turn in the device and test vectors to someone (FAE or rep or hotline) and get them to replace your part. I did this once and was told Xilinx incorporated the bitfile into their test program. So it does happen. I'm sure with something as complex as the V2 they will never be able to test for all the kinds of faults there are. Steve "Endric Schubert" <endric_@_bridges2silicon.com> wrote in message news:bxPQ8.6788$LG4.362189992@newssvr21.news.prodigy.com... > A hardware guy in my company recently mentioned that he has 2 "bad" Xilinx > Virtex2 devices now. In one device there seems to be a stuck-at-1 memory bit > (he found that out when using 100% block RAM) the other seems to have a > internal connection problem: One and the same bit file works fine on one > device but not on the "bad" device. > > I just wonder, has anybody had similar experiences and how do you find those > problems in the lab? > > Endric > > -- > Bridges2Silicon, Inc. > Endric Schubert, PhD > 471 E. Evelyn Ave. > Sunnyvale, CA 94086 > www.bridges2silicon.com > Direct: (408) 245 8513 > Fax: (408) 245 2960 > Mobile: (408) 221 6139 > > > >Article: 44591
hi, any one know is it possible to control the skew betwen different signal on Virtex2. for i.e, between i_data[0], i_data[1] ....i_data[7]. from what I understand NET "i_data[*]" MAXSKEW = 4 ns, will only constraint the skew of the individual signal. the problem I have is that my external data(5 bit) and clock is not align properly (don't ask me why, I have try that), so we are trying to sample the input data with 8 different phase of the internal clock and then determind which phase is the best to use. so there will be 8 set of input data sample register and they can not be in the IOB. But we will have to make sure that all the 5 bit input data have the same delay to all the 8 set of data sample reg. Xilinx actually have a app note on this (xapp 255), but I am not convince that they are able to control the skew between different signal. correct me if I am wrong. any help? thanks pyngArticle: 44592
how can I constraint the ISE to use the ALT_VRP and ALT_VRN of bank 4 instead of the VRP_4/VRN_4 as the pins to be connected to the termination resistors ? I would like to use VRN_4 and VRP_4 as functional IOs.Article: 44593
"Jerzy Gbur" <furia@wp.pl> wrote in message news:3d16f50d@news.vogel.pl... > I'm looking for recipe how to truncating or rounding stages in CIC filter. These are not exactly what you requested but maybe they will help: http://www.dspguru.com/info/tutor/cic.htm http://www.xilinx.com/ipcenter/catalog/logicore/docs/cic.pdf Paul.Butler@ni.comArticle: 44594
I've never found it on line. It can, however be found in a decent university
library. It doesn't distill into a simple formula, but you can get most of the
way there by starting at the output and adding one LSB on each prior stage until
you get to the integrator. I don't recall off hand the method for truncating
the integrator, IIRC it depends on the number of samples in the comb delay.
Paul Butler wrote:
> "Jerzy Gbur" <furia@wp.pl> wrote in message news:3d16f50d@news.vogel.pl...
> > I'm looking for recipe how to truncating or rounding stages in CIC filter.
>
> These are not exactly what you requested but maybe they will help:
>
> http://www.dspguru.com/info/tutor/cic.htm
>
> http://www.xilinx.com/ipcenter/catalog/logicore/docs/cic.pdf
>
> Paul.Butler@ni.com
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44595Do a search in the Xilinx Answers database for ALT_VRP and you'll see that the ALT_VRs are supported for legacy designs which specified the VRs on those ALT_ pins. If you need to use the ALT_VRs, it applies to all banks with ALTs, not selectable on a bank by bank basis. An environment variable is needed to make the switch. Since the ALTs are for legacy support, I had our schematic part made without the ALTs. Eyal Shachrai wrote: > how can I constraint the ISE to use the ALT_VRP and > ALT_VRN of bank 4 instead of the VRP_4/VRN_4 as the pins to > be connected to the termination resistors ? > I would like to use VRN_4 and VRP_4 as functional IOs.Article: 44596
Nope, non that I am aware of. The clock nets are designed for low skew, but not
necessarily low delay. I suspect even if you coerced the tools into letting you abuse
the global clock distribution that you would find the delay unacceptable. The clock
nets are wired just to the flip-flop clock inputs with an ability to get off the clock
net onto the general routing.
The 'low skew' nets are design for CE distribution, but they are way too slow if you are
clocking the part more than a couple tens of MHz. You need to distribute the CE in a
pipelined tree, or create local ce's as needed. You can also just CE critical registers
and let the data go through the others as it pleases. For example, if you put a CE on
the first register in a pipeline, the data becomes static until the next ce'd clock, so
the subsequent registers could be allowed to run without CE. The data may not be
deterministic after the first clocks, but it should be OK on the next ce'd clock +
latency at the other end. Any data dependent or position dependent stuff in the
pipeline will have to be gated by a delayed version of CE as well.
Marc Randolph wrote:
> John_H <johnhandwork@mail.com> wrote in message news:<3D16825F.BA4705EB@mail.com>...
> > I thought gbufs only - repeat ONLY - went to clocks or immediately to
> > secondary routing. Has this changed since Virtex such that a global
> > signal is available for more than just clocks? A clock enable or
> > synchronous reset would be too nice.
> >
> > I've done my share of poking down into the VirtexE and Virtex-II with
> > the FPGA editor program and didn't see any new global resource
> > connectivity (other than clocks) but I wasn't looking hard at the time.
>
> I see the same thing John does. I have a widely used clock enable
> that I would like to be on a global net, but looking in FPGA editor on
> my Virtex-II design appears to reveal the clock enable being tapped
> off right after the BUFG driver and using local routing to travel
> across the chip and back. This actually ends up with worse timing
> than not having the BUFG in there at all because you have to incur the
> delay of the BUFG.
>
> Knowing Xilinx, there is probably a magic environment varible that
> enables GCLK routing to non-clk inputs.
>
> Marc
>
>
> > newman wrote:
> > >
> > > In a previous post, I mentioned something about a gbuf driving a
> > > synchronous reset in a VirtexE device. It was actually an
> > > asynchronous reset driven by a flip-flop in the same clock domain that
> > > got routed/synthesized by the tools via a gbuf. I was in a hurry, and
> > > still had 2 spare gbufs, so I did not investigate this phenomenon as
> > > much as I would have liked to, but it worked like a champ.
> > >
> > > Newman
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44597John, I think you are correct about gbuf global routing on non-clock lines. I did a small test case, and with a virtexe, the net name connected to the gbuf was H_GENOUT. With a VirtexII, the node was V_GLOBAL, but ended up going to a switchbox and was routed from there. Thanks for setting me straight. Newman John_H <johnhandwork@mail.com> wrote in message news:<3D16825F.BA4705EB@mail.com>... > I thought gbufs only - repeat ONLY - went to clocks or immediately to > secondary routing. Has this changed since Virtex such that a global > signal is available for more than just clocks? A clock enable or > synchronous reset would be too nice. > > I've done my share of poking down into the VirtexE and Virtex-II with > the FPGA editor program and didn't see any new global resource > connectivity (other than clocks) but I wasn't looking hard at the time. > > > newman wrote: > > > > In a previous post, I mentioned something about a gbuf driving a > > synchronous reset in a VirtexE device. It was actually an > > asynchronous reset driven by a flip-flop in the same clock domain that > > got routed/synthesized by the tools via a gbuf. I was in a hurry, and > > still had 2 spare gbufs, so I did not investigate this phenomenon as > > much as I would have liked to, but it worked like a champ. > > > > NewmanArticle: 44598
Our company was recently involved in an asset recovery program with a local manufacturing facility. As part of the program we received a qty. of xylinx and other product that is new, in manufacturer's packaging and we are able to offer at a signicant savings. We also received approx. 1000 boards that were already built and never deployed - each with 2+ xylinx chips as well as other material we can have these boards professionally demanufactured for your use if you are interested. Please let me know if we can be of service. Serious inquiries can be placed with bob@perecycle.com - I will be happy to supply a list. Thank you, BobArticle: 44599
--------------19B0F2E3C2A9609F0AC608C0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Steve, Sometimes a fault escapes our present coverage. It is true that if it is a real test escape, we are always interested in adding vectors to cover it. Understand that we prefer to work with customers when they find what they think is such a fault before the part is removed fromt he board. >99% of such reports turn out to be customer design issues, with no fault in the part. Once the part is removed from the board, and we test it, with the customer supplied pattern, we find an incredibly tiny fraction with a true fault. Open a case with the hotline. We will get the CAE with the local FAE to work the issue. It will either fix the problem with the design or the board, or it will (occasionally) catch a part that escaped with a real fault. One more advantage to this method, is that if there is a known issue with a part, and a workaround, you will learn of it much faster. Austin Steve Casselman wrote: > It's vary hard to test _everything_ in any kind of ASIC. Mostly you test for > stuck-at-faults, where node is stuck at a one or a zero, and local shorts. > There are a group of faults called bridging faults that have a piece of > metal bridging non-local areas. These are hard to find as the number of test > vectors goes up (2^n) if you including testing every piece of metal to every > other piece. > > You should turn in the device and test vectors to someone (FAE or rep or > hotline) and get them to replace your part. I did this once and was told > Xilinx incorporated the bitfile into their test program. So it does happen. > I'm sure with something as complex as the V2 they will never be able to test > for all the kinds of faults there are. > > Steve > > "Endric Schubert" <endric_@_bridges2silicon.com> wrote in message > news:bxPQ8.6788$LG4.362189992@newssvr21.news.prodigy.com... > > A hardware guy in my company recently mentioned that he has 2 "bad" Xilinx > > Virtex2 devices now. In one device there seems to be a stuck-at-1 memory > bit > > (he found that out when using 100% block RAM) the other seems to have a > > internal connection problem: One and the same bit file works fine on one > > device but not on the "bad" device. > > > > I just wonder, has anybody had similar experiences and how do you find > those > > problems in the lab? > > > > Endric > > > > -- > > Bridges2Silicon, Inc. > > Endric Schubert, PhD > > 471 E. Evelyn Ave. > > Sunnyvale, CA 94086 > > www.bridges2silicon.com > > Direct: (408) 245 8513 > > Fax: (408) 245 2960 > > Mobile: (408) 221 6139 > > > > > > > >
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