Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 43400

Article: 43400
Subject: Re: How to generate fractional-N clock ?
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Tue, 21 May 2002 05:04:46 GMT
Links: << >>  << T >>  << A >>
On Mon, 20 May 2002 16:38:27 GMT, John_H <johnhandwork@mail.com>
wrote:

>I just saw on another newsgroup a mention that I'll quote here
>(comp.lang.verilog, thread "7497 implementation"):
>
>Allan Herriman wrote:
>
>> I guess it's time to plug my totally free Fractional-N divider program
>> that generates VHDL and Verilog.
>> http://fractional_divider.tripod.com
>>
>> Regards,
>> Allan.
>
>I haven't looked at the site but you might find something of interest there.

Hi,

That program generates *fixed frequency* fractional-N dividers, and as
such probably isn't suited to the OP's needs.

Regards,
Allan.

Article: 43401
Subject: Addressable shift register
From: John Williams <j2.williams@qut.edu.au>
Date: Tue, 21 May 2002 15:08:28 +1000
Links: << >>  << T >>  << A >>
Hi folks,

I've created an addressable shift register, which has data_in, d_clk,
and tap_sel inputs, and a data_out output.  The idea is that data are
clocked in on d_clk, and tap_sel chooses which data value (tap) is
expressed on the output.  I'm using 8 of these things to create a
byte-wide structure.

I'm creating such registers up to 500 entries long, so it obviously
takes a fair while to synthesise (targetting Virtex 300K).  One of the
messages I get during synthesis is:

WARNING:Xst:738 - 2072 flip-flops were inferred for signal
<shift_buffer>. You may be trying to describe a RAM in a way that
 is incompatible with block and distributed RAM resources available on
Xilinx devices, or with a specific template that is n
ot supported. Please review the Xilinx resources documentation and the
XST user manual for coding guidelines. Taking advanta
ge of RAM resources will lead to improved device usage and reduced
synthesis time.

I've done a web search for addressable shift register but not founding
anything specific.  My design appears to work (ie behavioural sim
matches post P&R sim, and I'm happy about that), but if there's a
recommended "best practice" then I'd like to know about it.

From this warning, can anyone suggest how I might better implement such
a beast?  My code follows for those interested.  It's pretty short and
self-explanatory.  

Thinking about it, I guess in a way I'm creating an addressable FIFO,
except that instead of updating the write pointer (and morhping the read
address appropriately), I'm shifting all of the data every clock tick. 
Would I maybe be better rewriting this as a FIFO?

Cheers,

John


-- an addressable shift register
-- data are clocked in on d_clk, and shifted right one place each time
-- tap_sel chooses which register value is expressed on data_out
-- this is a fully synchronous design, with a one clock delay between 
-- d_clk and the data
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.conv_types.all;

entity shifter is
    Port ( reset: in std_logic;
           data_in : in std_logic_vector(7 downto 0);
           d_clk : in std_logic;
           tap_sel : in std_logic_vector(pix_sel_width-1 downto 0);
           data_out : out std_logic_vector(7 downto 0));
end shifter;

architecture behavioral of shifter is

  type my_buffer_type is array (7 downto 0) of
std_logic_vector(line_len-1 downto 0);
  signal shift_buffer: my_buffer_type;

begin

  process(d_clk,reset,shift_buffer,tap_sel)
  begin
    if(d_clk'event and d_clk='1') then
      for i in 7 downto 0 loop
        shift_buffer(i) <= shift_buffer(i)(line_len-2 downto 0) &
data_in(i);
      end loop;
    end if;
  end process;

  tap_output:
  for i in 7 downto 0 generate
    data_out(i) <= shift_buffer(i)(conv_integer(tap_sel));
  end generate;

end behavioral;

Article: 43402
Subject: Re: How to generate fractional-N clock ?
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Tue, 21 May 2002 05:21:48 GMT
Links: << >>  << T >>  << A >>
On Mon, 20 May 2002 16:42:46 +0200, "Marcel"
<marcelgl-hates-spam@xs4all.nl> wrote:

>Hi,
>
>I need to generate a tunable clock  in the range from 18Mhz - 30Mhz with
>100Hz resolution.
>I was considering to use an external VCO and implement a PLL in the FPGA.
>But I was wondering is this
>also can be done in another way.
>
>The main problem is that the clock is used for audio D/A, so it must be a
>low jitter clock.
>
>Any suggestions ?

1.  Audio is usually only sampled at certain rates, e.g. 8.0000kHz
(and multiples), 11.025kHz (and multiples) and 48.000kHz (and
multiples.)
... why do you need to use other frequencies?  And why 100Hz
resolution on your high speed clock?

2.  If you need the variable sampling rate for an audio effect (pitch
shift, delay, phaser, etc.), it might be more effective to do the
entire thing digitally, using fixed frequency ADC and DAC.  Ask in
news:comp.dsp

3.  Assuming you do need to use non-standard frequecies, you can do
resampling digitally (using a DSP sample rate converter) to get from a
standard rate to whatever rate you want.  This might be simpler, given
that you can get single chip resamplers e.g. AD1890 - AD1896.
http://products.analog.com/products/info.asp?product=AD1890
(Not sure if you are doing ADC or DAC (you mention both) but the
resampler chips should work in both cases.)
You could also implement a resampler using a polyphase filter or an
interpolator and decimator in an fpga.

4.  The 5ns jitter you mentioned is *way too high* for high end audio.
You will need to do some research to work out what the requirement
actually is, though.

5.  Lowest jitter will come from a crystal oscillator.

I hope this helps.

Allan.

Article: 43403
Subject: Re: Addressable shift register
From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver)
Date: Tue, 21 May 2002 05:34:34 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3CE9D64C.E2E16C40@qut.edu.au>,
John Williams  <j2.williams@qut.edu.au> wrote:
>I've created an addressable shift register, which has data_in, d_clk,
>I'm creating such registers up to 500 entries long, so it obviously
>takes a fair while to synthesise (targetting Virtex 300K).  One of the
>messages I get during synthesis is:


One word:  SRL16
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 43404
Subject: Re: Addressable shift register
From: John Williams <j2.williams@qut.edu.au>
Date: Tue, 21 May 2002 15:43:30 +1000
Links: << >>  << T >>  << A >>


Nicholas Weaver wrote:
> 
> In article <3CE9D64C.E2E16C40@qut.edu.au>,
> John Williams  <j2.williams@qut.edu.au> wrote:
> >I've created an addressable shift register, which has data_in, d_clk,
> >I'm creating such registers up to 500 entries long, so it obviously
> >takes a fair while to synthesise (targetting Virtex 300K).  One of the
> >messages I get during synthesis is:
> 
> One word:  SRL16

Thanks Nicholas,

I've checked out the SRL16 - to create a register longer than 16 bits,
I' can cascade them  - just set them all to be 16 bits long and tie the
Qs to the Ds.  

The problem is my random addressing scheme - I'll have to have two
modes, one where it shifts (where the Q's are tied to the Ds and the A
lines are fixed), and a second mode to actually read values out of it
(where the Q's are attached to the outputs and the A lines are
controlled by my input address (tap_sel in my design).  

This could be solved with multiplexers, but non-trivially.  Also it
complicates the surrounding circuitry.

Any other suggestions?

Cheers,

John

Article: 43405
Subject: Re: Addressable shift register
From: Peter Alfke <palfke@earthlink.net>
Date: Tue, 21 May 2002 06:15:17 GMT
Links: << >>  << T >>  << A >>


John Williams wrote:

> Any other suggestions?
>
>

I would use a dual-ported RAM. You can "shift" bits in serially into one
port ( needs an address counter) and read the result out in paralell fashion
on the other port. Needs a little finess with the two counters, but might do
your job.What's the speed?

Peter Alfke



Article: 43406
Subject: Re: Addressable shift register
From: John Williams <j2.williams@qut.edu.au>
Date: Tue, 21 May 2002 16:20:17 +1000
Links: << >>  << T >>  << A >>


Peter Alfke wrote:
> 
> John Williams wrote:
> 
> > Any other suggestions?
> >
> >
> 
> I would use a dual-ported RAM. You can "shift" bits in serially into one
> port ( needs an address counter) and read the result out in paralell fashion
> on the other port. Needs a little finess with the two counters, but might do
> your job.  

Yes, I think you're probably right.

> What's the speed?

Not crucial, the faster the better basically.

I'm experimenting with the SRL16 idea at the moment, will try the DP RAM
next.  

Cheers,

John

Article: 43407
Subject: Re: fpga cpu
From: "Victor Schutte" <victors@mweb.co.za>
Date: Tue, 21 May 2002 09:12:56 +0200
Links: << >>  << T >>  << A >>
I can only say that you are not alone.  I am now thinking of just porting
something like SmallC, generate generic assembly language and then writing a
translator for the specific CPU. Keep in mind that the size and capabilities
of the compiler will be determined by the size and capabilitities of your
CPU. If you design a simple 8 bit CPU with limited addressing capabilities
it would be senseless to write/port a large C/C++ compiler like GNU C.  For
something like NIOS you would need a small team of people (or you can do it
in a couple of months as a hobby pet project).

Sometimes C is not the best solution. If you look at the small PIC
controllers you will find many C compilers written for it but at closer
inspection you will find that the architechture does not allow for fancy
pointers and ROM addressing, making your code bloated. In some of these
cases if would be best to write a macro based assembler where you have total
control over what goes on inside.

BTW, have you looked at other compilers like SDCC (8051 GNU C port) or
Bison (yacc), etc..?


Victor Schutte




"stefaan vanheesbeke" <stefaan.vanheesbeke@pandora.be> wrote in message
news:SAbG8.88049$Ze.13379@afrodite.telenet-ops.be...
> Hi,
>
> I did some serious thinhing about fpga cpu's for some months, but I come
to
> the same bottleneck every time.
>
> After making small 8 bit processors with supporting assembler software on
> windows PC, ...
> After using Altera Nios, studying Xilinx Microblaze,...
>
> I every time want to make my own processor, with the best things of all
the
> previous mentioned systems, and I always stuck on the C (c++) compiler
port.
>
> Do I really need to learn everything on Linux (or cygwin) and gcc before I
> can do a successfull port? Can I do it uberhaupt on my own, or do I need a
> team of specialists?
>
> I thought on porting smaller compilers before (lcc), but I need the c++
> support.
>
>
> Can someone please point me into the right direction? Is there
documentation
> available (except the 'using and porting gcc' from Stahl)?
>
>
> Thanks.
>
>
>
>



Article: 43408
Subject: Re: fpga cpu
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 21 May 2002 19:23:37 +1200
Links: << >>  << T >>  << A >>
stefaan vanheesbeke wrote:
> 
> Hi,
> 
> I did some serious thinhing about fpga cpu's for some months, but I come to
> the same bottleneck every time.
> 
> After making small 8 bit processors with supporting assembler software on
> windows PC, ...
> After using Altera Nios, studying Xilinx Microblaze,...
> 
> I every time want to make my own processor, with the best things of all the
> previous mentioned systems, and I always stuck on the C (c++) compiler port.
> 
> Do I really need to learn everything on Linux (or cygwin) and gcc before I
> can do a successfull port? Can I do it uberhaupt on my own, or do I need a
> team of specialists?
> 
> I thought on porting smaller compilers before (lcc), but I need the c++
> support.
> 
> Can someone please point me into the right direction? Is there documentation
> available (except the 'using and porting gcc' from Stahl)?

 What is missing from these Soft Cores, that you could do better in your
own ?

 If you want to create a soft CPU for the exercise, then the Infineon 
C166 would be a reasonable starting point, as I believe it has 
a C/C++ gnu port. Anything smaller will struggle with the SW.

 There may also be soft core starting points for this, plus you 
have reference silicon to compare with :-), and the option of a 
hard core, with FLASH, which is likely to be more ecconomical 
than a soft core.


-jg

Article: 43409
Subject: i need help getting started with fpgas
From: "James Zaiter" <jzaiter@magnasys.com.au>
Date: Tue, 21 May 2002 07:28:16 GMT
Links: << >>  << T >>  << A >>
hi my name is james and my email is jzaiter@magnasys.com.au
I am new to fgpa programming and need some direction in learning to programm
these devices.
I need help with software and development board preferably xilinx
xc2000,xc3000 and xc4000 chips.
is there any free software available to use for learning purposes only as i
have a very small budget.
any help would be much appreciated.
james



Article: 43410
Subject: Off topic - a little
From: "Jerzy Gbur" <furia@wp.pl>
Date: Tue, 21 May 2002 10:22:31 +0200
Links: << >>  << T >>  << A >>
Hello
If someone is interested in creating group pl.comp.lang.vhdl (polish
language), I invite You to vote on it.
Voting take it's place on group: pl.news.nowe-grupy

Thanks

furia



Article: 43411
Subject: Re: Driving high speed external devices from an FPGA
From: mr_bert_wibble@hotmail.com (Bert Wibble)
Date: 21 May 2002 01:32:20 -0700
Links: << >>  << T >>  << A >>
Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3CE9209E.5EACAFC0@xilinx.com>...
Austin,

Thanks for your comments. The DAC part is indeed to be used in a 3G
type application and therefore clock stability is very important.

> Bert,
> 
> True.  DLLs, DCMs have jitter.  They do wonderful things, but at a cost.  For sampling clocks, or D/A clocks, always recongnize that there will be jitter, and in the most demanding applications (3G base stations), one may have to use the best
> possible LVPECL clock, differentially distributed, directly to the D/As and A/Ds (see the Analog Devices Website, and read their app notes on this subject, they are excellent in this regard).
> 
> In fact, not even a PLL may be used for these kinds of situations, especially not one integrated into an FPGA.
> 
> Once the data has been sampled by the high quality clock, it can then be processed in the FPGA, and then output and retimed by the high quality clock into the D/As.  DCMs (or DLLS) are then used internal to the FPGA to deskew the clocks, and
> ease the IO timing.
> 
> In other areas, where jitter is less of an issue (such as the audio DAC posting on this board), DCMs (DLLs) are not going to be an issue, and clock synthesis becomes the problem.
> 
> Austin
> 
> Bert Wibble wrote:
> 
> > Adrian <> wrote in message news:<ee76d20.4@WebX.sUN8CHnE>...
> > > Are you going to drive the DAC with a clock signal from your DLL? You can just use different phase shifted signals until it works and you meet your setup requirements. I would guess either a 180 degree or 270 degree phase shift would work.
> > >
> > > adrian
> >
> > No plans to clock the DAC from the FPGA DLL due to the very low jitter
> > requirements on the DAC clock. DLLs are just too noisy for this sort
> > of thing. Unfortunately.
> >
> > Bert

Article: 43412
Subject: Xilinx WP test vectors in Jedec file
From: Joerg Schneide <JSchneide@t-online.de>
Date: Tue, 21 May 2002 11:25:21 +0200
Links: << >>  << T >>  << A >>
Hello,

I have problems with the test vectors in an ABEL design for
a XC9572. They don't appear in the Jedec file, there are
only X's: "V0001 XXXXXXX...".
I have enabled the "Jedec Test Vector File" checkbox in the
"Generate Programming File" properties, there are no lower case
signal names.

How to put my vectors in the Jedec file?

When I try to program the device with the "Functional Test"
setting in iMPACT, there is an error message related to
missing BSD-Files (so told me the Answer Database at Xilinx)
but they are present and I downloaded the newest.

Is it possible that this error occurs due to the missing
test vectors? If not, how to fix this one?

I am using WP Project Navigator 4.1WP2.x, build+E-32+0
and the related iMPACT version on Win98.

Thanks,

Joerg.


Article: 43413
Subject: Altera FPGA (EPM7256AETC100-5) programming
From: petedgreenwood@yahoo.com (Peter)
Date: 21 May 2002 03:02:13 -0700
Links: << >>  << T >>  << A >>
I need to program an Altera EPM7256AETC100-5 fpga, and have available
to me the device, MPU and appropriate VHDL code. However, I don't know
which programming adaptor I need to program the device with the MPU.
Does anyone know for sure which one, as the website is a little
confusing and not much help?

Thanks in advance,

Peter

Article: 43414
Subject: Ann: Spartan-IIE development board
From: "Felix Bertram" <f.bertram@trenz-electronic.de>
Date: Tue, 21 May 2002 12:32:15 +0200
Links: << >>  << T >>  << A >>
Dear Developers,

we just introduced our new FPGA development board
which is especially well suited for FPGA-centric
processing applications.

The board is based upon a 300k-gate Spartan-IIE,
which is accompanied by the following peripherals:
- 256kx16 SRAM
- 512kx16 Flash
- 2x16 LC-display
- USB interface
- RS232 interface
- VGA output
- VG96 connector

For a convenient desktop or laboratory setup,
the board is powered and configured via USB.
The Flash memory is used to store non-volatile
configurations and data. The board fits into
industry-standard 19" racks with VG96 connector.
For easy expansion, there are up to 100 user
I/Os with may be assigned freely.

For further information, refer to the following links:
http://www.trenz-electronic.de/prod/proden12.htm
http://www.trenz-electronic.de/prod/proden10.htm
http://www.trenz-electronic.de/prod/ps-TE-XC2Se.pdf


The board is in stock and may be ordered via
our online shop. We offer discounts for orders
of two or more boards. Contact us!

Best regards

Felix
_____
Dipl.-Ing. Felix Bertram
Trenz Electronic GmbH
Brendel 20
D - 32257 Buende
Tel.: +49 (0) 5223 4939755
Fax.: +49 (0) 5223 48945
Mailto:f.bertram@trenz-electronic.de
http://www.trenz-electronic.de





Article: 43415
Subject: Re: Synchronous Single Clock Designs
From: =?ISO-8859-1?Q?L=E4hteenm=E4ki?= Jussi <jusa@cc.tut.fi>
Date: Tue, 21 May 2002 11:15:42 +0000 (UTC)
Links: << >>  << T >>  << A >>
In comp.lang.vhdl Tom Hawkins <thawkins@dilloneng.com> wrote:
I remember reading somewhere, that major target for ASIC and SOC designs 
is in the telecommunications. Therefore, the power consumption is a big 
part in any design and the easiest way to get it down is to drop the 
clock frequency. So, I think in any modern design there are several 
clock domains included. Another question is the availability to stop the 
clock in inactive parts. This also adds complexity to the design. Not 
taking any wild guesses here, just stating my point of view.

Also, I think people are using FIFOs too easily to connect their clock 
domains. I understand the need in your case as you are doing DSP and 
such, but when there is just simple register R/W -operations between two 
clock domains, FIFOs are a bit extreme. Finally, I don't think you 
should ever use tri-stated on-chip buses, they are here only to 
interface with the outside world...

regards,
juza

: I'm just trying to get an idea what percentage of logic
: designs are synchronous single clock domain
: with strict I/O, meaning no tristates or shared buses.

: Sure almost every complete chip design has several clock
: domains and most have some form of a shared inout bus.
: But I am curious what percentage of a design is purely
: synchronous single clock without shared buses.

: The last two years I have worked for an FPGA design firm
: that specialized in image processing cores.  All of our
: individual cores were built synchronous, single clock.

: At times when we needed to integrate several cores together
: and connect to external devices, we would create a top level
: design unit that contained all the shared buses and tristates.
: If we needed to move data across clock domains we would drop
: in a multi-clocked FIFO between two design components.
: But still all the major design units were synchronous,
: single clock logic void of bidirectional buses--accounting for
: about 95-98% of a total design.

: Is this pretty typical?  I'm curious what percentages are
: common within the ASIC and SoC design communities.

: Thanks for your input.

: Tom



-- 
Juza

Article: 43416
Subject: military/industrial FPGA device suggestion request
From: "Geiger Hope" <isuzu@softhome.net>
Date: Tue, 21 May 2002 12:06:55 +0000 (UTC)
Links: << >>  << T >>  << A >>
Dear all,

Could you please compare the ALTERA and XILINX devices
in terms of military/industrial specs. compliance?
We are at device selection phase of the project.

Thanks in advvance.

- Geiger


-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 43417
Subject: Re: RocketIO simulations, ISE 4.2iSP2 GT_SWIFT simulation
From: Petter Gustad <newsmailcomp1@gustad.com>
Date: 21 May 2002 14:47:36 +0200
Links: << >>  << T >>  << A >>
Brian Philofsky <brian.philofsky@xilinx.com> writes:

>           2) If not, which library/object file supplied with ISE 4.2iSP2 do I    use?
> 
> You must install the simulations files.  To find the instructions to do so, look at:
> Answer Record # 14595: 4.2i SmartModel installation - How do I install the PPC and MGT
> SmartModels that are included in the 4.2i Implementation Tools?

Thank you Brian. I did this and everything worked fine. I'm using VCS
under SPARC Solaris 8.`

Petter

-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 43418
Subject: Configuration Blues
From: "me" <cdelphia@snet.net>
Date: Tue, 21 May 2002 13:04:54 GMT
Links: << >>  << T >>  << A >>
Hello,

I am developing code targeted at a Xilinx XC2S150 and using Coregen to
instantate a Block RAM component. To do this I needed to copy over and
compile files into a local xilinxcorelib directory. Everything went fine.
Next I instantiated the component into the design and placed the following
code in the test bench (outside of the architecture) module above it:

configuration cfg_my_design of nvram is
for nvram
 for all : nvramcomp
     use entity XilinxCoreLib.C_MEM_SP_BLOCK_V1_0(behavioral)
  generic map(
   c_has_en => 1,
   c_rst_polarity => 1,
   c_clk_polarity => 1,
   c_width => 8,
   c_has_do => 1,
   c_has_di => 1,
   c_en_polarity => 1,
   c_has_we => 1,
   c_has_rst => 1,
   c_address_width => 13,
   c_read_mif => 0,
   c_depth => 6144,
   c_pipe_stages => 0,
   c_mem_init_radix => 16,
   c_default_data => "0",
   c_mem_init_file => "E:\VF36FPGA\nv_ram\RTL\nvramcomp.mif",
   c_we_polarity => 1,
   c_generate_mif => 1);
 end for;
end for;
end cfg_my_design;


The test bench compiles as well issuing messages that the appropriate
coregen entities and packages are getting loaded. However I then compile the
file below that contains the design, I get the warning message:
"# WARNING[1]: E:/VF36FPGA/nv_ram/RTL/nvram.vhd(55): No default binding for
component: "nvramcomp". (No entity named "nvramcomp" was found)"

When loading the design unit (config unit) I have no visibility to the block
ram. I do not think (at this point) I have a problem with the development
system, just the way I am trying to get the config block to show the design
file the information for the block ram I am trying to instantiate out of the
coregen library. Could someone please tell me the proper way of doing this
as well as some insight as to how the configuration block is supposed to
work.

Thanks

Mike





Article: 43419
Subject: Re: i need help getting started with fpgas
From: Russell <rjshaw@iprimus.com.au>
Date: Tue, 21 May 2002 13:06:59 GMT
Links: << >>  << T >>  << A >>
James Zaiter wrote:
> 
> hi my name is james and my email is jzaiter@magnasys.com.au
> I am new to fgpa programming and need some direction in learning to programm
> these devices.
> I need help with software and development board preferably xilinx
> xc2000,xc3000 and xc4000 chips.
> is there any free software available to use for learning purposes only as i
> have a very small budget.
> any help would be much appreciated.
> james

You can download xilinx webpack and make a jtag cable programmer.
If you can make good circuit boards, you can make and program
your own kit. You'll need to learn vhdl, verilog, or schematic
entry.

Article: 43420
Subject: Re: How to generate fractional-N clock ?
From: mrand@my-deja.com (Marc Randolph)
Date: 21 May 2002 06:18:53 -0700
Links: << >>  << T >>  << A >>
allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3ce9d59e.89244667@netnews.agilent.com>...
> On Mon, 20 May 2002 16:42:46 +0200, "Marcel"
> <marcelgl-hates-spam@xs4all.nl> wrote:
> 
> >Hi,
> >
> >I need to generate a tunable clock  in the range from 18Mhz - 30Mhz with
> >100Hz resolution.
> >I was considering to use an external VCO and implement a PLL in the FPGA.
> >But I was wondering is this
> >also can be done in another way.
> >
> >The main problem is that the clock is used for audio D/A, so it must be a
> >low jitter clock.
> >
> >Any suggestions ?
> 
> 1.  Audio is usually only sampled at certain rates, e.g. 8.0000kHz
> (and multiples), 11.025kHz (and multiples) and 48.000kHz (and
> multiples.)
> ... why do you need to use other frequencies?  And why 100Hz
> resolution on your high speed clock?

Either he isn't sampling audio for human consumption, or he is making
a typo and meant 18kHz to 30 kHz.

30 MHz is WAY overkill for anything that humans could hope to hear. 
Over 500 times overkill.
 

> 4.  The 5ns jitter you mentioned is *way too high* for high end audio.
> You will need to do some research to work out what the requirement
> actually is, though.

5 ns at 30 MHz is 0.151 UI.  Not horrible, but not great.

But if he perhaps meant 30 kHz rather than 30 MHz,
5 ns at 30 kHz is 0.000150 UI.  I dare say that would be better than
anything the human ear could hear.

   Marc

Article: 43421
Subject: RS232 a utility for debugging serial data transfers between devices.
From: john@fcoder.com (Evgeny Shamin)
Date: 21 May 2002 06:39:16 -0700
Links: << >>  << T >>  << A >>
Hello 
Hope this information could be useful for some of you.

Look RS232 is a program for debugging serial data transfers between
devices, such as PC, modem, projector, etc. using one of the
accessible COM ports (1-6).
Look RS232 will help you send data to the selected COM port, view
device response in a handy form and trace the message traffic step by
step or using break points.

For more info please visit here:
http://www.fcoder.com/products/lookrs232.htm

Yours respectfully
Evgeny Shamin

Article: 43422
Subject: Shift register or state machine
From: "Cyrille de Brébisson" <cyrille_de-brebisson@hp.com>
Date: Tue, 21 May 2002 07:43:38 -0600
Links: << >>  << T >>  << A >>
Hello,

I am trying to make a simple design in which I have 16 32 bit wide input
that I need to put in a buffer and then deliver back as 8*64 bit output.

I was wondering if it was better to:

implement a 16*32 shift register, shift my data in, and after 16 cycles,
output the 8*64 bits, or
store each 32 bit value directly in it's final position in the 16*32
register using a state machine to know where to store each data.

Which one do you think is the 'cleanest' design, the simplest design, which
one would you recomand.

regards, Cyrille



Article: 43423
Subject: Re: SDRAM pricing
From: Jim Thomas <jthomas@bittware.com>
Date: Tue, 21 May 2002 09:49:19 -0400
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> I am finding that.  I just strikes me as odd that I can buy exactly one
> memory module at a quarter or even an eighth of what the equivalent
> SDRAM chips will cost me if I buy 1000 of them.  But then electronic
> purchasing has never been logical.. :)

Hey Rick,

Any reason you couldn't just plunk down a DIMM socket?
I suppose form factor might be one.

-- 
Jim Thomas            Principal Applications Engineer  Bittware, Inc
jthomas@bittware.com  http://www.bittware.com          (703) 779-7770
The sooner you get behind, the more time you'll have to catch up

Article: 43424
Subject: Re: RPMs
From: hamish@cloud.net.au
Date: 21 May 2002 13:59:57 GMT
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> wrote:
> UCF will work on a hierarchy, but the UCF itself is flat.  That means that everything in
> the UCF has to have full hierarchical names.  Ideally, there would be a hierarchical UCF
> so that any components that are repeated in there only need the placement described
> once.  

You can sort-of use an NCF to do this; you're allowed one NCF per
EDIF, so you would have to split up your synth project.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search