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hi, I read in a post previously that VHDL/Verilog programming style differs when being written for an FPGA from being written for an ASIC. Is there any website which mentions these differences ? I'm looking to see what should I take care of when programming for an FPGA. Thanks, PrashantArticle: 42126
Try here: <a href="http://www.xilinx.com/isp/microprocessor.htm">Products : Microprocessor Solution</a> Kevin Hansen wrote: <blockquote TYPE=CITE>A few months ago I downloaded some JTAG-programming C source code, from the <br>Xilinx site, that could be modified for my application. I have misplaced <br>the files and am looking for them again, but I haven't been able to find <br>them. Can anyone point me to where they are? Thank you, <br>Kevin Hansen</blockquote> </html>Article: 42127
Just thought I'd put up a short review of this book as well. I bought it on the strength of the review (below) posted in these newsgroups I'm not going to write about what topics it covers, I'm just aiming to provide some overall personal opinions on the book. I'm afraid that the ad-hoc style of presentation with poor and inconsistently styled diagrams is the first thing to hit you. Tables of text that look like they were converted to bitmap and then stretched are really unacceptable in this day and age. Same applies to certain equations (how long would that have taken to typeset properly?)Probably an easy way of scanning source material though :( Undeniably there is useful information here, but unfortunately, anyone who has looked through Altera and Xilinx's app notes and followed a few links to recommended articles posted on the news group will be in for a disappointment. For an example Altera clocklock/clock boost (Altera App115) is reused, as are numerous Xilinx/Altera Fifo discussions. (With permission I hasten to add). I felt a little cheated by the amount of information that was directly lifted from other freely available sources. Granted there's a CD with a lot of the files on, and the book does provide a central repository, but I don't think that justifys the expenditure of your effort. There are items that everyone from newcomers to moderately well-versed HDL engineers will learn, but it isn't presented in a coherent style, instead my impression is that its stitching articles together in the hope of getting a book published quickly. The fact that its trying to be a dual language book is also intensely annoying with page upon page of listings to skip (and providing a six page listing of repetitive 32bit CRC equations is not my idea of a well-chosen example when extracts from this code would have been much better). Most of the listings are very simple and don't add too much value to the overall content. You may think I absolutely loathed the book. That's not the case as it does present some useful cookbook-style topics, but its lack of a coherent presentation style, poorly chosen example code and in the end is a missed opportunity. Ben is extremely helpful in these newsgroups and I did hold off before publishing my comments in the hope that my disappointment would temper somewhat, but at the end of the day I'd much prefer to give you a list of seven or eight app notes/articles that are freely available that provide a similar amount of content. I really hope Ben doesn't take too much offence as it is books like this that when executed well deliver a fabulous wealth of information. This one falls short of the mark in several ways, sadly. Now if Ray and Ben got together with an independent typesetter... there could be a killer cookbook :) Paul Baxter > strut911@hotmail.com (strut911) wrote in message news:<4379d3e0.0203161247.eef8730@posting.google.com>... > > its a little rough around the edges in appearance (sorry mr. cohen) > > but its worth its weight in gold in terms of the lessons that can be > > learned from it. i had it for one day and i already learned about five > > new things, and i thought i had been in the industry long enough to > > consider myself a semi-professional. there are all sorts of tips and > > tricks that can be used to combat well-known design issues (i never > > thought of using a flancter before) and it goes through the real way > > to write verification suites (instead of paying lip-service to some > > simple testbenches). overall, i am very happy with it. some issues i > > have with it are: leans a bit more towards vhdl than verilog, although > > he obviously tries to balance the two languages, synplify pro > > schematics are sometimes a bit tough to follow, and in some cases it > > might be slightly better to abbreviate the code listings instead of > > allowing it to take up multiple pages. > > but like i said, in the true spirit of independent publishing, its > > rough around the edges, but definitely written by an expert. i will > > definitely recommended the people at work to pick up a copy. the only > > thing mr. cohen needs to worry about is that he might not get as much > > consulting work since he already present many solutions to common > > problems in his book. > > i just wanted to give everyone a heads up on my experience with this > > book. if you want to learn more about chip/fpga design and > > verification, at least the way it is done by professionals, i > > recommend this book. or if you want to support good independent > > publishing and encourage more experts to publish books where they can > > actually make money and provide quality instruction (are you listening > > mr. andraka?), then i would also recommend this book. this is just my > > two cents. i hope other people can present their reviews of this or > > other industry books also. > > strut911Article: 42128
"Pete Koziar" <koziar.pete@orbital.com> schrieb im Newsbeitrag news:2951d198.0204160412.2414e128@posting.google.com... > We have an application where we desire to remotely program a new FPGA > image into a flash ROM then signal the system to reinitialize itself, > including reloading the Spartan II. > > The Spartan II is configuring through slave parallel mode. > > How do I get the Spartan II to clear its internal memory and reload > itself? I've tried just dropping the Program line, but neither Init or > Done ever goes low. Pulse PROGRAM LOW (>300ns), then some hundred us after PROGRAM is HIGH again, DONE is LOW and INIT is HIGH (both are open drain). Then you start to clock in the data, if there is a CRC error, INIT will go LOW. After all bytes are transfered, you need some additional clocks (4 or 6, not sure at the moment) to start te FPGA (release global reset, Tristate etc.) Then DONE will go HIGH. -- MfG FalkArticle: 42129
"Vladislav Vasilenko" <vlad@comsys.ntu-kpi.kiev.ua> schrieb im Newsbeitrag news:3CBC52AF.438A6514@comsys.ntu-kpi.kiev.ua... > Can you explain me answer or where can I read detailed information about The problem is, that the FPGA will ALWAYS run at full speed, even if you design has only frequencys of some kHz. That means, it will switch VERY fast. In this moment, it requires a big current surge form the power supply network. If you connect just 1/2 of the VCC/GND pins, this will increase the inductance of the power supply network as seen from the FPGA and during the small, but powerfull current spikes, the voltage will drop, causing malfunctions. -- MfG FalkArticle: 42130
Hello, We are working on a BIG design, and we are looking for a Virtex II based development board with a XC2V4000 or higher. Does someone has an idea of where to find one? Regards, CyrilleArticle: 42131
Does anyone know of any FPGA GPS Cores that are out on the market? KentArticle: 42132
koziar.pete@orbital.com (Pete Koziar) writes: > Does anyone know of a command-line utility for loading the Xilinx > XC9572XL and the Spartan II via JTAG? I would like to set up a batch > file for our medium size production run where the whole process is > automated to the point where the tester plugs in the JTAG port and > hits "Enter." > > The operations it needs to do are: > > o Load a CPLD > o Load a Spartan II > > After that the batch file would run our application to program the > flash chip. > > Does such a thing exist or do we need to write it? You don't say anything about what kind of JTAG programming device you are using. If you are using a XILINX MultiLINX or similar then jtagprog should do the job. I've done something like: jtagprog -batch jtag where the file jtag.cmd contains something like part XC95144XL:pld program -v pld quit You can also generate SVF files from jtagprog by adding the -svf option and then copy the generated file to your other JTAG system. A similar file for a scan chain of two 18v04's looks like: part XC18V04:TOP_0 XC18V04:TOP_1 erase -f TOP_0 erase -f TOP_1 program -v TOP_0 program -v TOP_1 quit Where the two MCS files TOP_0.mcs and TOP_1.mcs have been created using promgen. > I know that Xilinx has a big honkin app in WebPack, but the problem is > that it takes a fair amount of resources and requires too much manual > intervention. What we're looking for could potentially be loaded on a > little embedded PC and run automatically. I just start a script which does synthesis, map, par++, and then finally jtagprog. The next day the 18v04's for the Virtex device are ready for testing... Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 42133
I found answer 10901 and tried solution #1. I could not get it to work (I could not get the External Macro Pin to be available.) I looked at solution 2 (xapp123) but it seems to apply only to the tri-state buffer if I read the readme correctly. Any help? Theron Hicks wrote: > Hi, > My design is somewhat structural at the highest level. I would like > to floorplan the lower level modules and then have that floorplan (and > perhaps even routing) be retained at the higher level. Is that > possible? Is there some hidden trap that I need to be aware of (other > than the potential problem with the blocks not being able to be placed)? > > If this is a reasonable and wise idea, how do I do so? My code is VHDL > and my target device is the Spartan2E. I am currently using ISE4.1 but > I have ISE4.2 available. (I just haven't installed it yet, as I would > rather avoid changing software in mid project.) > > Thanks, > Theron HicksArticle: 42134
Jeff, My suggestion would be to start debugging the problem by programming the FPGA through the JTAG chain. Don't worry about programming the part from the PROM at this point. -Generate the .bit file with startup clock set for JTAG Clock and readback/reconfiguration enabled, as you mentioned. -Set the Mode pins for Boundary Scan mode -Launch iMPACT and initialize the chain. The Spartan-II will appear as a Virtex because they use the same IDCODEs. -You can assign the $xilinx\xc18v00\data\xc18v01.bsd file (BSDL file) to the PROM instead of a .mcs file for the purpose of bypassing the PROM. -Assign the .bit file to the Spartan-II as you did before -Right-click on the Spartan-II and program it. At this point, the critical question is whether or not the DONE pin went high. If it did, configuration was successful, and the problem is somehow related to the design or your board setup. Make sure that your oscillator is hooked up and oscillating, and make sure that any enable signals are correctly driven. Check your design.pad file (the PAD report) and make sure that design clock input is locked to the correct pin, and that the LED outputs are locked to the correct pins. Hope this helps! --Brendan jeff wrote: > I've been trying to make the counter demo work with > Insight's $125 Spartan II demo board, but it fails. > All I get is a blank LCD. It should have incrementing > numbers. > > I got the Verilog source for the counter demo here: > http://208.129.228.206/solutions/kits/xilinx/spartan-ii.html > > I created a project in Webpack 4.2, and it compiled OK. > > In the process called "Generate Programming File", I > opened the property box, and selected CCLK as the startup > clock. I ran the process, and then went to Generate > Prom File, and made the counter.mcs file. > > Then I went back again, and set the startup to JTAG clock. > I ran the process, which made a counter.bit file with > the JTAG clock. I didn't make a prom file, because this > file is for the Spartan II chip. > > (I'm sure I selected the clocks correctly, because if I > don't the iMPACT program tells me). > > After that, I clicked on Configure Device. I have the board > jumpered for JTAG mode (M1 jmpr on, M0 & M2 off). I clicked > on Initialize chain, and it shows a 18V01 and a XCV100. > I assign counter.mcs to the 18V01 and counter.bit to the > next chip. After I do that, the XCV100 changes to a > XC2S100. Now I right-click on the 18V01 and tell it > to program. It succeeds. > > Now I unplug power from the board, and re-jumper it for > Master Serial mode, which is M0,M1,M2 jumpers all on. > I plug in power, fully expecting the LCD to start incrementing > but it doesn't. Nothing happens. Can anyone tell me > what I'm doing wrong ? > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 42135
Hi Theorn, You need to be in macro editing mode in FPGA Editor, look for an .nmc extension in the banner. If it's .ncd instead, you need to first do a "save as macro". Once you're in macro editing mode, an external pin is added by selecting a component pin (not just a site pin) and running the command Edit-->Add Macro External Pin. Fill in the resulting form. You need to give the external pin the same name as the corresponding port name for the black box in your logical design. Hope this helps, Bret Theron Hicks wrote: > I found answer 10901 and tried solution #1. I could not get it to work (I > could not get the External Macro Pin to be available.) I looked at solution > 2 (xapp123) but it seems to apply only to the tri-state buffer if I read the > readme correctly. Any help? > > Theron Hicks wrote: > > > Hi, > > My design is somewhat structural at the highest level. I would like > > to floorplan the lower level modules and then have that floorplan (and > > perhaps even routing) be retained at the higher level. Is that > > possible? Is there some hidden trap that I need to be aware of (other > > than the potential problem with the blocks not being able to be placed)? > > > > If this is a reasonable and wise idea, how do I do so? My code is VHDL > > and my target device is the Spartan2E. I am currently using ISE4.1 but > > I have ISE4.2 available. (I just haven't installed it yet, as I would > > rather avoid changing software in mid project.) > > > > Thanks, > > Theron HicksArticle: 42136
Different documentation seems to say different things about what IO standards are supported in Spartan-II. One table says it doesn't support PCI33_5, but another document about the Virtex (the Xilinx site takes you to that doc since Spartan-II and Virtex have the same IO) says it does support PCI33_5. Does anyone know if it actually does or not?Article: 42137
All,
Think first principles,
remember long division? now think binary!
think async or sync
That's all folks :-)
"kn" <kn@cetic.be> wrote in message
news:1b1252c2.0204160700.379a8571@posting.google.com...
> Hi all
>
> I am trying to implement a module in VHDL which performs an 8 bit
> disvison operation.
> I am looking for an efficient algorithm suitable for hw
> implementation.
>
> Kind Regards
> kn
Article: 42138That was the problem, Thanks! Bret Wade wrote: > Hi Theorn, > > You need to be in macro editing mode in FPGA Editor, look for an .nmc extension > in the banner. If it's .ncd instead, you need to first do a "save as macro". > Once you're in macro editing mode, an external pin is added by selecting a > component pin (not just a site pin) and running the command Edit-->Add Macro > External Pin. Fill in the resulting form. You need to give the external pin the > same name as the corresponding port name for the black box in your logical > design. > > Hope this helps, > Bret > > Theron Hicks wrote: > > > I found answer 10901 and tried solution #1. I could not get it to work (I > > could not get the External Macro Pin to be available.) I looked at solution > > 2 (xapp123) but it seems to apply only to the tri-state buffer if I read the > > readme correctly. Any help? > > > > Theron Hicks wrote: > > > > > Hi, > > > My design is somewhat structural at the highest level. I would like > > > to floorplan the lower level modules and then have that floorplan (and > > > perhaps even routing) be retained at the higher level. Is that > > > possible? Is there some hidden trap that I need to be aware of (other > > > than the potential problem with the blocks not being able to be placed)? > > > > > > If this is a reasonable and wise idea, how do I do so? My code is VHDL > > > and my target device is the Spartan2E. I am currently using ISE4.1 but > > > I have ISE4.2 available. (I just haven't installed it yet, as I would > > > rather avoid changing software in mid project.) > > > > > > Thanks, > > > Theron HicksArticle: 42139
Virtex and Spartan-II do support PCI33_5, but Virtex-E and Spartan-IIE don't. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Sean wrote: > > Different documentation seems to say different things about what IO > standards are supported in Spartan-II. One table says it doesn't > support PCI33_5, but another document about the Virtex (the Xilinx > site takes you to that doc since Spartan-II and Virtex have the same > IO) says it does support PCI33_5. Does anyone know if it actually > does or not?Article: 42140
Hi, I am currently having a problem with Xilinx ISE WebPACK 4.2WP0.0's PAR. In ISE WebPACK 4.1, when I specified the number of routing iterations to whatever number, PAR routed it whatever many times even if it thinks the design has no chance of meeting timing requirements. However, somehow things have changed in ISE WebPACK 4.2, and now even if I specify the number of routing iterations, let's say to ten iterations, PAR always gives up after two routing iterations. Has anyone noticed this behavior, and is there a way to override the current behavior? Some may suggest that I should manually floorplan my design, but I already did that (I am using UCF flow.), and what I am trying to do is to run multiple routing iterations after manually floorplanning my design. Others may suggest that I should go back to ISE WebPACK 4.1, but the newer version of ModelSim XE-Starter that comes with ISE WebPACK 4.2 'seems' to run faster than the version that comes with ISE WebPACK 4.1, so I don't want to go back to ISE WebPACK 4.1. Thanks, Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.)Article: 42141
You can build placed macros in your source: to do so you need to
structurally instantiate anything you want to place and then put RLOCs on
it. That works fine for 3.3sp8, however you will find out that the
floorplanner in v4.x wrecks your virtex/virtexE/spartanII/spartanIIe RPMs
because of a nasty bug that moves placed stuff around willy-nilly. Word
right now is that it won't be fixed until the next major release, so if you
go this route you are confined to 3.3 software. Ask your FAE for an update
to the timing files if you do stick with 3.3
Theron Hicks wrote:
> Hi,
> My design is somewhat structural at the highest level. I would like
> to floorplan the lower level modules and then have that floorplan (and
> perhaps even routing) be retained at the higher level. Is that
> possible? Is there some hidden trap that I need to be aware of (other
> than the potential problem with the blocks not being able to be placed)?
>
> If this is a reasonable and wise idea, how do I do so? My code is VHDL
> and my target device is the Spartan2E. I am currently using ISE4.1 but
> I have ISE4.2 available. (I just haven't installed it yet, as I would
> rather avoid changing software in mid project.)
>
> Thanks,
> Theron Hicks
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 42142Hi, I am looking for spec/details on Telecom Bus (TelecomBus). I searched on the web and all I could get is a number of links to PMC Sierra which offers Telecom bus bridges, converters, serializers etc but does not offer much details about Telecom bus protocol. Neither could I find anything on the IEEE standards website. I am designing an ATM Cell Processor in FPGA which has Telecom bus interface. I would greatly appreciate if someone can point me to relevant info on Telecom Bus. ThanksArticle: 42143
HOTMan is a program/API for management and delivery of Xilinx Virtex/XC4000 bitstreams. It can run locally or remotely and includes bitstream compression and bitstream version control. It uses C++ for low level access to the hardware and Java for the GUI and networking. It has source code examples of programming through the Xilinx download Parallel Cable III (I'm told Cable IV is backwards compatible) in both Serial Slave and Jtag 1149.1. It currently runs under any of the NT flavors and is being ported to Solaris and Linux. With this system it is easy to program applications that help test and debug your hardware. Not only does it deliver bitstreams but it also enables you to add your own commands to the GUI interface and gives you a quick and reliable method of remote test and upgrade. We need some beta testers to use this software and report back any bugs or other anomalies. If you are interested please mailto:jas@vcc.com . Thanks Steve Casselman, CEO Virtual Computer Corporation -- Remove the .nospam for the correct reply addressArticle: 42144
Apeak wrote: > > Is there a copy of Synario v2.3 available either for free or purchased? > I start learning about programming the GAL22V10 and someone recommended > Synario v2.3. Synario is no longer a standalone tool. You could go to the Atmel web, and get AWINCUPL.EXE, which is CUPL, and this supports 22V10, and std SPLDs ( 16V8 + ). CUPL can run via the IDE, or with a programmers editor, and includes conditional compile controls & optimise choices. CUPL can also create JED test vectors for post-pgm functional test in most programmers. - jgArticle: 42145
Why is it that all the production people like to get to work real early and then leave early, while the engineers arrive late and work late, so that when you really need a big chip replaced there's nobody around to do it for you? JohnArticle: 42146
Hi Austin and Newsgroup, Sorry, the part is an XC2S50PQ208. XST, 4.2i sp1. No daisy chain, just a single device, and there are no other devices on the JTAG port. I have tried with the M0, M1, M2, programming mode pins set to 010, slave parallel mode and with them set to 100, boundary scan mode. Same results both times. The FPGA is not configured properly(exhibited by simple single SRL16E not working correctly and other portions of design faulty) when it is configured for a second time over JTAG. I had a look through xapp188 - configuration and readback of sp2 fpgas using boundary scan. On page 9, fig 5, it implies to me that the shutdown sequence is run when the FPGA is configured for a second time over JTAG. So the configuration memory doesn't get cleared the second time its programmed. Well, thats one difference I noted, dunno if thats significant. Ok, I'll submit a case. Regards Andrew Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3CBC34F8.15E46326@xilinx.com>... > Andrew, > > I would need to know which part to comment. > > Sometimes the startup sequence at the end of configuration may not behave correctly if there are other older > devices in a daisy chain (ie Virtex II with Spartan II) as early bitgen option defaults were not correct for > Virtex II and daisy chaining (since been corrected in subsequent service packs). > > As well, Virtex II ES parts required a bitgen switch set for generating the correct bitfile for the ES > material. > > Often when we encounter one of these 'cycle the power' mysteries, we do not follow it to the end and find out > what was really going on: I would advise against that. File a case on the hotline, and follow through. I > despise mysteries! >Article: 42147
"John Larkin" <jjlarkin@highlandSNIPTHIStechnology.com> wrote in message news:Xt68PBLDZOsrEop6+udYs5ye81GL@4ax.com... > > Why is it that all the production people like to get to work real > early and then leave early, while the engineers arrive late and work > late, so that when you really need a big chip replaced there's nobody > around to do it for you? Im an engineer - i arrive early and work late ;-) Leo Havmøller.Article: 42148
Quartus Megawizard generates Verilog or VHDL files for the NIOS core for simulation. It may be slower than an instruction set functional model. Jim "Mats Brorsson" <Mats.Brorsson@imit.kth.se> wrote in message news:a9gnr5$3f7$1@news.kth.se... > Hi, > > I'm considering using the NIOS processor from Altera for lab exercises in a > computer organization course and would then like to have an instruction set > simulator for this processor. With the Altera Excalibur NIOS development kit > there is a simulator, but I can't find the source code for it. Anyone knows > of another simulator for this architecture? > > Please respond by email since I do not regularly read the news groups. > > Regards > > Mats Brorsson > Mats.Brorsson@imit.kth.se > > >Article: 42149
On Tue, 09 Apr 2002 03:50:25 GMT, Ray Andraka <ray@andraka.com> wrote: Hi, I recently discovered a problem that not all applicable paths covered by a timespec were checked by the software. I had a multichannel design and the same timespec for all channels. But in the report I saw that the parts covered were only half for a certain channel. There were paths not meeting the timespec which didn't get reported !!! And concerning the post P&R simulation, there are a lot of cases were timing errors will be not found by this simulation. The simulator uses the max. time in all paths, also the clock paths. So a design might work in the simulator but since there is a skew between paths in practise the real implementation might have problems! Regards Andreas >You mention all timing constraints were met. What about constraint coverage? >It is entierly possible to have all constraints met with only a small portion >of the design actually constrained. If your design is passing a functional >simulation and timing, but does not work, the next step is to carefully examine >your timing constraints to make sure you haven't got something important >unconstrained, followed by doing a post-route simulation to verify that the >routed design does indeed match the input design. There have been a few cases >where the xilinx tool is the culprit, but much more often it is the result of a >change in the synthesizer. > >al wrote: > >> We were using 3.1i and works fairly stable with no major problems. Last >> week, we loaded up the 4.1i and decided to give it a try. We used the same >> set of VHDL design files, UCF constraint and batch file. At first, tool >> seems working fine -- we are able to save compile time by about 40% and all >> timing constraints are meet. Well, not so happy yet -- the output binary >> doesn't not work in our hardware, seems like there is some sort of timing >> problem somewhere. We called up xilix hotline, this support guy by the name >> of Justin have no idea of what he is talking about -- keep telling me to do >> a post route timing simulation on my 1.6 million gate design. Anyway, bad >> tool + bad support = unhappy customer.
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