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Did you do a post P&R simulation or at least a post translate (gate level) simulation before burning a Configuration PROM or the FPGA? When you simulate it, you might see some signals turning undefined, but in practice, those undefined signals will be something if you attached an oscilloscope. If you happened to use XST, I have seen, in the past (WebPACK 3.3), XST messing up clock enabled related stuff when "Complex Clock Enable Extraction" option is checked. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.)Article: 42101
Hi, Well, I have got my SRL16E working. It does not appear to be any problem with my VHDL or how the init attribute was being passed to the tools. (As an aside, from reading previous posts on this newsgroup, my understanding was that generic was used for simulation, and attribute was used for the Xilinx tools, However, by looking at the EDIF netlist after synthesis, and FPGA editor after PAR, the generic init parameter gets used by the Xilinx tools, not the attribute. Synthesis with XST. 4.2i) It appears the FPGA was not being configured correctly. It took me a while to figure this out because a fair whack of my design did operate correctly after configuration, so I had no reason to question the configuration. I eventually found that programming with JTAG without cycling the power first created problems. It seems you can't program twice in a row with JTAG without cycling the power in between. Is this true or do you think this is indicative of a problem with the hardware? I searched the Xilinx answers data base, Answer Record # 10169: and Answer Record # 9013: come close but do not explain the behaviour observed. If I cycle the power before JTAG programming, it works every time. If not, portions of the design work, and interestingly the SRL16E portion does not. Regards Andrew cablow@yahoo.com (Carlton Blow) wrote in message news:<ae3b23a3.0204151046.482d1b5d@posting.google.com>... > Hi Andrew, > > The problem you are experiencing lies in the transfer of > generic/attribute information of the primitives from the VHDL code > over into the Xilinx tools. Essentially, your generic/attribute > information is being ignored somewhere during your implementation > flow. Most likely during synthesis (check the resulting EDIF output > file to confirm). > > Your syntax appears correct. However from past experience I have found > that sometimes the attribute(s) supported by the synthesis tool are > not always recognized by the Xilinx tools. I have also found that > direct manipulation of the primitive generic values to values other > than the default result in implementations that differ from the > results observed during a functional simulation. > > It should also be mentioned that this "problem" you are having is not > limited to just the SRL16E's. You may also see a similar situation if > for example, you instantiated LUT based or block based memory > primitives with initialization values that differ from the default > (all zeros). > > With all that being said, I would propose to you the following: > > 1 - Do not manipulate the generic default values of the primitives > directly. For a functional simulation, manipulate them instead by > using a configuration statement(s). > > Thus the init generic would stay at the default value of "0000", > however the configuration statement(s) would override this to set it > at your desired value of "0001" for the functional simulation. > > If the problem is with the direct manipulation of the generics, your > attribute should then pass through the implementation flow and the > initialization value would then be correctly processed by the Xilinx > tools. > > 2 - If (1) does not work, then also remove the init attribute. > Instead, add the desired initialization value(s) into the accompanying > UCF file of your design. > > For details on adding the initialization info into the design's UCF > file, refer to the Xilinx support section of the Xilinx website. There > is an app-note or other detailing how to perform this function. > > Regards, > > Carlton > > Jonathan Swift <jonathan.swift@xilinx.com> wrote in message news:<3CBADFEF.F81723D5@xilinx.com>... > > Hi Andrew, > > > > Have you checked the contents of the LUT in FPGA Editor to ensure that the > > INIT value has been applied correctly? > > You can see the INIT attributes for every component using this. > > > > As to your code, everything looks fine and you should be able to > > initialise the contents of the SRL using this. > > > > Hope this helps, > > > > Cheers, > > > > Jonathan > >Article: 42102
In article <3CBB6B46.54DF2EA5@xilinx.com>, micholba@xilinx.com (Michol Bauer) wrote: > (NOTE: W95 is not supported.) Are you saying that the parallel cable isn't supported or the software. I say that because I have a shiny new Parallel IV cable and can only almost get it to work with Webpack on one machine (Win 98) but not at all on another. Should I send it back ? JonArticle: 42103
(I added comp.arch.fpga to distribution) Tom Loftus wrote: > As a hardware engineer who started drawing schematics on paper, > transitioned onto EDA systems and now uses advanced HDL's and > synthesis tools, I cringe when I see this type of > article (March 2002 issue of Embedded Systems Programming) Me too, and for both the same, and some different reasons. Having just finished an evaluation of Celoxica's "Handel-C", I have some specific problems with that part of the article. I'm also a hardware engineer, and while I do see some value in hardware higher level languages (HHLL's), I also see some real limits to them, and the tools that support them. Specific problems with the Embedded Systems Programming article: "Handel-C is a slight tweak of the C language." I disagree. HandelC does share syntax with C. However, even the seemly simple "par" statement, which means: "run the following statement block in parallel", is far more than a slight tweak to the language, as it creates all sorts of new issues that are not present in non parallel C. Using parallelism is not simple, if it was, compilers would do it for programmers automatically. I would also say that data types are rather different, and there are other differences. "In fact, you won't design hardware at all." I disagree. Perhaps you might design an ASIC or a FPGA with a HHLL. But before the signals from that chip hit the circuit board, at least some hardware design needs to be done, for signal integrity, driving real devices, EMI and EMC, clock and power management, etc. As well, I think that HHLL based chips will be in the minority for years, due to limits in the HHLL tools. The digital signal processing (DSP) world, for example, needs a very good implementations of their designs, and the HHLL's will not give this. Why? In a word, floorplanning. "no code profiling" I really disagree. It's easy to write something that is expensive or extremely expensive to produce in hardware. The HHLL tool had better do code profiling, as tracking back from the resulting hardware to the offending line of source may not be trivial. Celoxica's profiling isn't as good as I would like to see, but at least they do seem to understand that this is important. "no integrating the software with the hardware" I really disagree. Sorry, but sometime this wonderful code you put into the chip need to be tested with the real world, and the correlation (or lack of) between what you assumed would happen and what really does happen will be observed. The code in the chip may well be software (of some unknown firmness), but there is something outside it, that it communicates with, that is, at very least, closer to hardware. Leaving enough time for integration of the most common failures in scheduling projects. I try to never forget just how messy this stage can be. -- Phil HaysArticle: 42104
I use W2K Pro.
Vladislav Vasilenko
Pete Koziar wrote:
>
> What operating system (Windows 95, 98, 2000) are you running on in the PC?
>
> - Pete Koziar
> Principal Engineer,
> Orbital Sciences/TMS
> Columbia, MD, USA
>
> vlad@comsys.ntu-kpi.kiev.ua wrote in message news:<3CBAD522.3A7155E4@comsys.ntu-kpi.kiev.ua>...
> > Hi All
> > I made JTAG cable and it works normally on Foundation 3.3i in GUI JTAG
> > programmer
> > but when I tried configure device with iMPACT tool from WEB PACK 4.2
> > then cable is not detected ("Cable connection failed") . Where is
> > problem ?
> > Thank in advance.
> > Vladislav Vasilenko.
Article: 42105Here is content of summary file. <<fileset.txt>>-------------------------- 4-16-2002 09:25:36:: product=Xilinx WebPACK 4.2 4-16-2002 09:25:36:: version=4.2WP0.x 4-16-2002 09:25:36:: Registration_ID= 4-16-2002 09:25:36:: summary=Location: C:\xilinx_webpack Components: Design Entry CPLD Fitter Spartan Fitter Virtex Fitter CPLD Programmer FPGA Programmer ECS CPLD Libs ECS FPGA Libs XPower HDLBencher StateCAD ---------------------------------------------- I use W2K Pro. Best regards, Vladislav Vasielnko. Michol Bauer wrote: > > Vladislav, > > Check your XRAY file for 4.2 to make sure the that > the fileset.txt shows the parallel driver was installed > "summary=Parallel Cable III Driver". > > (NOTE: W95 is not supported.) > > Regards, > Michol BauerArticle: 42106
In the meanwhile, I also got the answer from Altrera. They confirmed they had a problem with Win98: >There have been a few isolated cases where this error occurs. We >have discovered the cause of this and we have fixed it in the next version >of Nios which will be released in a few weeks. Regards, Jeremy Altera Europe But I have to notice that previous version of Nios (1.1.1.) worked OK. Of course, sometimes it reported errors during system generation (probably because of Win98) but except this it worked fine. There's been another explanation from our distributor for Altera also: >Dear Matjaz, > >I do not know still what is a reason of the problem you had got. What I can >confirm, the problem is infrequent. You are only one person in the large >area where I have to operate who run into it. > >In the case you have the possibility, replace the W98 by W2000 please. >Altera has announced to finish support for the W98 by end of Q2. The change >is more important for Nios users than for others. Some security functions >which are "converted" from Linux to W2000 have to be simulated under W98. I >do not belief the simulation is without any problem. You told me you use >128MB operating memory. Quartus is guaranteed to work OK at 256MB like a >minimum. I have some experience with Quartus on PC with 64MB only. It never >starts correctly. It stop with different warnings start per start. > >The above I do not think is the main reason for your problems, but I think >it make sense too. I'll probably go for Win2000. Thanks for advice. MatjazArticle: 42107
Hi, I'm considering using the NIOS processor from Altera for lab exercises in a computer organization course and would then like to have an instruction set simulator for this processor. With the Altera Excalibur NIOS development kit there is a simulator, but I can't find the source code for it. Anyone knows of another simulator for this architecture? Please respond by email since I do not regularly read the news groups. Regards Mats Brorsson Mats.Brorsson@imit.kth.seArticle: 42108
Our project based on XC2S50-PQ208 chip. This chip has many Vcco,Vcint and GND pins. Number of pins that should be connected affect on complexity and cost of PCB. Datasheet reports that PQ208 package has one Vcco bank and therefore all Vcco pins connected internally in chip. Can I connect only few pins to Vcco and others Vcco pins leave unconnected ? What a minimum of Vcco , Vcint, GND pins should be connected to chip on PCB? Best regards, Vladislav VasilenkoArticle: 42109
Hi! > I'm looking for a SpartanXL demo board. Any good ones out there? > > Something I can download with my XChecker cable, and get at all the > pins. Look at http://www.digilent.cc/. They have a nice board. It is available with a Spartan or a SpartanXL FPGA (3.3V version). It is quite cheap, I think less than $100. The only problem is, that Spartan and SpartanXL are not supported by Xilinx WebPack. Downloading the configuration is done by a parallel cable. If you need instructions or souce code, you can have mine. I wrote a small Pascal program for Linux, but it is easily ported to whatever you need. Bye HansiArticle: 42110
Mike <none@null.net> wrote in message news:<ee763f4.0@WebX.sUN8CHnE>... > Pete, > > Check out this solution record (you'll also get it if you search for BSCAN_VIRTEX on support.xilinx.com): > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10703 > > Mike Thanks! That nailed it. I was relying on the BSCAN_SPARTAN2 clock to transition me through bus access states once my command was loaded into DR, but the clock goes away after JTAG leaves the SHIFT-DR state. I'm modifying the logic to use the processor clock for bus access timings. Hopefully, that will work much better. "Shift" also looks a little odd, but I think I can deal with it. - PeteArticle: 42111
We have an application where we desire to remotely program a new FPGA image into a flash ROM then signal the system to reinitialize itself, including reloading the Spartan II. The Spartan II is configuring through slave parallel mode. How do I get the Spartan II to clear its internal memory and reload itself? I've tried just dropping the Program line, but neither Init or Done ever goes low. - Pete Koziar Principle Engineer, VLU-120 Orbital Sciences/TMS (www.orbtrac.com)Article: 42112
Andrew, I would need to know which part to comment. Sometimes the startup sequence at the end of configuration may not behave correctly if there are other older devices in a daisy chain (ie Virtex II with Spartan II) as early bitgen option defaults were not correct for Virtex II and daisy chaining (since been corrected in subsequent service packs). As well, Virtex II ES parts required a bitgen switch set for generating the correct bitfile for the ES material. Often when we encounter one of these 'cycle the power' mysteries, we do not follow it to the end and find out what was really going on: I would advise against that. File a case on the hotline, and follow through. I despise mysteries! Austin Andrew Bridger wrote: > Hi, > Well, I have got my SRL16E working. It does not appear to be any > problem with my VHDL or how the init attribute was being passed to the > tools. (As an aside, from reading previous posts on this newsgroup, > my understanding was that generic was used for simulation, and > attribute was used for the Xilinx tools, However, by looking at the > EDIF netlist after synthesis, and FPGA editor after PAR, the generic > init parameter gets used by the Xilinx tools, not the attribute. > Synthesis with XST. 4.2i) > > It appears the FPGA was not being configured correctly. It took me a > while to figure this out because a fair whack of my design did operate > correctly after configuration, so I had no reason to question the > configuration. I eventually found that programming with JTAG without > cycling the power first created problems. It seems you can't program > twice in a row with JTAG without cycling the power in between. Is > this true or do you think this is indicative of a problem with the > hardware? I searched the Xilinx answers data base, Answer Record # > 10169: and Answer Record # 9013: come close but do not explain the > behaviour observed. > > If I cycle the power before JTAG programming, it works every time. If > not, portions of the design work, and interestingly the SRL16E portion > does not. > > Regards > Andrew > > cablow@yahoo.com (Carlton Blow) wrote in message news:<ae3b23a3.0204151046.482d1b5d@posting.google.com>... > > Hi Andrew, > > > > The problem you are experiencing lies in the transfer of > > generic/attribute information of the primitives from the VHDL code > > over into the Xilinx tools. Essentially, your generic/attribute > > information is being ignored somewhere during your implementation > > flow. Most likely during synthesis (check the resulting EDIF output > > file to confirm). > > > > Your syntax appears correct. However from past experience I have found > > that sometimes the attribute(s) supported by the synthesis tool are > > not always recognized by the Xilinx tools. I have also found that > > direct manipulation of the primitive generic values to values other > > than the default result in implementations that differ from the > > results observed during a functional simulation. > > > > It should also be mentioned that this "problem" you are having is not > > limited to just the SRL16E's. You may also see a similar situation if > > for example, you instantiated LUT based or block based memory > > primitives with initialization values that differ from the default > > (all zeros). > > > > With all that being said, I would propose to you the following: > > > > 1 - Do not manipulate the generic default values of the primitives > > directly. For a functional simulation, manipulate them instead by > > using a configuration statement(s). > > > > Thus the init generic would stay at the default value of "0000", > > however the configuration statement(s) would override this to set it > > at your desired value of "0001" for the functional simulation. > > > > If the problem is with the direct manipulation of the generics, your > > attribute should then pass through the implementation flow and the > > initialization value would then be correctly processed by the Xilinx > > tools. > > > > 2 - If (1) does not work, then also remove the init attribute. > > Instead, add the desired initialization value(s) into the accompanying > > UCF file of your design. > > > > For details on adding the initialization info into the design's UCF > > file, refer to the Xilinx support section of the Xilinx website. There > > is an app-note or other detailing how to perform this function. > > > > Regards, > > > > Carlton > > > > Jonathan Swift <jonathan.swift@xilinx.com> wrote in message news:<3CBADFEF.F81723D5@xilinx.com>... > > > Hi Andrew, > > > > > > Have you checked the contents of the LUT in FPGA Editor to ensure that the > > > INIT value has been applied correctly? > > > You can see the INIT attributes for every component using this. > > > > > > As to your code, everything looks fine and you should be able to > > > initialise the contents of the SRL using this. > > > > > > Hope this helps, > > > > > > Cheers, > > > > > > Jonathan > > >Article: 42113
Does anyone know of a command-line utility for loading the Xilinx
XC9572XL and the Spartan II via JTAG? I would like to set up a batch
file for our medium size production run where the whole process is
automated to the point where the tester plugs in the JTAG port and
hits "Enter."
The operations it needs to do are:
o Load a CPLD
o Load a Spartan II
After that the batch file would run our application to program the
flash chip.
Does such a thing exist or do we need to write it?
I know that Xilinx has a big honkin app in WebPack, but the problem is
that it takes a fair amount of resources and requires too much manual
intervention. What we're looking for could potentially be loaded on a
little embedded PC and run automatically.
As the production run gets bigger, we'll pre-program the flash and
CPLD before installing on the board, but we need something for now.
- Pete Koziar
Principle Engineer, VLU-120
Orbital Sciences/TMS (http://www.orbtrac.com)
Article: 42114Vladislav Vasielnko wrote: Can I connect onl few pins to Vcco and others Vcco pins leave unconnected ? No ! > What a minimum of Vcco , Vcint, GND pins should be connected to chip > on PCB? > All, if you want to build a reliable system. Peter Alfke, Xilinx ApplicationsArticle: 42115
Hi all I am trying to implement a module in VHDL which performs an 8 bit disvison operation. I am looking for an efficient algorithm suitable for hw implementation. Kind Regards knArticle: 42116
Hi Matjaz, I have the workaround for you. Nios 2.0 does not support Win98, but there are steps to make it work. First - install to a directory that is all lowercase. In Nios: 1. make sure that your germs mon has a good vecbase offset. - the end is best. 2. generate. 3. it will fail - it says that it made the sdk, but it didn't. So, you have to make it. 4. so, through the start menu, go to programs>Altera>Excalibur Nios 2.0> Nios SDK Shell navigate to your project dir and type mk_custom_sdk this will make your sdk. 5. when it is done, press generate again on your Nios design. This has solved all the problems we've had on Win98. Also note that Quartus runs MUCH faster on 2000 than on 98. Kerri "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:<3cb69b58$0$227$cc9e4d1f@news.dial.pipex.com>... > "Matjaz Finc" <matjaz.finc@fe.uni-lj.si> wrote in message > news:a961r4$o9$1@planja.arnes.si... > > Hello! > > > > Has anyone experienced any problems with Nios 2.0 (build 224) in Quartus > II > > 2.0? I can't generate it with SOPC builder - it always terminates with an > > error. Even Altera representatives and their official support were of no > > help (!?) until recently - they said it will be fixed in next update. My > OS: > > win98. > > Though I can't help with the specifics, I have found that all of the tools > run far more smoothly under windows 2k. I used to dual-boot, but frankly I > don't bother with win9x now. > > Another tip is to make sure all tools run from paths with no spaces. The > batch command line scripts etc have a habit of sometimes not working with > spaces. (e.g. Leonardo integration etc) > > PaulArticle: 42117
Hello again. I didn't realise that you had posted both messages. I would have replied at the same time. 1. the workaround I gave in the other post should fix this. 2. The reason Tech support thought that it would be fixed (probably) is that the error you were describing is happening on many OS' because of a current working directory problem, which is indeed fixed. But you see it because of Win98, which will not be supported by Nios in the future. In fact I believe that soon Quartus will stop supporting it also. IF others see this and have the error on other OS', here's the reason. You can decide where you are having it change CWD. If you open the Nios/SOPC builder megawizard in Quartus without a project open Quartus may think the CWD is another folder - you get the error. Fix: open the project that the nios design is in then the MW. Problem, open the Nios proj, and the MW then open a file from elsewhere (outside the CWD), get this error. Fix: after opening the file, go back and open ANY file in the real CWD. generate. Hope this helps. Also, look for the next release it is fixed in there. Kerri "Matjaz Finc" <matjaz.finc@fe.uni-lj.si> wrote in message news:<a961r4$o9$1@planja.arnes.si>... > Hello! > > Has anyone experienced any problems with Nios 2.0 (build 224) in Quartus II > 2.0? I can't generate it with SOPC builder - it always terminates with an > error. Even Altera representatives and their official support were of no > help (!?) until recently - they said it will be fixed in next update. My OS: > win98. > > Error excerpt: > -------------------------------------------------------- > # 2002.03.26 16:47:16 (*) Running Generator Program for boot_monitor > > Bad file boot_monitor_contents.srec at > c:/vhdl/excalibur/nios2/bin/format_conversion_utils.pm line 923. > Error: Generator program > for module 'boot_monitor' did NOT run successfully. > --------------------------------------------------------- > > Regards, > > Matjaz FincArticle: 42118
OK. Here is confirmation below. Eric Smith wrote: > Theron Hicks <hicksthe@egr.msu.edu> writes: > > Please enlighten me. In 4.1 the simulation options are > > 1. Simulate Behavioral VHDL Model > > 2. Simulate Post-Translate VHDL Model > > 3. Simulate Post-Map VHDL Model > > 4. Simulate Post-Place & Route VHDL Model > > Can you clarify what each of these really accomplishes? > > > > #1, I assume is simulation of the code as written and assumes delta delays > > I suppose it might also simulate any explicitly specified delays, though > that's obviously a big no-no for synthesis. This is the simulation of your RTL code/Schematic design. ISE will take the source files before synthesis and send those to the simulator. Most instantiated Xilinx primitive (either instantiated by the user in the RTL code or in a schematic) will have a delta delay of 100 ps (prevents possible race conditions in certain situations). The RTL code itself will only have delays if you put it in there and as mentioned by Eric, that is generally not a good idea. > > I am uncertain as to precisely what #2 and #3 do. > > My guess is that at post-translate you have a pure RTL model, but that it > has not been partitioned to the specific primitives of the target FPGA, > since that's the function of mapping. Post-traslate (a.k.a post-ngdbuild) is a structural netlist created from Xilinx SIMPRIM primitives that represents the design after synthesis and after tranformation from EDIF/NGC to the Xilinx database structure howevere before MAPing optimizations/trimming and before place and route. There is no timing associated with this simulation. > After mapping, the logic matches what's available in the FPGAs, but the > routing has not been done, so there's still not a complete delay model. The Post-Map simulation is different from the Post-Translate in two ways. First, the Mapper may have done some optimizations and trimming of the design during that process and therefore may have altered the underlying structure of the design however the functionalitly should remain unchanged unless there was a problem in the netlist (i.e. significant portions of the design left unconnected). The other difference is there is partial-timing associated with this netlist. Since the design is Mapped and all component delays can be determined, an SDF file is written out containing all component delays (i.e. LUT delays, FF delays, RAM delays, etc.) however does not contain the routing delays. > > #4 I assume is the actually delays including routing, etc. > > Sounds right. Post Place and Route simulation contains full timing (routing and component delays). Otherwise, it should look very similar to the Post-MAP simulation. > Perhaps someone at Xilinx can confirm? Another place for confirmation of these types of issues is in the Xilinx Synthesis and Simulation Design Guide: http://support.xilinx.com/support/sw_manuals/xilinx4 The simulation methodology and all of the information I said above should be contained in that guide. -- BrianArticle: 42119
Hi,
My design is somewhat structural at the highest level. I would like
to floorplan the lower level modules and then have that floorplan (and
perhaps even routing) be retained at the higher level. Is that
possible? Is there some hidden trap that I need to be aware of (other
than the potential problem with the blocks not being able to be placed)?
If this is a reasonable and wise idea, how do I do so? My code is VHDL
and my target device is the Spartan2E. I am currently using ISE4.1 but
I have ISE4.2 available. (I just haven't installed it yet, as I would
rather avoid changing software in mid project.)
Thanks,
Theron Hicks
Article: 42120kn, you need to provide more details: Are both operands 8 bit integers? Do you expect an 8-bit integer result and an 8-bit remainder? Are you concerned about speed or more about size (=cost)? Peter Alfke =============================== kn wrote: > Hi all > > I am trying to implement a module in VHDL which performs an 8 bit > disvison operation. > I am looking for an efficient algorithm suitable for hw > implementation. > > Kind Regards > knArticle: 42121
Can you explain me answer or where can I read detailed information about it ? Best regards, Vladislav Vasilenko Peter Alfke wrote: > > Vladislav Vasielnko wrote: > Can I connect onl few pins to Vcco and others Vcco pins leave unconnected ? > > No ! > > > What a minimum of Vcco , Vcint, GND pins should be connected to chip > > on PCB? > > > > All, if you want to build a reliable system. > > Peter Alfke, Xilinx ApplicationsArticle: 42122
Norman Yang wrote: > Thanks! > I wonder if I could add some constriant in verilog source code and affect > its simulation behavior. For Verilog simulation, you can add a defparam to your code/testbench to modify DLL attributes. Using Falk's UCF attribute as a guide, the defparam statement will look something like: // synthesis translate_off defparam my_dll_inst_name.CLKDV_DIVIDE = 8.0; // put other DLL attributes here // synthesis translate_on Since these parameters are ignored for synthesis, you must make sure that the UCF attribute or Verilog attribute for synthesis is consistant in this value or else you risk a simulation-synthesis mis-match for the DLL. Good luck, -- Brian > > > Norman > > -- > Best regards. > Norman > norman@zh.t2-design.com > > Falk Brunner <Falk.Brunner@gmx.de> wrote in message > news:a9bkkd$1k92t$3@ID-84877.news.dfncis.de... > > "Norman Yang" <norman@zh.t2-design.com> schrieb im Newsbeitrag > > news:a98pf7$5b6$1@news.cz.js.cn... > > > Hello everyone: > > > I meet a problem in controlling VertexE DLL property in UCF file. I > don't > > > know how to control the Clock Divide Property of DLL in UCF. XILINX > > > > INST my_dll_inst_name clkdv_divide=8; # divide by 8 > > > > See also Xilinx Constaints guide, chapter C. > > > > -- > > MfG > > Falk > > > > > > > >Article: 42123
Try here: Products : Microprocessor Solution Kevin Hansen wrote: > A few months ago I downloaded some JTAG-programming C source code, from the > Xilinx site, that could be modified for my application. I have misplaced > the files and am looking for them again, but I haven't been able to find > them. Can anyone point me to where they are? > > Thank you, > Kevin HansenArticle: 42124
Is there a copy of Synario v2.3 available either for free or purchased? I start learning about programming the GAL22V10 and someone recommended Synario v2.3.
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