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This is changing. Altera has apparently recognized the value of allowing an
expert user to direct placement to improve performance. This is especially
necessary in the 20K and new Stratix families because the local connections
between LABs make it possible to significantly alter the delay times. In 10K, it
was not nearly as helpful since anything arithmetic had to go on the row routes
anyway. Altera is listening very carefully to expert users, and I think it is
beginning to show in their offerings both in terms of the silicon and the
software.
Kevin Brace wrote:
>
> Altera attitude seems like users don't have to get too much in detail,
> and let the tool handle it, but shouldn't Altera listen to those power
> users?
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 42026
Competition is good. It keeps the vendors honest, keeps the parts affordable
and gets us a better selection of parts to use and better features to play
with. I'm all for it.
Peter Ormsby wrote:
> Both Altera and Xilinx have taken ideas from each other and used them to
> make their own products better. This is good for all the engineers out
> there as they will have better devices today than they had five years ago -
> no matter which vendor's devices they decide to use.
>
> -Pete-
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 42027
You get what you pay for. If you want a fully documented guaranteed bug
free core, I don't think a free core is likely to meet your needs.
If you feel strongly about this, you could always pick up a few of the
cores, test them, post the testbenches and test results, and then document
them, I am quite sure no one would object. Besides, I am sure it would give
you a wonderful learning experience. One learns very quickly when debugging
another persons work, even if that other person is a very poor designer.
Please remember that no one got paid to do the thousands of hours of work
represented by those free cores.
Kevin Brace wrote:
> No, I won't say that the ideal of the Opencores.org is bad, but
> the problem is, the people who work on projects seem to post their work
> there without adequately testing it.
> Perhaps for a small project (I will consider a PCI IP core a small
> project.) they might want to have a policy not to allow code to be
> available until all known bugs are fixed.
> Also, since the design will be open source, the authors will have to
> keep the design easy to understand if someone wants to modify or fix
> bugs themselves, but the authors of Opencores.org PCI IP core didn't
> seem to care about it.
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 42028
If you can find one, the old xchecker cable is serial. I don't
think it is supported by the 4.x software though. Probably the
best solution is to run out to your local computer shop and buy
one of those $15 parallel port boards and plug it into your
system.
Tom Loredo wrote:
> Hi-
>
> I'm experienced with 8-bit microcontrollers, but a complete
> newbie to FPGAs. I'm considering them for an upcoming
> project, and a factor in my choice is availability of
> an affordable evaluation/development board with a *serial*
> interface. So far I've been looking at parts from Xilinx
> and Atmel, but the eval boards I've come across all use
> the parallel port on the PC. I only have a serial or USB
> port, so these are not suitable. Any leads/suggesions
> are appreciated.
>
> Thanks!
> Tom Loredo
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin,
1759
Article: 42029
On Fri, 12 Apr 2002 22:27:15 +0000 (UTC), nweaver@CSUA.Berkeley.EDU (Nicholas
Weaver) wrote:
>OK, call me brain damaged, but searching the Xilinx web site isn't
>helping me yet.
OK, "you are brain damaged" .... Nope, I checked your other postings,
and you are not.
>I want to do some post placement, pre-routing manipulation of the
>design (well, actually, build TOOLS to do...). Is there a way to
>extract/manipulate the .ngd file, including placement information? Or
>is the format published somewhere?
So I did a litle test design, and I was able to change the location of a
CLB post placement, pre routing.
(all from a w2000 batch file)
First:
set des=test
set maptype=XC4013E-4-PQ208
ngdbuild -p %maptype% -u %des%.edn %des%.ngd > %des%.log
map -pr b -p %maptype% -o map.ncd -detail %des%.ngd %des%.pcf >> %des%.log
par -w -pl 5 -r -detail map.ncd %des%.ncd %des%.pcf >> %des%.log
The "-r" disables the routing phase, and you get an .NCD that is placed
but not routed. You can look at it in the FPGA editor.
Then:
xdl -ncd2xdl -nopips test.ncd
creates test.XDL
which I then edited, by changing the location of one of the CLBs.
Then:
xdl -xdl2ncd test.xdl test2.ncd
renamed test.pcf to test2.pcf
par -k -rl 2 test2.ncd test2pr.ncd
The "-k" is for re-entrant routing.
Then checke the resultant .NCD, to see if the moved CLB had survived
the surgery. It had.
I am looking forward to your placement repairer program that will
fixup the stupid data-path placement that the xilinx tools do.
All the best,
Philip Freidin
>ngd2{edif,vhdl,vlg} seems to just produce a simulation netlist,
>annotated with delays. I want something I can go back & forth with.
>
>Thanks.
Philip Freidin
Fliptronics
Article: 42030I've got my bitstream files and wish to load them in slave serial mode. There are application notes but I think they might be a bit out of date. Is this the right recipe ? Take one .bit file Drop the first 68 bytes so it starts with the 32 ones like the .mcs file does. Take each byte, and starting from the MSB clock it in through CCLK/DIN being careful to observe timing constraints. I find that the only way to make /INIT go low (DONE never goes high unfortunately) is by clocking the stuff in for a second time then /INIT drops after a couple hundred (repeatable number) bits. The clocks til /INIT dropping is independant of how many zeros or ones I pad with after the first bitstream. Almost as if the preamble is actually a postamble and the entire stream needs turning back to front. GeorgeArticle: 42031
This is what I want to do. I have a spec and I have some HDL written, now I am going to try to target a spartII device, could some one please point out a set of common tools needed? I am looking for HDL editor, behavior and netlist level simulation tools, timing tools and ways to download everything to my fpga, what tools in webpack ISE and other components do I need to accomplish this goal?Article: 42032
Hello everyone: I meet a problem in controlling VertexE DLL property in UCF file. I don't know how to control the Clock Divide Property of DLL in UCF. XILINX datasheet mentioned about how to control it by symbol. And I also want to know how to control it in HDL code and affect simulation. The default one is always divide by 2. Thanks! -- Best regards. Norman norman@zh.t2-design.comArticle: 42033
Theron Hicks <hicksthe@egr.msu.edu> writes: > Please enlighten me. In 4.1 the simulation options are > 1. Simulate Behavioral VHDL Model > 2. Simulate Post-Translate VHDL Model > 3. Simulate Post-Map VHDL Model > 4. Simulate Post-Place & Route VHDL Model > Can you clarify what each of these really accomplishes? > > #1, I assume is simulation of the code as written and assumes delta delays I suppose it might also simulate any explicitly specified delays, though that's obviously a big no-no for synthesis. > I am uncertain as to precisely what #2 and #3 do. My guess is that at post-translate you have a pure RTL model, but that it has not been partitioned to the specific primitives of the target FPGA, since that's the function of mapping. After mapping, the logic matches what's available in the FPGAs, but the routing has not been done, so there's still not a complete delay model. > #4 I assume is the actually delays including routing, etc. Sounds right. Perhaps someone at Xilinx can confirm?Article: 42034
George Hodges wrote > I've got my bitstream files and wish to load them in slave serial mode. > > There are application notes but I think they might be a bit out of date. > > Is this the right recipe ? > > Take one .bit file > Drop the first 68 bytes so it starts with the 32 ones like the .mcs file > does. Nope. Check the FPGA FAQ site for the bit file format. The header length depends on the date, part type, and so on. The rest of your recipe looks OK.Article: 42035
Start at optimagic.com and fpga-faq.com akhar wrote > Hello, I have been looking around on the net for more information but it > seems quite obscure (not totally but a bit) I am interested in learning more > about FPGA's and how to program them. I have found www.fpgacpu.org to be > quite interesting but no quite clear at least with what I know from the > FPGA's. I wanted to know : > - what is the native language to program an FPGA ( I saw that I can use C > but I have not found the compiler , Can I use another language?(lisp,scheme, > java,Smalltalk)) > - Are there limits to what I can program? (I would like to use them to > program neural networks) > - Is it possible to use OO paradigms? > - what is the best recommended starter kit (altera's or xilinx's) > - how do I know the number of gates I'll need for a project/applicationArticle: 42036
"akhar" <akhar@videotron.ca> writes: > - what is the native language to program an FPGA ( I saw that I can use C > but I have not found the compiler , Can I use another language?(lisp,scheme, > java,Smalltalk)) Well there exist no such thing as an "native" language. What there exist are 4 entirely different approaches to programming and a few languages or tools for each: - high level code: Verilog, VHDL, AHDL, CUPL, Handel-C, ... - high level schematic (drawing): whatever format the tool wants - low level schematic: mainly FPGA Editor (only for Xilinx chips) - low level code: JBits, cnets, PamDC, ... Generally: - Low level means that you select individual FPGA features, comparable with assembly language programming. - High level means you write logic formulas and they are compiled, somewhat like high level programming. - Code means an ASCII source files that are assembled/compiled. - Schematic means some an drawing/CAD style program. As for C: there exists high level (Handel-C) and low level (cnets and PamDC) tools that use C as language. Handel-C tries to actually compile C expressions to FPGAs. cnets and PamDC use C as "driver" language to drive an library of "place this type of function here" calls. As for other languages like Lisp, Scheme, etc: forget them. Even Handel-C is at the limit of what is possible presently. And gets lots of flak for not being up to it yet. > - Are there limits to what I can program? (I would like to use them to > program neural networks) For one: Chip size. Remember the days when computers had 100k to 1M of RAM, and no virtual memory? All them "out of memory" errors. FPGA programming will remind you of that. Get a bigger chip... More importantly though: FPGAs are not sequencial "do this, do that" programming like processors. FPGAs are more "place this function here, place that there" with data traveling from one unit to the next and all units working all the time. So programming is splitting your problem into units and placing them so that data travels fast. So traditional languages are not what you want. You want an "layout descriptor" language. > - Is it possible to use OO paradigms? No. Totally useless. OO is all about managing sequential access to data. An FPGA is about as OO as an layout of machines on an factory floor! Each Unit is one instance of one class of processing (and not just a class for data objects to be instantiated), and data is not in instanciated objects that direct computation, but rather as stream of packets that travel (and need to be directed) to the proper units. So this is nearer to traditional "we know what data to expect" programming. > - what is the best recommended starter kit (altera's or xilinx's) Roughly equal. That is why both firms are roughly same size. Altera seems to win on complexer logic, Xilinx on faster Arithmetic. And whose tools are better, that is an ongoing but low-intensity holy war :-). For your neural networks (many small units with arithmetic and connecting to near neighbors) I would recommend Xilinx. > - how do I know the number of gates I'll need for a project/application Forget gates. They are an near-useless marketing number. Count Logic units (so called LUTs). Basically one LUT can compute any 1-bit function of 4 bits of input. And its associated FF can facultatively store one bit of data (the output bit) before sending it further. See the manufacturesrs data sheet for the range of LUT sizes they make. Usually in the few-100 to few-10000 range. To give an example: Xilinx XC2S200, for $50, is 4700 LUT/FF units. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Make your code truely free: put it into the public domainArticle: 42037
> BTW You have plenty of RAM I take it? You'll need it with both running. > Does anybody know why Quartus II 2.0 needs huge amount of memory? Just opening up the GUI without any project opened takes 80M bytes of RAM on a WinNT PC!!! Unbelievable!Article: 42038
"akhar" <akhar@videotron.ca> writes: > I looked up Handel C and found a lot of article talking about it but no > official web site? is there one or is hcc the only compiler ? Sorry, I never looked into them. Only know their name from what has been discussed here on the group. They are at the top of the "high level code" approach, I am "low level code" style thinker and therefore programmer. I come from an El Eng background , using 74(LS)xx(x) chips. While you seem to be coming from an Comp Sci background used to HLLs. > What sites do > you recommend for learning how to program the FPGA's ? Caveat: sites selected for my own use, so perhaps not good your style. You could visit my computer and electronics links page: http://neil.franklin.ch/Links/comp_electro.html There scroll down to "FPGA CPU", as that was also for me the first FPGA oriented site I found. From there on there are quite a few links to (and into) various FPGA sites. The file is find-time ordered, so don't imply anything else from ordering. Most important (for me, low level code style) were the vendors data sheets. All the important ones have direct links in each vendors section, all fairly short after FPGA CPU. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer - Make your code truely free: put it into the public domainArticle: 42039
Thanks for the pointers, I looked up Handel C and found a lot of article talking about it but no official web site? is there one or is hcc the only compiler ? What sites do you recommend for learning how to program the FPGA's ? best regards Stephane "Neil Franklin" <neil@franklin.ch.remove> wrote in message news:6ud6x3zrla.fsf@chonsp.franklin.ch... > "akhar" <akhar@videotron.ca> writes: > > > - what is the native language to program an FPGA ( I saw that I can use C > > but I have not found the compiler , Can I use another language?(lisp,scheme, > > java,Smalltalk)) > > Well there exist no such thing as an "native" language. What there > exist are 4 entirely different approaches to programming and a few > languages or tools for each: > > - high level code: Verilog, VHDL, AHDL, CUPL, Handel-C, ... > - high level schematic (drawing): whatever format the tool wants > - low level schematic: mainly FPGA Editor (only for Xilinx chips) > - low level code: JBits, cnets, PamDC, ... > > Generally: > > - Low level means that you select individual FPGA features, comparable > with assembly language programming. > - High level means you write logic formulas and they are compiled, > somewhat like high level programming. > - Code means an ASCII source files that are assembled/compiled. > - Schematic means some an drawing/CAD style program. > > > As for C: there exists high level (Handel-C) and low level (cnets and > PamDC) tools that use C as language. Handel-C tries to actually compile > C expressions to FPGAs. cnets and PamDC use C as "driver" language to > drive an library of "place this type of function here" calls. > > As for other languages like Lisp, Scheme, etc: forget them. Even > Handel-C is at the limit of what is possible presently. And gets lots > of flak for not being up to it yet. > > > > - Are there limits to what I can program? (I would like to use them to > > program neural networks) > > For one: Chip size. Remember the days when computers had 100k to 1M > of RAM, and no virtual memory? All them "out of memory" errors. FPGA > programming will remind you of that. Get a bigger chip... > > More importantly though: FPGAs are not sequencial "do this, do that" > programming like processors. FPGAs are more "place this function here, > place that there" with data traveling from one unit to the next and > all units working all the time. So programming is splitting your > problem into units and placing them so that data travels fast. > > So traditional languages are not what you want. You want an "layout > descriptor" language. > > > > - Is it possible to use OO paradigms? > > No. Totally useless. > > OO is all about managing sequential access to data. An FPGA is about > as OO as an layout of machines on an factory floor! Each Unit is one > instance of one class of processing (and not just a class for data > objects to be instantiated), and data is not in instanciated objects > that direct computation, but rather as stream of packets that travel > (and need to be directed) to the proper units. > > So this is nearer to traditional "we know what data to expect" > programming. > > > > - what is the best recommended starter kit (altera's or xilinx's) > > Roughly equal. That is why both firms are roughly same size. Altera > seems to win on complexer logic, Xilinx on faster Arithmetic. And whose > tools are better, that is an ongoing but low-intensity holy war :-). > > For your neural networks (many small units with arithmetic and > connecting to near neighbors) I would recommend Xilinx. > > > > - how do I know the number of gates I'll need for a project/application > > Forget gates. They are an near-useless marketing number. > > Count Logic units (so called LUTs). Basically one LUT can compute any > 1-bit function of 4 bits of input. And its associated FF can facultatively > store one bit of data (the output bit) before sending it further. > > See the manufacturesrs data sheet for the range of LUT sizes they > make. Usually in the few-100 to few-10000 range. > > To give an example: Xilinx XC2S200, for $50, is 4700 LUT/FF units. > > > -- > Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ > Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer > - Make your code truely free: put it into the public domainArticle: 42040
akhar wrote: > Thanks for the pointers, > I looked up Handel C and found a lot of article talking about it but no > official web site? http://www.celoxica.com/home.htm > is there one or is hcc the only compiler ? Synopsys and Forte have SystemC to Verilog or VHDL compilers. SystemC is a "standard" library of C++ classes. Xilinx has a Java to Verilog compiler that is "freeware" until this summer: http://www.xilinx.com/ise/advanced/forge.htm http://www.synopsys.com/cgi-bin/sld/ltl1.cgi#f2 http://www.forteds.com/products/cynthesizer.html > What sites do > you recommend for learning how to program the FPGA's ? To do what? If you want high speed digital signal processing in the lowest cost possible FPGA, you may need different tools, attitudes and skills than if you want to emulate a ASIC, or emulate obsolete hardware, or communications equipment, or any of the various and sundry uses that FPGAs are put to. Some of the tools are useful for a narrow range of types of designs. For freeware tools, both Xilinx and Altera have fairly nice packages for starting with VHDL or Verilog: http://www.altera.com/products/software/sfw-quarwebmain.html http://www.xilinx.com/webpack/index.html > - Are there limits to what I can program? Of course. Large FPGAs have ten's of thousands of slices and hundreds of pins, and these limit the computation than can be done in a clock cycle and the amount of data than be input or output in a clock cycle. >(I would like to use them to program neural networks) Are you more interesting in learning about FPGAs, in learning about neural networks or is there an application of neural networks you are interested in? Also, is this learning or for a real product? If you are mostly interested in an application of neural nets, you have a need to speed it up relative to a software implementation, but don't need a fully optimized design, you might want to look at one of the HLL(HandelC, SystemC, Java). If you want to learn lots about FPGAs, you might want to start with a much lower level of abstraction (schematic or VHDL physical netlist) and learn about primitives, placement and other basics of FPGA design. > - what is the best recommended starter kit (altera's or xilinx's) I'd say Xilinx is somewhat ahead in general, this week. Altera is competitive, and has some advantages. > - how do I know the number of gates I'll need for a project/application Don't look at gate counts. The devices don't have "gates". The devices have small 4 input "Look Up Tables" LUTS, carry chains, multipliers and other special purpose logic, and larger memories, and some of these can be used for other purposes. The published gate counts make the assumption that you can use some large fraction of all of these: and real designs don't. I do estimation by trying to identify the resource that will be most used, and plan for the part that has enough of that resource. It's not easy. Usually, however, the design will be limited by internal memory or by LUTs. In Xilinx speak, one slice = 1 LUT + 1 flipflop (single bit storage). -- Phil HaysArticle: 42041
Take a look at http://www.synplicity.com/literature/index.html#certify You can now easily map a large ASIC design onto an off the shelf board (fixed routing) with multiple FPGAs. We have a web page with links to suppliers (and would like more). You may well need more capacity than you think. 1) The effective capacity of an FPGA depends on the type of logic you are implementing. 2) You will probably want to add a bunch of instrumentation logic to your design and you need extra capacity for that. Ken McElvain, CTO Synplicity, Inc. Gil Herbeck wrote: > I need to prototype an ASIC design and am looking for > advice on type of FPGA and on FPGA board as well. > > The board needs to have an ARM9, external memory, an > interface to a PC (serial is ok), the FPGA (or ASIC), > and a header to plug in a daughter card with some pins > routed to the FPGA. > > The ASIC will have between 100K and 500K ASIC Logic > Gates. It will run at about 150 MHz. It needs about > 200 KB of internal RAM. And it will have a lot of > multipliers. There will probably be some pipelining > in the ASIC to meet speed - and probably deeper pipes > in the FPGA. We want to match the FPGA to the ASIC > as closely as possible. > > I think the key factors in FPGA selection are: > - Capacity. We want to fit in one FPGA. > - Performance. We want to run at speed. > - "ASIC-like" synthesis library (see below)? > - Availability of board described above. > > "ASIC-like" synthesis library... The datapath > content on the ASIC may force us to use one of the > datapath synthesis tools. These tools don't support > FPGA architectures directly. I've heard that since > the Actel architecture is "fine-grain" that it works > best for these types of designs. > > Any advice will be much appreciated. > > Thanks, > Gil >Article: 42042
On Sat, 13 Apr 2002 07:40:08 +0100, George Hodges <nospam@here.please> wrote:
>I've got my bitstream files and wish to load them in slave serial mode.
>
>There are application notes but I think they might be a bit out of date.
App note 138 in particular should be read. It is up to date, as far as I
know.
http://www.xilinx.com/xapp/xapp138.pdf
>Is this the right recipe ?
>
>Take one .bit file
Good start
>Drop the first 68 bytes so it starts with the 32 ones like the .mcs file
>does.
Various things affect the number of bytes to be skipped. See
http://www.fpga-faq.com/FAQ_Pages/0026_Tell_me_about_bit_files.htm
for details.
>Take each byte, and starting from the MSB clock it in through CCLK/DIN
>being careful to observe timing constraints.
Right. MSB first.
>I find that the only way to make /INIT go low (DONE never goes high
This is NOT what you want! /INIT starts off low, indicating that the
FPGA is clearing all the config memory (called house-cleaning). It
then goes high for the duration of the configuration process. If it
goes low during configuration, this is an indication of an error.
>unfortunately) is by clocking the stuff in for a second time then /INIT
>drops after a couple hundred (repeatable number) bits.
Which is an indication of an error.
>The clocks till
>/INIT dropping is independant of how many zeros or ones I pad with after
>the first bitstream. Almost as if the preamble is actually a postamble
>and the entire stream needs turning back to front.
No. I can't tell what is going wrong with your config, but it isn't the
reversing the bitstream! . Since DONE didn't go high, and /INIT didn't
go low, then I would suggest re-checking that you are shifting in the
correct bits. Another common problem is the quality of the CCLK that
you are supplying. People often don't give it enough attention because
it is not particularly fast. Even so, the signal integrity is very
important, and you should check that the rising and falling edges are
clean, fast, and monotonic. You need a fast scope (>300MHz) for this.
>George
Good luck,
Philip Freidin
Philip Freidin
Fliptronics
Article: 42043Ray Andraka wrote: > Even if you write your own you run into the attributes and generics > issue. . . . This presumes that making use of some device-specific nuance is required. This do-it-yourself synthesis is certainly required for many designs. For others, the lowest common synthesizable subset for brand A and X is good enough. -- Mike TreselerArticle: 42044
ISE WebPACK got all the tools you are asking for, so go ahead and download the whole version from Xilinx. (About 160MB total download. Takes about 14 hours if you are using a 56K modem to download it.) Don't forget to download ModelSim XE-Starter at the same time. Several Xilinx distributors like Insight Electronics or Avnet sell low cost Spartan-II-based prototype boards, so you should be able to use those to test your design. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) crackeur wrote: > > This is what I want to do. I have a spec and I have some HDL written, > now I am going to try to target a spartII device, could some one please > point out a set of common tools needed? I am looking for HDL editor, > behavior and netlist level simulation tools, timing tools and ways to > download everything to my fpga, what tools in webpack ISE and other > components do I need to accomplish this goal?Article: 42045
Ray Andraka wrote:
>
> You get what you pay for. If you want a fully documented guaranteed bug
> free core, I don't think a free core is likely to meet your needs.
> If you feel strongly about this, you could always pick up a few of the
> cores, test them, post the testbenches and test results, and then document
> them, I am quite sure no one would object. Besides, I am sure it would give
> you a wonderful learning experience. One learns very quickly when debugging
> another persons work, even if that other person is a very poor designer.
> Please remember that no one got paid to do the thousands of hours of work
> represented by those free cores.
>
Ray, is this reply intended for me or the original poster?
I agree that most of the time, free IP cores are pretty much "you get
what you pay for," but if Opencores.org is a little more strict about
the quality of the work getting uploaded, I think some of them will be
useful even in commercial designs.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 42046
Martin Thompson wrote:
> Without wishing to ignite anything - the Altera LPMs use the generics
> for simulation, which Synplify passes through the EDIF netlist on the
> blackboxes and then the P&R tool deals with it from there. Any chance
> of Xilinx imitating this?
The best thing about the Altera LPMs is that they are open source.
If you ignore the schematic string interface, you get a
synthesizable template for useful hardware blocks that work
for both brands A and X through the EDIF netlist.
Of course the coverage for brand A is better, since
they wrote it.
-- Mike Treseler
Article: 42047
akhar wrote:
>
> Hello, I have been looking around on the net for more information but it
> seems quite obscure (not totally but a bit) I am interested in learning more
> about FPGA's and how to program them. I have found www.fpgacpu.org to be
> quite interesting but no quite clear at least with what I know from the
> FPGA's. I wanted to know :
> - what is the native language to program an FPGA ( I saw that I can use C
> but I have not found the compiler , Can I use another language?(lisp,scheme,
> java,Smalltalk))
I personally won't like to use the phrase "programming an FPGA."
Although SRAM-based FPGAs have virtually unlimited programmability, I
will rather call it, "Developing a circuit for an FPGA."
If you want to seriously learn how to design circuits in which
FPGAs can handle, learn Verilog or VHDL.
I personally will recommend learning Verilog, and play around with a
sample design that comes with free tools I will mention later.
Besides http://www.fpgacpu.org, you can download free IP cores
from Opencores.org (http://www.opencores.org), but be aware that the
quality of the IP cores there isn't that great.
> - Are there limits to what I can program? (I would like to use them to
> program neural networks)
Depends on the capacity of the FPGA.
For FPGAs that cost less than $30, the gate density of FPGAs are still
pretty small.
For only that much of money, all you will likely get will be roughly
about 50,000 ASIC (custom chip) gates.
> - Is it possible to use OO paradigms?
Although there might be attempts to bring such concepts into the
FPGA world, I don't think it has worked too well, so you should forget
about it.
> - what is the best recommended starter kit (altera's or xilinx's)
Well, I will become a partisan here.
If you a newbie of designing circuits for an FPGA, I recommend
downloading freely available design tools from various FPGA vendors.
However, the tools from Xilinx and Altera are the ones that are useful
in practice.
I will personally recommend using Xilinx's free tools because Altera
doesn't give you a free version of ModelSim (Yes, because it is free,
the version distributed by Xilinx is somewhat crippled, but it still
works at a reasonable speed as long as the design is not too big.), and
there aren't too many vendors selling low cost Altera FPGA-based
prototype boards.
From my own experience, Xilinx's free tools seem to run more stable,
faster, and requires less hardware resource than Altera's free tools.
For low cost Xilinx FPGA-based prototype boards, check out Insight
Electronics (http://www.insight-electronics.com) or Avnet
(http://www.avnet.com) website.
You can get one below $200.
> - how do I know the number of gates I'll need for a project/application
>
> That's most of it I think
>
> Best Regards
>
> Stephane
Design whatever you want to, and target the biggest chip that's
available.
Hopefully it will fit.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 42048Phil Hays wrote: > <snip, lots of good stuff> > It's not easy. Usually, however, the design will be limited > by internal memory or by LUTs. In Xilinx speak, one slice = 1 LUT + 1 > flipflop (single bit storage). By definition, a slice is TWO LUTs and two flip-flops. But let'snot argue about the arcane reasons for this definition... Peter Alfke, Xilinx ApplicationsArticle: 42049
Hi, I'm working on a design in a Virtex2 that uses both gated and ungated clk's i.e. a clk is distributed to modules in the design and some of them internally gate the clk to some of the logic. Can I just do the gating with a bufgce and run logic of both system clk and some of a gated version of that clk, or will there be so much skew between the two clks it's unsafe? Or, will I have to change the code to run all clk's through a bufgce to have them aligned? thanks, -Lasse -- Lasse Langwadt Christensen, -- Aalborg, Denmark
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