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I am impelmenting dsp algorithms in fpga. i am new to the field. this is my first project. i don't know what would be the gate count of the design before coding in vhdl for synthesis can i come to know what would be the approximate gate count of the design? if so when can get to know that? also how to proceed in that direction as to know the gate count? when can i get the gate count in the flow to the best? thank u prasad.Article: 41851
Falk Brunner wrote: > > "Alexander Miks" <monstrum@tiscali.se> schrieb im Newsbeitrag > news:nDpr8.1110$m4.20430@news010.worldonline.se... > > I've built a small prototypeboard for experimenting with this Altera PLD. > > Basically, all pins are routed to some expansions connectors. But I really > > don't know what happened, because first I managed to download a simple > > design into the chip. It was just an input connected through a T-flipflop > to > > an outout. Then I hooked up a led to the output (through a 1k resistor), > and > > had a 1kHz clock connected to the input. Everything worked, wow I though. > > But then I touched the chip and noticed it was very hot. The led still > > toggled as it was supposed to, but the programmer got no contact. I've > > dubble-checked all connections and there are no shorts or missroutings. > I've > > heard of the so called latch-up effect on the inputs when they're not > > connected but can that really have made the chip get hot and crack? > > Hmm, probably, probably not. The are some things to consider. > First, the chip is a CPLD right? The classic CPLDs consume a lot of stand-by > current, so even if there is nothing going on inside, the get reasonable > hot. > Second, the Altera design enviroment drives all unused outputs to LOW, not > TRISTATE. This is at least true for the Flex10K series, I dont know about > the CPLDs. Falk, from memory Maxplus 2 connects unused pins to undefined internal nets so you can't be sure what they're doing. Nial.Article: 41852
Hello,
I'd like to know how to obtain an executable file from the HandelC's example
"addone.c".
I've read everything I've found but It doesn't work.
We would like to produce the same results (executables) that comes from
Celoxica (addone.exe, video.exe dma.exe ...).
What are the exactly the steps we must to follow?
Our System especifications:
We have gcc 2.95.3-5 installed. We don't want Visual C to do this.
Windows 2000 Proffesional
DK1.1
Thank you.
--
Antonio Martínez Álvarez
Article: 41853RAcoops (racoops@aol.com) wrote: : I am looking for feedback on people's expriences using either Xilinx or : third-party FPGA evaluation/test platforms as part of or in conjunction with : their development processes. : For example, did the use of the platform save : development time/money over not using them? What are people's thoughts & : experiences of using such platforms - do they have significant advantages over : just simulating the design? I'd appreciate any and all responses. Thanks in : advance! I can't speak for other people, but I find it incredably usefull to be able to drop a design, or part thereof, into real hardware and play with it as a means of testing and debuging. For example, one project I did is essentially a programmable waveform generator, continuously addressing a large number of DACs over a common bus, and it was drastically easier to wire a card up, drop the bitstream in and play with a scope to look for glitches etc. in the waveforms and follow these back to design flaws (oops, my bad etc.) than it is to use the simulators (Having all the data muxd over one bus made interpreting sim results a bit of a headache...) There's a big real time advantage as well... ;-) When integrating with custom hardware I think the early use of a prototype board has made my life significantly easier. I have yet to simulate a complete design - each block gets tested thouroughly and the interface between blocks is manually checked and synchronous. Dunno if this is good or bad design practice, but it's working... If you are planning to use an FPGA prototype board, where possible get one with more pins than you need, as the importance of status LEDs can never be underestimated, and you can also route signals out of the design for inspection with a PC / scope / logic analyser. Also, Xilinx's Chipscope looks nice, it uses some logic fabric of the FPGA and blockrams to implement a logic analyser inside the fpga... Cheers, Chris SaunterArticle: 41854
Hi,
I have problems when I want to do a post-synthesis pre-place and
route simulation in Modelsim. I have synthetized a VHDL design in a
apex20ke (an FPGA family of Altera), and I have obtained another VHDL
design which is an FPGA-independent netlist ready for place and
route.This post-synthesis design exported from the synthesis tool give
me errors when I simulate it. Should I compile another library in my
work directory,first?Where could I find the entity´s architectures,
wich are instantiated in this vhdl design?
Thanks, a lot.
Itsaso Zuazua
Article: 41855Hi, if someone who has the above FPGA development system would email me off list, Im having a few problems and would be be greatly obliged to whoever could give me a few pointers. THanks, VincentArticle: 41856
Hi Frank, Check out www.silirec.com Silicon Recognition make a ZISC76 chip and a few development boards. ZISC stands for Zero Instruction Set Computer and is a play on RISC and CISC I guess. Pretty funny!. "It implements an RBF-like Neural Network" and a lot of its applications involve pattern recognition. It will do pattern matching, I'm not sure about pattern generation. I have been playing around with their Wizard board recently (only has FPGA + 2 ZISC76 + 4Mbit(?) RAM), no processor, so if you are interested I can give more info. What is your applicaton? Regards Andrew Frank de Groot wrote in message ... >Hi guru's, > >I need an off-the-shelf PCI PC addin card that I can use to do some >specialized coprocessing. >BUT that board should not be move expensive than 500$. >Am I unrealistic? If not, could you give me a link, a brand name, a type >number? >Just the simplest FPGA and a processor, like a transputer or an ARM will do, >better would be an 80x86 processor. > >Any other solutions? I need to do pattern matching and quite complex pattern >generation. >I might be able to do that without a CPU on the FPGA board maybe? >Is there another solution (like SPLD, CPLD, CSOS, TTL array) that may be >sufficient and would be cheaper? Should I opt for a CPU-only board instead? >Any websites that have specs & prices of coprocessor boards, FPGA boards? > >Thanks very much for your help. > >Frank de Groot >Oslo, Norway > >Article: 41857
"Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:a8tpjg$5a0$1@newsreader.mailgate.org... > > > "Theron Hicks (Terry)" wrote: > > > > > > I agree whole heartedly. I would never count on a design until I had done a Post > > P&R simulation. On the otherhand, I would never waste time with a post P&R > > simulation until I had the other levels of simulation working correctly. > > > I am glad I am not the only one who advocates doing a Post P&R > simulation to make sure the synthesis tool synthesized the design > correctly. > And yes, I don't do it that often because it seems to run about 1/50 to > 1/100 of the speed of an RTL simulation. I just assumed that everyone did a post P & R simulation before commiting a design. I typically do so with a higher clock frequency than I will actually use to verify how much design headroom exists. Theron > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 41858
Hi; I did somthing like this a couple of years ago for a switcher transformer tester. As I remember I had 2 clocks 1 high freq to set the duration of the pulse Then I had a counter that would stay high for variable lengths of time (the width part) this was set high by the lower freq clock (the one that set the rate) so basically you had a counter that got turned on st the start of each PWM cycle then would count till it matched the "width" time then reset. Enabled and synched to the low freq clock. Hope this helps.Sorry I can't remember where I put the code. Mine was fairly simple. Cheers; C.W. Thomas > > Patrick Robin wrote: > > > > > > Jim Granville wrote: > > > > > <snip> > > > > That's correct for freq, but to apply a PWM compare to an accumulator > > > > based > > > > Freq generator is where I cannot see stable PWM out values. > > > > Do you actually have this working in SW ? > > > > > > Yes and cycle-cycle variation in on time-off time doesn't exceed the step size: 2% for > > > 1MHZ frequency and 50MHZ sample rate > > > > > <paste> > > > > I think you can get an 'energy average' by applying any compare value to > > > > the accumulator, > > > > but because the compare is fixed, and the accum adds by varying amounts > > > > then cycle-cycle > > > > errors can be very large. > > > > The 'mental example' I was using, was for a high % of Clock rate ( > > large Adder ), > > which is not correct for this example. > > At a 50:1 ratio, you are correct, the short term jitter in PWM Slice > > level is 2% > > The frequency precison is better then this. > > > > <snip > > > > If you mean Sine Wave out, then Direct Digital Synthesis can do that, > > > > with a Sine > > > > ROM. Look for Direct Digital Synthesis devices from Analog Devices etc > > > > > > It needs to produce a square wave only. I initially tried to find a DDS chip with a > > > programmable wave table but couldn't find any. I believe that would work in my case > > > since I could just load the square wave with needed duty cycle in the table and if the > > > sample rate was fast enough, it would come out with correct precision. > > > > > > But I couldn't find one so I decided to use the same principle but without the wave > > > table since in a square wave the only information we are storing is a single transition > > > point from on to off and that can be figured out by comparing the table pointer derived > > > from the accumulator to a number: > > > > > > if (accumulator > transition point ) put out 0 > > > else put out 1 > > > > > > The rest of the algorithm is identical to DDS as far as I can tell. ie, the frequency is > > > defined by how fast the accumulator passes FFFFFFFF and overflows and a new cycle > > > starts. > > > > > > Your method is new to me and I will have to look more into it if it allows greater > > > precision in the same PLD chip. > > > > There are two precisions, Frequency and PWM. > > If you tolerate 2% on PWM, then you do not need a 32 bit Latch/compare, > > and this can work off only the MSB's of the Adder. > > Even a single 8 bits MSB compare / 8 bit latch will define PWM to 0.4%, > > and have STJ 2% at 50:1, improveing to the define limit above 256:1 > > > > Shortening the adder ( eg 24 bits ) will increase the speed, and reduce > > the > > resource in a PLD. > > > > It's an interesting problem, I will think some more about a 'mixed > > scheme' > > Thanks for your ideas. > > I really don't need 32 bits for the accumulator to get the frequency resolution I need, Last > time I did the calculation I think I needed 27-28 bits for a 50MHZ accumulator. But I have > been mentioning 32 bits since it is a multiple of 8 and most discreet ships are 4 or 8. But I > guess with a PLD it is fully configurable. > > Patrick > > > > > > > -jg >Article: 41859
I am doing a project in Verilog using Lattice ispExpert and Synplify. Being quite new to verilog, I make frequent small syntax errors. It is a real pain to use ispExpert to compile a module only to find it stops with a simple error - moving back and forth between the various windows and waiting for the compile is very time consuming. What I would like to do is a quick check of the verilog syntax, so that I can eliminate most of the errors before running the compiler proper. Using the Synplify gui instead of ispExpert is a bit faster, and there is both a "Syntax check" and "Synthesis check" in the menu. But it would be much better for me if I could simply run these as command-line programs - then I could use them quickly and simply alongside my normal editor. Does anyone know how to do this? Alternatively, are there any simple verilog checking tools available? Thanks. -- David Brown WestControl a.s NorwayArticle: 41860
X-no archive:Yes Thanks for pointing out an interesting alternative. I had a look, and neural networks are not so useful for my app, and the prices are prohibive as well. I could get away with asking 500$ for card + software, but I'd need my own profit too... I am working on a game, played against the computer. To be more specific (but please don't quote this part), it is about implementing a move generator and/or pattern evaluator for the game of G O. My main concern now is the PCI bottleneck, and I whished the PILCHARD, invented in Hong Kong, was available for Windows. The Pilchard is a FPGA board that plugs into a DIMM slot. Frank "Andrew Bridger" <andrew.bridger@xtra.co.nz> wrote in message news:YdAs8.206$iP.27026@news.xtra.co.nz... > What is your applicaton?Article: 41861
Hello FPGA experts, does anybody know a freeware graphic EDIF viewer? Thank you very much, Gunther MayArticle: 41862
Hi; Thanks for reading this. Is there any advantage (I'm thinking ground bounce) to tying unused V2 pins to gnd and setting them as outputs "0"?? I hope to use the DCI function on some of the banks set to 50 OHMs Is there any problem with this. Is there any benefit? Thanks; C.W. ThomasArticle: 41863
Frank de Groot wrote: > > X-no archive:Yes > > Thanks for pointing out an interesting alternative. > I had a look, and neural networks are not so useful for my app, and the > prices are prohibive as well. > I could get away with asking 500$ for card + software, but I'd need my own > profit too... > > I am working on a game, played against the computer. > To be more specific (but please don't quote this part), it is about > implementing a > move generator and/or pattern evaluator for the game of G O. > > My main concern now is the PCI bottleneck, and I whished the PILCHARD, > invented in Hong Kong, was available for Windows. The Pilchard is a FPGA > board that plugs into a DIMM slot. Do you know if this board is commercially available ? It sounds to me that it is still a research prototype. > > Frank > > "Andrew Bridger" <andrew.bridger@xtra.co.nz> wrote in message > news:YdAs8.206$iP.27026@news.xtra.co.nz... > > > What is your applicaton?Article: 41864
Hi there, I think that it is really good to have a power estimation tool like XPower to know how hot the FPGA will get....but that's when the PCB has already been designed. I think that the Excel spread sheet for power estimation is really good to choose a power supply. Has anybody got the an Excel spread sheet for Virtex-II ? Thanks. Philippe.Article: 41865
I hate to keep saying this but it seems people with patents get no respect. If you read my patent http://www.delphion.com/details?pn=US06178494__ You will see that the Pilchard board falls under that patent. I explicitly site Rams of all kinds. Remember the patent issued in 2000 I put it in 11/96 and have all of it in my note book from 12/94. The people from Honk Kong are doing great work but ..... Steve Casselman, CEO Virtual Computer Corporation >invented in Hong Kong, was available for Windows. The Pilchard is a FPGA > board that plugs into a DIMM slot.Article: 41866
Does your design/simulation flow require unique modules? Each instantiation has a unique (hierarchical) name. Is the problem that the synthesis complains about creating a module with that already exists when you try to bring 3 black boxes together? I can see where a poor simulator might get confused by not considering the hierarchy in module definition. What simulator are you using? That might be the right place to ask the question rather than with Synplify. strut911 wrote: > is there any way to uniquify a synplicity netlist? i am trying to do a > bottom-up compile where i compile modules individually and tie them > together at the top level. i am running into problems in simulation > because there are multiple instantiations of the same type of LUT. is > there a way to avoid this?Article: 41867
Thank you very much, Philip. I tried the suggested approach, and modified it
for the ROM16X1 as shown below, and successfully synthesized it using Xilinx
WebPack V4.1 and simulated it using ModelSimXE V5.5b:
--------------------------------------------------------------------------------
library IEEE, unisim;
use IEEE.std_logic_1164.all;
use unisim.vcomponents.all;
entity rom is
port (clk : in std_logic;
addr: in std_logic_vector(3 downto 0);
dout: out std_logic);
end rom;
architecture rom of rom is
-- component declarations --
component ROM16X1
generic(init : bit_vector := x"0000");
port (O : out std_logic;
A0: in std_logic;
A1: in std_logic;
A2: in std_logic;
A3: in std_logic);
end component;
-- constant declarations --
-- signal declarations --
signal tout : std_logic;
-- configuration specifications for declared components --
begin
-- component instantiations --
U1 : ROM16X1
generic map(init => x"5123")
port map (O => tout,
A0 => addr(0),
A1 => addr(1),
A2 => addr(2),
A3 => addr(3));
-- processes --
process(clk) begin
if clk'event and clk = '1' then
dout <= tout;
end if;
end process;
end rom;
-------------------------------------------------------------------------------
It's my understanding that as of ISE4.1i, we can now use generics to initialize
the memory, instead of having to use attributes. So I left out the attribute
statements. I haven't tested this in hardware, so I'm assuming that it
synthesizes correctly. I get no synthesizer errors.
Chip
Article: 41868China and Russia are different worlds... Piracy reigns... Look at it from the bright side. One day, half the world will use your patent, and then you sue them, winning millions in royalties. The guy who invented the IC did that, became a billionaire, remember? Frank "Steve Casselman" <sc.nospam@vcc.com> wrote in message news:_AEs8.1784$2_6.924707050@newssvr14.news.prodigy.com... > I hate to keep saying this but it seems people with patents get no respect. > If you read my patent > http://www.delphion.com/details?pn=US06178494__ You will see that the > Pilchard board falls under that patent. I explicitly site Rams of all kinds. > Remember the patent issued in 2000 I put it in 11/96 and have all of it in > my note book from 12/94. The people from Honk Kong are doing great work but > ..... > > Steve Casselman, CEO > Virtual Computer CorporationArticle: 41869
"Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> schrieb im Newsbeitrag news:a8sr8h$qi2$1@newsreader.mailgate.org... > I recently saw a posting by a guy who made his own Altera MasterBlaster > MV compatible cable having lots of problems. > It probably doesn't cost any more than $10 (maybe less than $5) to make > a Xilinx JTAG cable, but I rather not spend the time and effort on > making one because I have better ways to spend my time. (i.e., > Developing my PCI IP core.) Sure, but this depends on the situation. You said that this PCI thing is just a hobby, not your daily paid work. So low cost is much more important than time. On the other side it would be silly, wasting a engineer sitting down for some hours for assembly/debugging a 60 $ piece of cable. Unless you have a cheap wannabe engineer, aka intern . . .;-) -- MfG FalkArticle: 41870
That's not good. Worst case scenario...say all unused I/Os were set to inputs, could the "latch-up"-effect have caused the chip to draw a tremendous amount of current (0.5A) and brake? ----- Original Message ----- From: "Nial Stewart" <nials@britain.agilent.com> Newsgroups: comp.arch.fpga Sent: Tuesday, April 09, 2002 11:12 AM Subject: Re: How sensitive is the EPM7064? > Falk Brunner wrote: > > > > "Alexander Miks" <monstrum@tiscali.se> schrieb im Newsbeitrag > > news:nDpr8.1110$m4.20430@news010.worldonline.se... > > > I've built a small prototypeboard for experimenting with this Altera PLD. > > > Basically, all pins are routed to some expansions connectors. But I really > > > don't know what happened, because first I managed to download a simple > > > design into the chip. It was just an input connected through a T-flipflop > > to > > > an outout. Then I hooked up a led to the output (through a 1k resistor), > > and > > > had a 1kHz clock connected to the input. Everything worked, wow I though. > > > But then I touched the chip and noticed it was very hot. The led still > > > toggled as it was supposed to, but the programmer got no contact. I've > > > dubble-checked all connections and there are no shorts or missroutings. > > I've > > > heard of the so called latch-up effect on the inputs when they're not > > > connected but can that really have made the chip get hot and crack? > > > > Hmm, probably, probably not. The are some things to consider. > > First, the chip is a CPLD right? The classic CPLDs consume a lot of stand-by > > current, so even if there is nothing going on inside, the get reasonable > > hot. > > Second, the Altera design enviroment drives all unused outputs to LOW, not > > TRISTATE. This is at least true for the Flex10K series, I dont know about > > the CPLDs. > > Falk, from memory Maxplus 2 connects unused pins to undefined internal > nets so you can't be sure what they're doing. > > > Nial.Article: 41871
Hi Steve For we non-lawyers, could you post a few lines on what you reckon your patents cover. The stuff at Delphion is not very engineer-friendly :) "Steve Casselman" <sc.nospam@vcc.com> wrote in message news:_AEs8.1784$2_6.924707050@newssvr14.news.prodigy.com... > I hate to keep saying this but it seems people with patents get no respect. > If you read my patent > http://www.delphion.com/details?pn=US06178494__ You will see that the > Pilchard board falls under that patent. I explicitly site Rams of all kinds.Article: 41872
Check the group archives. The X recommendation (Peter A) is, in summary, to ground the pin either side of a clock input. C.W. THomas wrote > > Thanks for reading this. Is there any advantage (I'm thinking ground > bounce) to tying unused V2 pins to gnd and setting them as outputs "0"?? I > hope to use the DCI function on some of the banks set to 50 OHMs > Is there any problem with this. Is there any benefit?Article: 41873
the problem with synplify is that you need a floating license to run the command-line (batch) mode. if you do not mind the pain of running each program separately, then you should probably use the Tcl shell at the bottom of the synplify gui to run some kind of script that you write and then do all the back-end stuff in the Lattice tools. strut911Article: 41874
First let me say there are two patents that cover a lot of reconfigurable computing. One is from the pilkington guys. I forget the number but Tom Kean knows it. This has most of the prior art. The other is from Mike Butts while he was at Mentor. This has one line (maybe more) about "computing." I don't remember if there are claims to the effect (maybe Mike can let us know) I always thought the people at Mentor would give me a call on that but that is another story. I have 5 patents (two pending). The first one covers the run time generation of bitstreams as well as some double buffered crossbar technology. Some of the claims cover configuration techniques like loading multiple FPGAs in parallel. It is basically the first patent to show how to build a stand alone computer system from FPGs (field programmable gates). There are some continuations of that patent with the same specifications that add additional claims. Then there is the network patent that covers shipping bitstreams over a network and configuring something remotely. The network patent is the first patent that talks about using fpgas to do any kind of computing on the network card. In my opinion it is the first "network processor" patent (someone let me know if I'm wrong about that). The third patent covers any device that could plug into an already existing socket like a processor, ram or dsp. This patent also contains the first (as far as I know) mention of a "hardware operating system (HOS)" By this I mean hardware that does operating system calls. In the patent I reserve the area around the I/Os and separate the user area from the HOS. Anyone who wants a copies let me know I'll send you the 3 main pdfs Steve Casselman "Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:1018373516.26887.0.nnrp-01.9e9832fa@news.demon.co.uk... > Hi Steve > > For we non-lawyers, could you post a few lines on what you reckon your > patents cover. The stuff at Delphion is not very engineer-friendly :) > > > "Steve Casselman" <sc.nospam@vcc.com> wrote in message > news:_AEs8.1784$2_6.924707050@newssvr14.news.prodigy.com... > > I hate to keep saying this but it seems people with patents get no respect. > > If you read my patent > > http://www.delphion.com/details?pn=US06178494__ You will see that the > > Pilchard board falls under that patent. I explicitly site Rams of all kinds. > > >
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