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Matthew, I really don't know enough about Altera devices to be of any help. Obviously, I could have helped you with the use of the Xilinx DLL or DCM... :-) Good luck ! Peter Alfke, Xilinx Applications Matthew Plante wrote: > My system is operating at 62.5 MHz. The clock is skewed just enough so that > the sampled data is incorrect. I've tried using Altera's PLL megafunctions, > but I haven't had any luck getting them to work. Whenever I tried to use > the module, it gives me an error about my I/O assignment, but no useful > information. I'm not quite sure what is wrong with it. The clock input to > the PLL is one of the global clocks, and the output is going to the pll > clock output pin. > > "Peter Alfke" <palfke@earthlink.net> wrote in message > news:3CB0BED1.A579AB53@earthlink.net... > > Matthew, you did not tell us your clock frequency. If it is low enough, I > see > > no problem with your design the way it is. In a synchronous design using > > edge-triggered flip-flops or registers, the data initiated by a certain > clock > > edge must arrive a little before the next clock edge. Anything else is > > irrelevant > > > > Peter Alfke > > =========================== > > Matthew Plante wrote: > > > > > Hello, > > > > > > I'm trying to shift around one of my clocks in my altera 20K200E chip. > I > > > have a clock coming in from a board, going into a global clock on my > fpga. > > > I then send that clock to an output pin where it is used as a clock for > an > > > external pattern generator, which then sends data to my fpga.: > > > > > > Pattern > > > tx fpga clk to generator > > > Generator > > > clk -----> +------------+ ------------------------> +---------- --+ > > > | | data from generator | > > > | > > > | | <------------------------- | > > > | > > > +------------+ > > > +-------------+ > > > > > > So, the returned data from the pattern generator is clocked out with the > tx > > > clock. Well, they are a little out of phase, so I need to either delay > the > > > data, shift the clk to the generator, or set another signal equal to the > tx > > > clk, and then shift that derived clk. Can anyone help me out. I'm > using > > > quartus, and my code is in verilog. > > > > > > thanks, > > > > > > --Matt > > > maplante@iol.unh.edu > >Article: 41776
Kevin, This probably should be an off-line conversation, but since it appears that you want to go public with your personal issues that you seem to have with me, I guess I'll comply... Let's start with this: Kevin Brace <kevinbraceusenet@hotmail.com> wrote in message news:cc7b0b5f.0204021251.687e81d9@posting.google.com... > Peter, I find the things you mentioned somewhat unfair. > In Quartus II 2.0 Web Edition (the free version like the ISE WebPACK), > LogicLock is disabled. (and bunch of other things like Tcl scripting > are also disabled.) > Since the original poster is talking about ISE WebPACK here, I will > say that you shouldn't mention the features available only for the > paid version. The original poster had a problem. He did not specify that he was only interested in "free" solutions, only that he was looking for answers. I offered him one. I'm sorry that you didn't think it was a viable solution, but then again, you weren't the one looking for floorplanning help, so I don't see how you should be judging whether I should have mentioned it or not. > I already did some manual floorplanning in QII 2.0 WE, and some > features like automatically displaying the routing delay on the screen > is nice, but it has its own problems like it lets me assign multiple > FFs to a single LE which shouldn't happen in the first place because > one LE has only one FF. The floorplanner doesn't let you assign anything to a specific LE. Since every LE in a LAB has essentially the same connection to the rest of the FPGA fabric, it doesn't make a lot of sense to assign to that level of detail. If you'll go back and take another look at it, you'll notice that all LE assignements get promoted to a LAB assignment. If you read the messages, it will tell you the same thing. As far as the rest of your tirade (both in this thread and the Queensbury Rules thread), let's make this all clear: I recieve absolutely no financial gain by reading or posting to this newsgroup. There is no one at Altera that told me to, or probably even knows that I post here, unless they've seen the postings here like you. My postings are done on my own time with my own computer equipment and they represent nothing more than my own opinion. As far as my employer goes, there is nothing in my job description or any of my performance review categories that has anything to do with this newsgroup. In summary: I don't get paid anything (directly or indirectly) to post here. However, in interest of full disclosure, I do own some Altera stock (and the stock of another programmable logic vendor too). I am much more familiar with the Altera tools and devices that those from any other vendor. I won't even pretend to know half as much about Xilinx devices/tools or even FPGA design in general as some of the brighter posters in this group do. However, if someone has a problem that I think would be aided by some feature in an Altera device or tool, I'm probably going to post something. This is mostly because there doesn't seem to be an over-abundance of Altera product knowledge here (although lately there sure seem to be a lot of marketing-type cheerleading that I'd appologize for if I was somehow responsible). OK, that's enough here. If you want to take continue this, I would suggest that you send me an email. I would be happy to continue this discussion without adding any more useless postings to this otherwise generally informational newsgroup. -Pete-Article: 41777
Patrick Robin wrote:
>
<snip>
>
> PWM might not be the right term. I am a Software engineer, not a EE, remember ;-)
>
> The application (biological research) does not need extreme precision from wave to
> wave. Correct me if I am wrong but the main problem with my approach is that there
> can be some duration variation from one wave to the next but overall the
> frequency precision is good and with a 32 bit counter I can get fine adjustable
> steps wich is what is needed.
That's correct for freq, but to apply a PWM compare to an accumulator
based
Freq generator is where I cannot see stable PWM out values.
Do you actually have this working in SW ?
> I figure that the wave to wave variation for a 1MHZ
> square wave signal sampled at 50MHZ is 2% and it gets much better bellow 100KHZ
> (.2%)
For a programmable Divide by N, you can define 1MHz in 2% steps, 100KHz
in 0.2%
steps etc.
> Another requirement is adjustable duty cycle between 10-90% but precision is not
> critical at all for this (5-10% is ok). I used the term PWM because the solution I
> initially came up with in software (accumulator/comparator) seems identical to
> circuits for PWM I just learned about when looking for faster hardware solutions.
PWM is correct to use for adjustable duty cycles.
In the example below, Freq precision and PWM precision (step deltas) are
the same.
> The sum of the accumulator is compared against a 32 bit adjustable value to know
> when the pulse should toggled on or off.
I think you can get an 'energy average' by applying any compare value to
the accumulator,
but because the compare is fixed, and the accum adds by varying amounts
then cycle-cycle
errors can be very large.
> Am I right to think that I can then run the output of the CPLD throught a driver
> like 74HCT240 and have a decent function generator? Is 1MHZ too fast for this
> chip?
If you mean Sine Wave out, then Direct Digital Synthesis can do that,
with a Sine
ROM. Look for Direct Digital Synthesis devices from Analog Devices etc
We have done sine ROMs in CPLDs
> If you know of a better way to do this and still keep the circuit simple let me
> know :)
There is a close app we did for a customer, for wide range stepper motor
control.
For this, we used a 'floating point' or 'Exponent/mantissa' LOG
approach.
This allows very wide dynamic ranges in small resource.
This fits in an ATF1504 ( 64 macrocells )
Freq Step granularity in this is 0.8%-0.4%
Set Speed Prog Divider
+--------+ Vc +--------+
QuadIn --------|I | | | |
QuadIn --------|Q U/D | | | |
| | +-1-|MSB |
| 0 | | /128 |
'Mantissa' | | |----7-| to |
| 6 | | /256 |-----> FO_CLK
| | | |-----> FO_DIRN
| 7 | | |
'Exponent' | | |-+ | |-----> FO_Io
| 10 | | +-|>CK |-----> FO_Qo
| | | | | |
+--------+ 4 | +--------+
| |
+------------------------+
| 4:16 -> 1 Select |
|------------------------|
FastCLK -------|> 16 stage Ripple ctr |
25.6MHz | |
Fo < 200KHz +------------------------+
Pulse Width control to also 0.8% steps would be a simple 8 bit
Latch/Compare
against the Prog Divider output.
Both Fout, and the Duty cycle, have zero jitter. ( no cycle-cycle jumps
)
If you application can tolerate some finite, but still small jitter,
then dithering can be used to interpolate finer frequencies.
Look for Rate Multiplier Logic devices for the best filtering of a
dither
value.
eg A 4 bit interpolate would weight over 16 cycles, to give varying
averages
from F+0% to F+0.8% -> 0.05% over > 16 cycle measurement times.
-jg
Article: 41778Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:a8jgu2$ovi$1@newsreader.mailgate.org... > ...snip... > Being called a "troll" by a likely Altera employee isn't nice > either. > > http://groups.google.com/groups?hl=en&selm=6zeh8.12912%24Or3.1429369%40typho on.mn.ipsvc.net > Kevin, Here's one of the places where I found the definition of a usenet "Troll": http://www.dickalba.demon.co.uk/usenet/glossary.htm Most of the posts to this newsgroup are either people with questions or people with answers to those questions. Sometimes the questions are really specific to a design and sometimes they're more like "What do you think of this concept?". Responses usually raise more questions or provide (hopefully) helpful answers. In any case, posts here usually either solicit feedback or provide it. This is good. The post which caused me to feel like you were behaving like a Troll was this: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:a63bum$p8s$1@newsreader.mailgate.org... > I have been using QII 2.0 Web Edition for a few days, and one of > the new features of QII 2.0 is fast fit option which reduces compile > (P&R) time. > > http://www.altera.com/corporate/news_room/releases/products/nr-stx_quartus.h tml > > Didn't kind of feature to reduce the P&R effort level already existed in > Xilinx tools for years? > In Xilinx tools (like ISE WebPACK 4.1 I primarily use), the user can > choose between five P&R effort levels with an optional Extra Effort > level available. > So, what is the big deal about it, Altera? > I guess I am now critical of Altera because of my bad experiences with > QII 2.0 WE + LeonardoSpectrum-Altera 2002 Level 1 NativeLink issue when > FLEX10KE or ACEX1K is the target device. This was not in response to any query about the Fast Fit option, nor is there any serious solicitation for feedback from the rest of the comp.arch.fpga community. It seemed to me that your post was submitted to "stir the pot" and see what sort of trouble you could stir up. In other words, it was a Troll post (unless I'm really missing the boat on the Troll definition). Now, granted, I should probably have provided a pointer to one of the usenet glossary pages to be a bit more clear what I was talking about, but you have to admit that the Troll reference wasn't totally unjustified. -Pete-Article: 41779
Philip Freidin wrote:
>
> >
> > Not a very nice comment.
>
> Oh, come on! I know that other have written personal attacks
> that were uncalled for, but this hardly counts. How much more
> gentle could I have been? The info is available, it's in the
> archive, anyone can see it.
>
When I tried to look up about PCILOGIC within
news:comp.arch.fpga before trying to crack it, I couldn't find it, and
only after I already figured it out using information from a posting at
Opencores.org, I saw that it was discussed at this newsgroup months
before.
The posting you are referring to assumes that the user have access to
FPGA Editor, and it didn't really give instructions on how to
instantiate from an HDL design.
For an ISE WebPACK user, instantiating from an HDL file is pretty much
the only way to use it other than maybe from an ECS schematics tool.
You might argue that instantiating from an HDL design is easy,
and just declare a blackbox, but for most users, including myself two
months ago, it wasn't so obvious.
I believe you have more than 10 years experience dealing with FPGAs, but
not everyone in this newsgroup has such experience, therefore, things
that seem obvious to you might not be so obvious to other less
experienced users.
I hope you understand that.
>
> Well, that doesn't make it a secret. Just an undocumented feature
> of the chip. Others have reverse engineered its functionality and
> published the info in this news group.
>
Again, the posting you are referring to assumes that the user
has access to FPGA Editor.
> >I find it surprising that Eric Crabill of Xilinx who supposedly works
> >with LogiCORE PCI at Xilinx publically admitting the equations inside.
>
> Typical Xilinx person being helpfull.
>
Although he isn't telling me how to use Bitgen's /Gclkdel
option.
> >Isn't that supposed to be a trade secret of Xilinx?
>
> Who supposes? Not much of a trade secret if it has been published.
>
> Since Xilinx tools even output a simulation model for it for
> post P&R simulation, there is no way it could be considered a
> secret. Just poorly (i.e. not at all) documented.
>
I guess I will agree with you that if a simulation model can be
extracted from ngd2ver or ngd2vhd, after all, it is not a top secret,
but Xilinx certainly doesn't make it obvious to most users on how to
obtain the simulation model.
Again, it might be obvious to you, because you are a lot more
experienced than most users, but I don't believe it is obvious to most
users including myself two months ago.
Therefore, I will still call PCILOGIC a secret feature, but you probably
won't agree with that, and neither will I agree with you that it is just
another undisclosed feature.
> > PCILOGIC may not be a huge secret to you, but a question about
> >it seems to come up once every two months or so, and people who answer
> >it keeps saying that it is a secret feature only Xilinx knows.
>
> Who said that ??? Show them too me !!! I'll give them the URL too.
>
I think you are getting too excited. (It seems like that to me.)
Here are a few posters called PCILOGIC a "magic box."
You might think it is obvious, but not too many people seem to know
about it.
http://groups.google.com/groups?hl=en&selm=u95o353k4qrq92%40corp.supernews.com
http://groups.google.com/groups?hl=en&selm=a6tujt%24h4nlk%243%40ID-84877.news.dfncis.de
When providing the URL to the people who didn't know much about
PCILOGIC, I think you should provide the Opencore.org URL I used when I
cracked it, and also tell them that a detailed FAQ answer is coming up
shortly.
http://www.opencores.org/forums/pci/2001/09/00003
> >Yes, if you ask a Xilinx employee about it, they won't tell you at all
> >saying that it is an undisclosed feature.
>
> More likely, they just don't know. Xilinx probably has 2000 people, and
> of them only 6 people (approx) know the details:
>
> The Product Planner
> The I.C. designer
> The I.C. test engineer
> The SW QA engineer
> The SW engineer that created the simulation model
> The engineer in the IP group that created the PCI cores.
>
> If you talk to any of the other 1994 people, they will look at the
> same info you have access to, and wont find an answer. Then they
> might answer "It must be a secret".
>
Someone who posted a question a few weeks ago said he asked
about PCILOGIC to a Xilinx applications engineer, but that person didn't
tell him the details of it.
You might be assuming that it is easy to talk to the person who knows
the details of PCILOGIC, but in a company with several thousands of
employees, I am sure it is virtually impossible to get a hold of the
engineer who knows about it.
Plus, it is a secret (Or you will call it undocumented.) feature, they
have much less incentive telling people about it.
Eric Crabill of Xilinx who knows about PCILOGIC just happened to be a
regular poster of this newsgroup, that's just a coincidence because not
all Xilinx employees post or reply to postings at this newsgroup.
> Just like the secret that you can do higher quality designs with
> schematics and hierarchial floorplanning. And timing based simulation
> is unnecessary if you have done fully synchronous design and have 100%
> coverage of timespecs with static timing analysis.
>
Wouldn't you still do Post P&R simulation to make sure the
synthesis tool correctly synthesized the RTL code?
I have seen a synthesis tool messing up synthesis, causing a crash when
I plugged a Spartan-II PCI card with my PCI IP core in it.
The RTL was fine, but the way I found what was going wrong was through
doing a Post P&R simulation.
Some outputs were going undefined, leading to a crash.
I turned off several optimization options, and everything worked fine.
Ever since that experience, I always do a Post P&R simulation before
burning a Configuration PROM.
>
> >Where should I send all the information?
>
> Go to http://www.fpga-faq.com/FAQ_Root.htm , and at the bottom of the
> page, down load the template of a FAQ page. Then fill in the page the
> way you would like it to be, and email it to philip@fpga-faq.com
> If you need help doing this, let me know.
>
> It will be published for all to see in the FAQ, and will not be a
> secret anymore. You may want to look at some other FAQ pages, to get a
> feel for the current style.
>
> This is also an open invitation to everyone else to write some FAQ
> pages. It is only as good as the sum of the contributions !!
>
> Philip Freidin
>
> Philip Freidin
> Fliptronics
That will be great.
PCILOGIC should no longer be secret to anyone who wants to know about
it.
I started writing the text, and it will take a few more days to finish
it.
When I am done, I will send you a copy of it, but it will be in a
regular text format. (Not HTML.)
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41780> Russell Shaw wrote: > > > > Hi, > > > > What is the recommended spartan-xc2s30 variant that has 5V tolerant > > inputs and 3.3V outputs? > > > > Will this programmer work for it? : > > > > http://toolbox.xilinx.com/docsan/2_1i/data/common/jtg/fig26.htm > > http://toolbox.xilinx.com/docsan/2_1i/data/common/jtg/jtg.htm Kevin Brace wrote: > > All Spartan-IIs are 5V I/O tolerant, and the device supports 5V TTL and > 5V PCI. > In my case, 5V PCI support is the only reason I use it, otherwise I will > use a newer part like Spartan-IIE. > Spartan-IIE is not 5V I/O tolerant unless additional components were > placed outside of the chip. > Yesterday, I burned a Configuration PROM (First time since August of > 2001.), and during the process, I used an Insight Electronics JTAG > cable, which I believe is exactly same as the schematics URL you > presented. > I know it can be hand made, but it was only $60, so I just paid for it. > One more thing to note, you might think XC2S30's LUT density is > same as Altera's EP1K30, but Xilinx inflates gate counts far more than > Altera does. > I know, some people have said that's because Xilinx counts RAM bits as > gates, and I guess I don't like that. > For example, EP1K30's number of LEs is 1,728 which translates to 1,728 > 4-input LUTs and DFFs, but XC2S30's has 216 CLBs which translates to > only 864 4-input LUTs and DFFs (1 CLB has 2 Slices, and 1 Slice has 2 > 4-input LUTs and DFFs.). > So, to get similar number of LUTs and FFs, you should use at least > XC2S50 (384 CLBs = 1536 4-input LUTs and DFFs). > Why not just go ahead and use XC2S100? > That's going to be bigger than EP1K30, although I am not sure how cost > sensitive your application is. > I don't know how you simulate your design, but in my case, the lack of > HDL-based simulator in Altera's free tools and low cost prototype boards > pretty much turns me off using Altera's free tools seriously, although I > do sometimes synthesize my design targeting FLEX10KE to make sure my HDL > code is vendor independent. I use an oscilloscope. Simulation? That's for weenies;) I think an xc2s30 should work, but i'll get an xc2s100 just in case.Article: 41781
Matthew Plante wrote: > > Hello, > > I'm trying to shift around one of my clocks in my altera 20K200E chip. I > have a clock coming in from a board, going into a global clock on my fpga. > I then send that clock to an output pin where it is used as a clock for an > external pattern generator, which then sends data to my fpga.: > > Pattern > tx fpga clk to generator > Generator > clk -----> +------------+ ------------------------> +---------- --+ > | | data from generator | > | > | | <------------------------- | > | > +------------+ > +-------------+ > > So, the returned data from the pattern generator is clocked out with the tx > clock. Well, they are a little out of phase, so I need to either delay the > data, shift the clk to the generator, or set another signal equal to the tx > clk, and then shift that derived clk. Can anyone help me out. I'm using > quartus, and my code is in verilog. Under Projects|Timing settings|Other requirements and options in quartus2, there's settings for Tsu, Th, Tco and Tpd, which i think are used to specify the delay times of signals relative to external pins. Try setting them, then doing a timing-driven fit.Article: 41782
Eric Crabill wrote:
>
> Hi,
>
> Kevin Brace wrote:
> > I find it surprising that Eric Crabill of Xilinx who supposedly works
> > with LogiCORE PCI at Xilinx publically admitting the equations inside.
> > Isn't that supposed to be a trade secret of Xilinx?
>
> I don't supposedly work at Xilinx, I actually work at Xilinx, in the IP
> Solutions Group, developing IP. I am, in a tangential way, associated
> with the PCI and PCI-X cores...
>
Sorry, I didn't word it too well.
What I wanted to say was, "Eric Crabill of Xilinx who supposedly works
with LogiCORE PCI there."
> I wouldn't call it a trade secret. You may find the general invention
> patented and assigned to Xilinx, however.
I will be very interested if such a circuit (After all, PCILOGIC
is just a tiny circuit with a few NAND gates.) can be patented.
Or are you saying that the concept of CE (Clock Enable) was first
patented by Xilinx?
What do you mean when you say "general invention," and which patents are
you referring to?
> The implementation in Virtex,
> Spartan-II, Virtex-E, and Spartan-IIE is the same and intended to assist
> implementation of PCI cores in these devices -- the logic implemented is
> quite literally a tiny part of our core cast into silicon (and, in the
> grand scheme of things, immaterial; the real advantage of this "feature"
> is the dedicated routing associated with it).
>
> This feature is, however, undocumented, unsupported, and not intended
> for
> general use. It is supported in the context of the Xilinx PCI LogiCORE.
> The feature was put in the silicon by the request of the PCI Development
> team, for use by the PCI Development team.
>
> If you use it in your own designs, that is fine. However, if you run
> into
> problems/issues, you are on your own -- the feature is undocumented and
> unsupported.
>
> If you were to file a case with the Support Hotline, they
> probably won't be able to help you directly. Such a case would most
> likely be forwarded to me, and I would write back, "This feature is
> undocumented, unsupported, and not intended for general use. Sorry."
>
I am fine with not supporting it.
I just wish I knew more about how to use NGD2VER, NGD2VHD, and declaring
a blackbox in a design earlier.
>
> I prefer to think of it as a magic box. In fact, the instance name of
> it
> in our core is "MAGICBOX". Maybe that is where the notion came from...
>
Yes, calling it "MAGICBOX" in LogiCORE PCI is probably the
reason why people started to call it a "magic box."
I guess it is indeed a magic box if that solves the timing issues of
long unregistered signal paths (IRDY# and TRDY# paths towards AD[63:0])
in 66MHz PCI.
However, the delay of unregistered paths going through it seems large.
(Tpcilog ~= 1.6ns for IRDY and TRDY in XC2S150-5).
> Anyone who is really interested can determine the logic function using
> the publically available tool set.
Someone else did that.
I appreciate that person.
> Likewise, if you are very curious
> about the GCLKDEL option, you can experimentally determine what it does.
>
> Eric
Okay, here is what I got so far.
When I set the /Gclkdel option to 00000, I got an error that the design
won't function.
In other cases besides 11111 (default value), Bitgen doesn't say
anything.
That makes it pretty hard to figure out what the values mean.
My guess is that smaller the value, greater the delay.
When you say, "you can experimentally determine what it does.," do you
mean like I have to put some kind value, and see if the PCI card will
crash to determine the approximate delay it inserts?
Won't that be fairly risky considering silicon variation of actual parts
being used?
Also, the delay added by using /Gclkdel doesn't get reflected during
static timing analysis.
Why isn't the delay added before static timing analysis?
As an alternative to /Gclkdel, I have come up with an idea of
tying two adjacent GCLKBUF to create some extra global clock buffer
delay.
How does this approach compared to /Gclkdel option, and is it more
desirable than /Gclkdel option?
Tying up two GCLKBUF creates about 1.0ns of extra delay.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41783Noddy wrote: > Can't really tell you how to fix your problem, other than the advice that > you should always finish a design/project to completion using the same > software before upgrading. I'm still using Foundation 3.3 with ISE 4.1 & 4.2 > still in their boxes, and I'm not taking them out till I have finished my > project. > > adrian > Absolutely the right approach but .... Back last November I had to restart a client's design to add support for a specific CPU feature. First I needed to re-sync the code to what we were using on our own board. Did that and then, since the original project was done with 2.1i I tried to rebuild. Downloaded the resulting bit file and ... non-functioning board!! After a, tedious, post P&R sim I found that MAP was ``optimising'' away a sync reset signal and connecting the pin to VCC !! No time for a test case so move to 3.3iSP8, which I was using for our own stuff. Cut to late January. I trying to track down a bug and decide to add 2 extra outputs to a particular state machine ... Blammm! 3.3i PAR now blows up unable to read the resulting PCF constraints file. Still no time to figure out why so move to 4.1iSP3. Currently o.k. but the 4.2i box is sitting next to the machine waiting ...Article: 41784
Rick Filipkiewicz wrote:
>
>
>
> Still no time to figure out why so move to 4.1iSP3. Currently o.k. but the 4.2i
> box is sitting next to the machine waiting ...
I have observed two odd behaviors when using ISE WebPACK
4.2WP0.0.
The first one is XST somehow messes up duplicating IOB FFs when "Pack
registers into IOB" option (I forgot the exact name, but something that
sounds like that.) is On.
XST of ISE WebPACK 4.1WP3.0 didn't have such a problem.
However, if I set the option to Auto, XST correctly duplicates the IOB
FFs.
Duplicating IOB FFs is extremely important to meet Tval < 11ns in
Spartan-II-5 when 5V PCI I/O buffers are used.
The second problem I observed was when I use MAP, I don't like using IOB
input FFs, so I always use "Outputs Only" for Packing IOB FFs.
However, one input FF somehow seems to get packed inside an IOB.
It happened to be a pin connected to PCI's IDSEL pin, and I don't know
why that's the only one that gets packed.
I know I can add a line in a UCF file to disable that (IOB = FALSE), but
it hasn't caused any major design problems, so I haven't added the line
yet.
The above two problems aren't major problems, but . . . I don't like
seeing even minor problems like these.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41785
rjshaw wrote:
>
>
>
> I use an oscilloscope. Simulation? That's for weenies;)
>
From my own experience, I recommend that you take simulation
more seriously.
When I first fired up my PCI IP core in a real computer, it worked
partially, but the rest didn't, and froze the computer.
After that, I did an RTL simulation of it, and found a few bugs that
were causing the computer to freeze.
I reburned a Configuration PROM, and fired it up again, but didn't work.
No, I don't own an oscilloscope, and I am poor, so I cannot afford one.
Although I am sure I would have figured out the problem faster if I had
an oscilloscope.
I had to waste another two weeks to figure out the problem, and did more
RTL simulation, but the board still didn't work properly.
I was getting desperate, so I started looking for application notes that
might be helpful, and in that process I found an application note for
Coolrunner that discussed how to simulate a design using ModelSim XE.
There it discussed how to do a Post P&R simulation of a design, so I
tried it.
When I did it, I saw several output control signals going undefined.
(Instead of 'L' or 'H'.)
The synthesis tool (XST) was somehow messing up the synthesis, so I
turned off bunch of synthesis options, and when I did a Post P&R
simulation again, the output control signals were valid.
Later I learned that the synthesis option that caused the problem was
"Complex Clock Enable Extraction."
The version of ISE WebPACK I used here was 3.3WP8.0, although since then
I haven't had any problems with this synthesis option. (Currently using
4.2WP0.0.)
Ever since this bad experience that cost me more than two weeks, I
always do a Post P&R simulation before burning a Configuration PROM.
However, a Post P&R simulation takes a lot of time, especially
with ModelSim XE-Starter, so most of the time I do an RTL simulation,
and I believe most design flaws can be found at this stage.
You can easily see what's going inside the design during an RTL
simulation, but you have a very limited visibility of what's going
inside the chip if you are using an oscilloscope to debug your design.
> I think an xc2s30 should work, but i'll get an xc2s100 just in case.
Yeah, Spartan-IIs are so cheap, so I think that's a good choice.
However, using a bigger chip will mean you will have to use a bigger
Configuration PROM if you are using one in your design.
People always want to add more stuff, so if you go with a small chip,
you might regret that later.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41786"Peter Alfke" <palfke@earthlink.net> wrote in message news:3CB0F234.82A331E5@earthlink.net... > Matthew, I really don't know enough about Altera devices to be of any help. > Obviously, I could have helped you with the use of the Xilinx DLL or DCM... :-) > > Good luck ! > Peter Alfke, Xilinx Applications > Peter, comments like this really do smack of commercial tastelessness. Matthew, Check through the Apex data sheet or the clocklock/clockboost app note (115 I think). The latter app note is very good at explaining what you can and can't do. There are certain combinations of clocks/PLLs that are OK to use, but certain others are not. e.g. low frequency (<10MHz) aren't available in all configurations eg2 Using a phase shift is only available in certain clock configurations. I guess what you are looking for is to feed in your main clock and then have a second output from the PLL that is phase shifted from the first to compensate for the external signal/buffer delay. If you have the chance maybe you could use external zero delay clock distribution buffers to ease this problem. If not then you could use the Quartus megawizard to generate an appropriate altclklock block. Check that you are feeding the input clock in on clk2p or clk4p and using PLL1 as clk1p and 3p do not have associated PLLs. (Figure 8 on page 15 on app115 will make things clear, I hope). PaulArticle: 41787
Are you using ISE WebPACK or paid version software? You can always try ModelSim XE-Starter 5.5e for free. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.)Article: 41788
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Article: 41789rickman wrote: > Cypress makes several chips that will output a 200 MHz clock using a PLL > based on a clock at any standard low speed. You can use a 10 MHz > crystal and generate several clocks of different frequencies using a > CY22393, for example. The frequency can be programmed in the one time > EPROM and can be changed (in volatile memory) after power up via a two > wire serial interface (I2C). > > I am using two of these on my board to generate several different clocks > from one crystal. > > There's also a nice one from ICS called, I think, the ICS525. http://www.icst.comArticle: 41790
Hi, I know that Modelsim distributed from Altera, hasnīt all the features as the Modelsim from Menthors (which is the complete one). But, which are the differences between them? What canīt I do with Modelsim from Altera that I could do, with the complete Modelsim?Article: 41791
"Itsaso Zuazua" <izuazua@ikerlan.es> wrote in message news:709383e9.0204080115.34e343c6@posting.google.com... > Hi, > > I know that Modelsim distributed from Altera, hasnīt all the features > as the Modelsim from Menthors (which is the complete one). But, which > are the differences between them? What canīt I do with Modelsim from > Altera that I could do, with the complete Modelsim? I believe it does have all features of the entry level Mentor offering EXCEPT speed has been reduced to 1/4 of the full version and probably it is only tailored to Altera libs. A good alternative is ActiveHDL if you were thinking on splashing out on full versions. PaulArticle: 41792
block RAM would be even more messy, In the past i prefer to pull out the signals to primary output and try to make the code easy to comment out these redudant lines... Still feel this method very messy... -- Best Regards, ----------------------------------------------------------------- Xu Qijun Engineer OKI Techno Centre (S) Pte Ltd Tel: 770-7049 Fax: 779-1621 Email: qijun@okigrp.com.sg "freny" <wacky_me@rediffmail.com> wrote in message news:446b88f2.0204062334.17cd5957@posting.google.com... > > I think that chipscope gets inserted at the edif level. Why is it that you > > can't simulate it? Why not hook up the signals you want to look at and run > > them into a block ram? > > hey, > > how do u hook up the signals into the block ram > tell me the actuall processArticle: 41793
Dear All, Thanks for the replies! I think I am leaning towards the paper schematic / HDL entry at the moment, but will certianly follow the pointers. One unexpected thing I found was the 'HDL Heros' cartoon on the Mentor Graphics website - http://www.mentor.com/hdlheroes/ - a nice light hearted break for a mondy morning. I noticed they didn't have a superher to defeat the evil Captain Metastable though... Cheers, Chris SaunterArticle: 41794
Hi Friends, Did any one used Asynchronous FIFO in your design which is genrated using Xilinx's Coregenerator? Here i tried, The behavioural model gives the exact fucntionality as per the data sheet what they give. But the PAR results, time_sim.v along with the .sdf file giving not exactly as the Behavioural model. ie., the functionality seems to be differ. Is it so? Any tried out results...... Best regards, Muthu.Article: 41795
Hi all,
I am using ISE 4.1 and thought to try XST synthesis. While this tool is
working fine with simple designs, It gives an error when i try to use a
tri-state.
The message I get is : ERROR:Xst:742 - Unexpected 'Z' expression found.
ERROR:Xst:746 - Failed to build equation
for signal <....<7>> in unit <....>.
Anyone can tell if there is a way to configure XST to be able to synthesize
tri-states too?
Article: 41796The problem of un-initialised values during functional simulation can easily be avoided. Each time you declare a signal, assign it a default-value. The way to do it is: signal test: std_logic:='0'; signal test_vector: std_logic_vector (upper_value downto 0):=(others=>'0'); This will initialise simulation with known values. As long as your default-values are '0' that's all you need to do. Synthesis will ignore these values and the implementation-tools will put on their own defaults (which are '0'). If your default-value happens to be '1' just assigning this in functional simulation wouldn't help you during implementation as you'd get a different result. In that case you need to set an INIT-attribute on the signals: architecture x of y is signal test: std_logic:='1'; attribute INIT : string; attribute INIT of test: signal is "1"; begin ... BTW: With this initialisation you can do quite a nice clock-signal in your test-bench within one line: architecture x of testbench signal clk: std_logic:='1'; begin clk<= not clk after 5 ns; --voila and you have a nice 50% 100 MHz-Clock. Hope that helps, Martin BTWArticle: 41797
Hi all, Is it feasible to generate a variable-phase square wave using the V-II DCM? My limited inspection of the datasheet (p32 of module 2 of 4 v1.9) implies I can only shift the rising edge of the input clock, not the falling one. Am I misreading this, or, if not is there something sneaky I can do? Thanks, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 41798
Martin, You shift the entire waveform with the variable phase shift. The shift is relative to the incoming rising edge on CLKIN. Austin Martin Thompson wrote: > Hi all, > > Is it feasible to generate a variable-phase square wave using the V-II > DCM? My limited inspection of the datasheet (p32 of module 2 of 4 > v1.9) implies I can only shift the rising edge of the input clock, not > the falling one. > > Am I misreading this, or, if not is there something sneaky I can do? > > Thanks, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt, Solihull, UK > http://www.trw.com/conektArticle: 41799
Hi, I like to convert a 8Bit Input Value to a 16Bit Output using the Block-Ram of a Spartan2 as a Look-up-table-ROM. The conversion function should be a logarithm. How can I write a simple VHDL code to initiate this ROM-Table. The code should be simulated with ModelSim and also be implemented using XST. thanks a lot peter
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