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Hi Kevin, > I will be very interested if such a circuit (After all, PCILOGIC > is just a tiny circuit with a few NAND gates.) can be patented. > Or are you saying that the concept of CE (Clock Enable) was first > patented by Xilinx? I am not saying either; I am talking about US6292020, which covers "low skew programmable control routing for a programmable logic device" which is certainly a rather obscure topic, but probably relevant to this discussion. > However, the delay of unregistered paths going through it seems large. > (Tpcilog ~= 1.6ns for IRDY and TRDY in XC2S150-5). I think you are not considering that this number includes both the logic delay (equivalent to a LUT + MUXF5) and the input routing delay on the IRDY# and TRDY# signals. It is respectable... The real advantage is the dedicated routing of the output net. That is what saves time. Regarding the gclkdel option: > When you say, "you can experimentally determine what it does.," do you > mean like I have to put some kind value, and see if the PCI card will > crash to determine the approximate delay it inserts? No, I mean you can make a simple test design to measure the clock to out of a flip flop, place and route it, then generate 31 bitstreams (each of the valid gclkdel options). Take all 31 into the lab, and measure the clock to out. The differences you observe will likely be related to the use of that option. At room temperature, at nominal VCC, on that one device you happen to be measuring. > Also, the delay added by using /Gclkdel doesn't get reflected during > static timing analysis. Why isn't the delay added before static timing > analysis? Probably because this "feature" is not intended for general use (you may re-read my boilerplate about "unsupported, undocumented" but is intended for use with the Xilinx PCI core for 66 MHz designs, and in that context only. > As an alternative to /Gclkdel, I have come up with an idea of > tying two adjacent GCLKBUF to create some extra global clock buffer > delay. How does this approach compared to /Gclkdel option, and is > it more desirable than /Gclkdel option? Tying up two GCLKBUF creates > about 1.0ns of extra delay. Your approach is a valid way to add delay, but have you considered: 1. What it does to the clock to out performance? 2. What it does to the input hold (0 ns) requirements? It may fix your input setup problems, but break something else... EricArticle: 41876
Hi, there are differences, except the price, between the two Altera CPLDs in subject? Thanks. LuigiArticle: 41877
hi john, thanks for the response. the simulator i am using is cadence NC-Verilog 3.3. it is a good simulator, and one of the standard verilog simulators in the asic industry. the problem is that if you compile two modules with the same name within the same design, it will exit with an error. i can understand the safety precautions that this check implements, but in the asic flow, you can uniquify your netlist which would eliminate these problems. Synopsys Design Compiler is conducive to a modular type of design flow, but i find increasingly that synplicity does not work that way. the main reason i would like to create a modular design where i can individually synthesize parts is that i would like to floorplan critical areas, and not have to touch them ever again. this would be an incredible help to me. i would normally sing the praises of synplicity, but i really wish that they could implement something like this. either that or maybe i have not come across a solution or workaround yet. strut911Article: 41878
Hi I am interest in your work, especially in the first one, if it cover dynamic configurable processor that fabric in ASIC? my work is mainly on ASIC, the fpga is only use as the verification platform because my work is still in progress and we are working on the patent process, so I can not expose it now, I am very sorry for that "Steve Casselman" <sc.nospam@vcc.com> wrote in message news:<zbGs8.1810$X17.957886607@newssvr14.news.prodigy.com>... > First let me say there are two patents that cover a lot of reconfigurable > computing. One is from the pilkington guys. I forget the number but Tom Kean > knows it. This has most of the prior art. The other is from Mike Butts while > he was at Mentor. This has one line (maybe more) about "computing." I don't > remember if there are claims to the effect (maybe Mike can let us know) I > always thought the people at Mentor would give me a call on that but that is > another story. > > I have 5 patents (two pending). The first one covers the run time generation > of bitstreams as well as some double buffered crossbar technology. Some of > the claims cover configuration techniques like loading multiple FPGAs in > parallel. It is basically the first patent to show how to build a stand > alone computer system from FPGs (field programmable gates). There are some > continuations of that patent with the same specifications that add > additional claims. Then there is the network patent that covers shipping > bitstreams over a network and configuring something remotely. The network > patent is the first patent that talks about using fpgas to do any kind of > computing on the network card. In my opinion it is the first "network > processor" patent (someone let me know if I'm wrong about that). The third > patent covers any device that could plug into an already existing socket > like a processor, ram or dsp. This patent also contains the first (as far as > I know) mention of a "hardware operating system (HOS)" By this I mean > hardware that does operating system calls. In the patent I reserve the area > around the I/Os and separate the user area from the HOS. > > Anyone who wants a copies let me know I'll send you the 3 main pdfs > > Steve Casselman > > > "Tim" <tim@rockylogic.com.nooospam.com> wrote in message > news:1018373516.26887.0.nnrp-01.9e9832fa@news.demon.co.uk... > > Hi Steve > > > > For we non-lawyers, could you post a few lines on what you reckon your > > patents cover. The stuff at Delphion is not very engineer-friendly :) > > > > > > "Steve Casselman" <sc.nospam@vcc.com> wrote in message > > news:_AEs8.1784$2_6.924707050@newssvr14.news.prodigy.com... > > > I hate to keep saying this but it seems people with patents get no > respect. > > > If you read my patent > > > http://www.delphion.com/details?pn=US06178494__ You will see that the > > > Pilchard board falls under that patent. I explicitly site Rams of all > kinds. > > > > > >Article: 41879
Let me know if you want a copy of the patent. I can't send anything that large to hotmail Steve "ssy" <shengyu_shen@hotmail.com> wrote in message news:f4a5f64f.0204091840.638c80c7@posting.google.com... > Hi > > I am interest in your work, especially in the first one, if it cover > dynamic configurable processor that fabric in ASIC? my work is mainly > on ASIC, the fpga is only use as the verification platform > > because my work is still in progress and we are working on the patent > process, so I can not expose it now, I am very sorry for that > > "Steve Casselman" <sc.nospam@vcc.com> wrote in message news:<zbGs8.1810$X17.957886607@newssvr14.news.prodigy.com>... > > First let me say there are two patents that cover a lot of reconfigurable > > computing. One is from the pilkington guys. I forget the number but Tom Kean > > knows it. This has most of the prior art. The other is from Mike Butts while > > he was at Mentor. This has one line (maybe more) about "computing." I don't > > remember if there are claims to the effect (maybe Mike can let us know) I > > always thought the people at Mentor would give me a call on that but that is > > another story. > > > > I have 5 patents (two pending). The first one covers the run time generation > > of bitstreams as well as some double buffered crossbar technology. Some of > > the claims cover configuration techniques like loading multiple FPGAs in > > parallel. It is basically the first patent to show how to build a stand > > alone computer system from FPGs (field programmable gates). There are some > > continuations of that patent with the same specifications that add > > additional claims. Then there is the network patent that covers shipping > > bitstreams over a network and configuring something remotely. The network > > patent is the first patent that talks about using fpgas to do any kind of > > computing on the network card. In my opinion it is the first "network > > processor" patent (someone let me know if I'm wrong about that). The third > > patent covers any device that could plug into an already existing socket > > like a processor, ram or dsp. This patent also contains the first (as far as > > I know) mention of a "hardware operating system (HOS)" By this I mean > > hardware that does operating system calls. In the patent I reserve the area > > around the I/Os and separate the user area from the HOS. > > > > Anyone who wants a copies let me know I'll send you the 3 main pdfs > > > > Steve Casselman > > > > > > "Tim" <tim@rockylogic.com.nooospam.com> wrote in message > > news:1018373516.26887.0.nnrp-01.9e9832fa@news.demon.co.uk... > > > Hi Steve > > > > > > For we non-lawyers, could you post a few lines on what you reckon your > > > patents cover. The stuff at Delphion is not very engineer-friendly :) > > > > > > > > > "Steve Casselman" <sc.nospam@vcc.com> wrote in message > > > news:_AEs8.1784$2_6.924707050@newssvr14.news.prodigy.com... > > > > I hate to keep saying this but it seems people with patents get no > > respect. > > > > If you read my patent > > > > http://www.delphion.com/details?pn=US06178494__ You will see that the > > > > Pilchard board falls under that patent. I explicitly site Rams of all > > kinds. > > > > > > > > >Article: 41880
It seems that your n-channel ( pull-down) output transistor is permanently on. Have you checked the design files? What happens before configuration, when all outputs are supposed to be 3-stated ? If this output is held Low even then, I assume a hardware defect. If it is 3-stated, it looks more like a bitstream error... Peter Alfke =============== qysheng wrote: > Hi: > > we are using virtexe. > there are 4 board. > after several month, 2 board's virexe's several pin is almost shorted with ground, only 20 ohm. > > if we use it as input then all the signal is ground. if we use it as output, there will be signal on it. but compared with other signals it is only 1V for high level. > > and I am sure there is no short on the board. > > Can any one tell me what is the problem? > > Bests > qyshengArticle: 41881
I've been trying to make the counter demo work with Insight's $125 Spartan II demo board, but it fails. All I get is a blank LCD. It should have incrementing numbers. I got the Verilog source for the counter demo here: http://208.129.228.206/solutions/kits/xilinx/spartan-ii.html I created a project in Webpack 4.2, and it compiled OK. In the process called "Generate Programming File", I opened the property box, and selected CCLK as the startup clock. I ran the process, and then went to Generate Prom File, and made the counter.mcs file. Then I went back again, and set the startup to JTAG clock. I ran the process, which made a counter.bit file with the JTAG clock. I didn't make a prom file, because this file is for the Spartan II chip. (I'm sure I selected the clocks correctly, because if I don't the iMPACT program tells me). After that, I clicked on Configure Device. I have the board jumpered for JTAG mode (M1 jmpr on, M0 & M2 off). I clicked on Initialize chain, and it shows a 18V01 and a XCV100. I assign counter.mcs to the 18V01 and counter.bit to the next chip. After I do that, the XCV100 changes to a XC2S100. Now I right-click on the 18V01 and tell it to program. It succeeds. Now I unplug power from the board, and re-jumper it for Master Serial mode, which is M0,M1,M2 jumpers all on. I plug in power, fully expecting the LCD to start incrementing but it doesn't. Nothing happens. Can anyone tell me what I'm doing wrong ? -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 41882
"luigi funes" <fuzzy8888@hotmail.com> writes: > Hi, > there are differences, except the price, between the two > Altera CPLDs in subject? > Thanks. > IIRC the pinout is different, to stop you changing chips on existing designs and saving money. Internally, the metal layers are finer, so the die is smaller (or so I was told). And the price :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 41883
Hello,
Once in a while, I keep checking the synthesis tools available
and the kind of RTL code they support.
I would appreciate if some users could check this trivial code
with the latest versions of their synthesis tools and report
here if they do not get the four expected OR gates.
I have tested Synopsys and Leonardo Spectrum ok, as well as older
tools like Metamor, Synario, etc...
Thx in advance,
Bert.
(do not use the email address provided which is spammed to death :-)
Here comes the Code ...
-- HOTDECOD.VHD
-- -------------------------------------
-- On-Hot Decoder
-- (is your synthesis tool WRONG ?)
-- -------------------------------------
-- (c) 2002 ALSE. http://www.alse-fr.com/english
-- This design must be synthesized as 3 x OR gates (4-inputs)
-- It should use 3 x LC in an Altera Flex or Acex
-- It should use 2 x CLBs in a Xilinx Spartan
-- It should use 3 x gates in an Actel ACT1, etc...
-- Any extra logic is not acceptable.
library IEEE;
use IEEE.std_logic_1164.all;
-- -------------------------------------
Entity HOTDECOD is
-- -------------------------------------
port ( A : in std_logic_vector(0 to 7);
Q : out std_logic_vector(2 downto 0)
);
end;
-- -------------------------------------
Architecture COMB of HOTDECOD is
-- -------------------------------------
begin
process (A)
begin
case A is
when "00000001" => Q <= "111";
when "00000010" => Q <= "110";
when "00000100" => Q <= "101";
when "00001000" => Q <= "100";
when "00010000" => Q <= "011";
when "00100000" => Q <= "010";
when "01000000" => Q <= "001";
when "10000000" => Q <= "000";
when others => Q <= "---"; -- don't care
end case;
end process;
-- Note : the "case" above is auto-full and auto-parallel.
-- Quite obviously, one solution is :
-- Q2 = A0 or A1 or A2 or A3
-- Q1 = A2 or A3 or A6 or A7
-- Q0 = A1 or A3 or A5 or A7
end COMB;
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
Article: 41884Hi then you can send it to following address syshen@nudt.edu.cn "Steve Casselman" <sc.nospam@vcc.com> wrote in message news:<pTNs8.2096$iQ6.1088667894@newssvr14.news.prodigy.com>... > Let me know if you want a copy of the patent. I can't send anything that > large to hotmailArticle: 41885
"strut911" <strut911@hotmail.com> wrote in message news:4379d3e0.0204090957.71812374@posting.google.com... > the problem with synplify is that you need a floating license to run > the command-line (batch) mode. if you do not mind the pain of running > each program separately, then you should probably use the Tcl shell at > the bottom of the synplify gui to run some kind of script that you > write and then do all the back-end stuff in the Lattice tools. > strut911 I'm a makefile junkie - I wouldn't mind running every program seperately (with "make" doing the hard work). I also wouldn't mind too much hacking together a Tcl script to do much the same thing (I have little experiance with tcl, but enough to know that a simple script is simple to write - that's why the language was created in the first place), although I'd prefer to be able to run the script outside of Synplify (i.e., from the command line). But the biggest problem is that I don't know what the commands and their options should be. When using MachXL several years ago, I had the same situation - I had to avoid the gui, since it took about 30% of the cpu time for itself (a bug). But the log files contained all the commands, so it was easy - I only had to use the gui whenever I changed project options. I have been able to get some information from ispDesign expert, but the command lines I can see there only work for the placing and fitting part of the development - the checking and compilation is done with a "synpwrap" program that will not do anything from the command line (as far as I can tell).Article: 41886
"Philippe Robert" <PhilippeR@sundance.com> wrote in message news:<3cb31b60@peer1.news.newnet.co.uk>... > Hi there, > > I think that it is really good to have a power estimation tool like XPower > to know how hot the FPGA will get....but that's when the PCB has already > been designed. I think that the Excel spread sheet for power estimation is > really good to choose a power supply. > Has anybody got the an Excel spread sheet for Virtex-II ? > > Thanks. > Philippe. If you contact Xilinx support they will send you a copy.Article: 41887
Can anyone tell me where I can find sites or material related to partioning of huge designs in to multiple (or single FPGAs) for ASIC prototyping purposes sujathaArticle: 41888
I found a German board with a dedicated PCI chip, very cheap too, about 200 $, but... I have a big problem with the PCI bandwidth. I really need something that WOULD take around 300 Pentium clockcycles, and get that done by the FPGA in 30 Pentium clockcycles, including all bus I/O. So what I need is a few dozen Pentium clockcycles to give the FPGA a task, which is examining a pattern on a small grid, then I need a boolan answer from the FPGA. I need tens of millions of those boolean answers per second, otherwise it is not a viable idea. What I need is a way to interface with the FPGA like I was accessing Pentium cache memory, or I need to have a FPGA + processor board, which I could feed a much more complex task. Sorry it took me such a long time to realize that. I am starting to think that current technology is not ripe for a low-cost FPGA coprocessor in a PC that features I/O like it was normal memory (preferably cache even). When will Intel put a FPGA in its processors? Wouldn't that be the absolute killer app? Frank "Steve Casselman" <sc.nospam@vcc.com> wrote in message news:X0us8.1399$d52.739929240@newssvr14.news.prodigy.com... > Isn't there a free PCI core at opencores.org? > > Steve > > > > Does the "no one project license for LogiCORE PCI" mean that I am notArticle: 41889
Bert, I've seen that test case throw off tools in the past. If you are
really concerned about consistent QOR, I do not recommend coding this
way. For discrete to encoded operations, index based functions provide
consistent results across every tool I have seen. An example would be:
-------------------------------------------------------------------------
---
-- Encode a vector of discrete bits into a binary vector representation,
-- WITHOUT guarding against multiple bits on.
--
-- For a single bit on, the encoded value is the offset from the
-- low index of src of the asserting bit, regardless of src's
-- endianness.
-------------------------------------------------------------------------
---
function fnEncBin
(
src : std_logic_vector
) return std_logic_vector is
variable rslt : std_logic_vector( fnLog2M( src'length ) - 1 downto 0 ) ;
begin
rslt :=3D ( rslt'range =3D> '0' ) ;
for rslt_idx in rslt'range loop
for src_idx in src'length - 1 downto 0 loop
if( ( ( src_idx / ( 2**rslt_idx ) ) MOD 2 ) =3D 1 ) then
rslt( rslt_idx ) :=3D rslt( rslt_idx ) OR src( src_idx + src'low ) ;
end if ;
end loop ;
end loop ;
return( rslt ) ;
end ;
Put in an eight bit vector, get 3) 4 input LUT's independent of the tool.
Article: 41890Sujatha Sriram ha scritto nel messaggio <3CB407AB.5F81951E@yahoo.com>... > Can anyone tell me where I can find sites or material related to >partioning of huge designs in to multiple (or single FPGAs) for ASIC >prototyping purposes > > >sujatha A long time ago, I saw some Altera tool did it. I don't know if Altera continues supporting this tool. LuigiArticle: 41891
Is there an expiry on XST or something. Webpack 4.2WP0.x . What worked perfectly a few weeks ago now says the following which I don't begin to understand. I have upgraded iMPACT. Could that have done damage ? Jon ISE Auto-Make Log File ----------------------- Updating: Synthesize Starting: 'exewrap -mode pipe -tapkeep -command C:/xilinx_webpack/bin/nt/xst.exe -ifn top.xst -ofn top.syr' Starting: 'C:/xilinx_webpack/bin/nt/xst.exe -ifn top.xst -ofn top.syr ' fatal error(0031): A device attached to the system is not functioning. Unable to run the process due to a system error. Done: failed with exit code: 0031. ===Article: 41892
Sweir,
Thanks a lot for your input, but it worries me.
Which tool(s) did you find that had a problem with this ?
I sure know of other ways of coding this, but this description
(hotdecod) is the clearest by far, + easy to understand and adapt :
* what if you have only 6 bits instead of 8 ?
* what if I need to customize the decoding completely ?
What do you think is wrong with this description ?
It sure ends up as a very easy to reduce Karnaugh map...
It is not some weird corner case, it's the kind of code we
use all the time.
When I teach HDLs (i.e. when I don't design :-), I keep
saying that RTL Synthesis tools main job is reducing the
combinational logic, and that they are very good at that.
The old logic reduction algorithms I knew of did converge
in this case (Espresso, Quine McCluskey...).
If some tools are having trouble here, the fix seems easy.
If this trivial table is not reduced correctly, it scares me
for when I write large combinational functions...
Another concern is that it could mean that some tool(s) would
not use the don't cares ('-') to simplify the logic ???
That's definitely scary too...
Bert.
"sweir" <weirsp@yahoo.com> wrote in message
news:7fVs8.203628$Yv2.67472@rwcrnsc54...
> Bert, I've seen that test case throw off tools in the past.
> If you are really concerned about consistent QOR, I do not recommend
> coding this way. For discrete to encoded operations, index based functions
> provide consistent results across every tool I have seen.
> An example would be:
>
> ----------------------------------------------------------------------------
> -- Encode a vector of discrete bits into a binary vector representation,
> -- WITHOUT guarding against multiple bits on.
> --
> -- For a single bit on, the encoded value is the offset from the
> -- low index of src of the asserting bit, regardless of src's
> -- endianness.
> ----------------------------------------------------------------------------
> function fnEncBin
> (
> src : std_logic_vector
> ) return std_logic_vector is
> variable rslt : std_logic_vector( fnLog2M( src'length ) - 1 downto 0 ) ;
> begin
> rslt := ( rslt'range => '0' ) ;
> for rslt_idx in rslt'range loop
> for src_idx in src'length - 1 downto 0 loop
> if( ( ( src_idx / ( 2**rslt_idx ) ) MOD 2 ) = 1 ) then
> rslt( rslt_idx ) := rslt( rslt_idx ) OR src( src_idx + src'low ) ;
> end if ;
> end loop ;
> end loop ;
> return( rslt ) ;
> end ;
>
> Put in an eight bit vector, get 3) 4 input LUT's independent of the tool.
--
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
Article: 41893The only two approaches I know about include 1) doing it manually, or 2) using the Certify software from Synplicity. While there may be other partitioning tools out there, Synplicity is the only house I'm aware of that's put strong effort into making the system work for the large designs. It isn't freeware, but evaluate the time for item 1). It may be worth it. Sujatha Sriram wrote: > > Can anyone tell me where I can find sites or material related to > partioning of huge designs in to multiple (or single FPGAs) for ASIC > prototyping purposes > > sujathaArticle: 41894
Hi, i'm starting with a new project. In this project i can use both an XC9572-10 PC44 or XC9572-10 PC84. The resources used with the actual program are: Macrocells: 52 /72 ( 72%) Product Terms: 313/360 ( 86%) To choose the package of the CPLD (44 or 84 pins) i must decide if i can implement four octal three-state latch buffer ( 74HC573) in the last free resurces of the IC or not. I would like to use the 84 pins CPLD, I have pins enough, but i don't know if the resources are sufficient. Can anybody help me to solve this problem? Thanks, Frank.Article: 41895
Antonio I think you are referring to the RC1000 FPGA Prototyping board? The library that is distributed with the RC1000 board only supports MS compilers, however it's worth contacting Celoxica because I think there could be an unsupported Borland and Linux GCC version around. I have had no problem with addone.c or any other programs, albeit I use MSVC. Cheers John "Antonio Martínez Álvarez" <amartinez@atc.ugr.es> wrote in message news:a8uddh$2dj$1@mercurio.cica.es... > Hello, > > I'd like to know how to obtain an executable file from the HandelC's example > "addone.c". > I've read everything I've found but It doesn't work. > > We would like to produce the same results (executables) that comes from > Celoxica (addone.exe, video.exe dma.exe ...). > What are the exactly the steps we must to follow? > > > Our System especifications: > We have gcc 2.95.3-5 installed. We don't want Visual C to do this. > Windows 2000 Proffesional > DK1.1 > > Thank you. > > -- > Antonio Martínez Álvarez -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 41896
HI; Thanks for reading this... I have Webpack and an old serial loader A DLC4. Can I use it with webpack? IS there a way to do It. I want to ISP a 9500 series CPLD. Thanks; C.W. THomasArticle: 41897
This is exactly what we proposed to Darpa when they had their "adaptive computing" program. Instead they decided to give 40% of the money to someone who was an expert in the analog/wireless world who just happened to have been one of the temporary managers of the program before he quit to get the contract. It's too bad. Our proposal pointed out that a PCI based system has way too much latency to address many of the applications that reconfigurable computing could accelerate. Of course they came to the same conclusion it just took more than $10M (I think it was 20) for them to figure that out through all their great research. Steve Casselman "Frank de Groot" <franciscus_andreas@hotmail.com> wrote in message news:3cb4172e$1@news.wineasy.se... > I found a German board with a dedicated PCI chip, very cheap too, > about 200 $, but... I have a big problem with the PCI bandwidth. > I really need something that WOULD take around 300 Pentium clockcycles, > and get that done by the FPGA in 30 Pentium clockcycles, including all bus > I/O. > > So what I need is a few dozen Pentium clockcycles to give the FPGA a task, > which is examining a pattern on a small grid, then I need a boolan answer > from the FPGA. > I need tens of millions of those boolean answers per second, otherwise it is > not a viable idea. > > What I need is a way to interface with the FPGA like I was accessing Pentium > cache memory, > or I need to have a FPGA + processor board, which I could feed a much more > complex task. > > Sorry it took me such a long time to realize that. I am starting to think > that current technology is not > ripe for a low-cost FPGA coprocessor in a PC that features I/O like it was > normal memory (preferably cache even). > > When will Intel put a FPGA in its processors? Wouldn't that be the absolute > killer app? > > Frank > > > "Steve Casselman" <sc.nospam@vcc.com> wrote in message > news:X0us8.1399$d52.739929240@newssvr14.news.prodigy.com... > > Isn't there a free PCI core at opencores.org? > > > > Steve > > > > > > Does the "no one project license for LogiCORE PCI" mean that I am not > > >Article: 41898
luigi funes wrote: > > Hi, > there are differences, except the price, between the two > Altera CPLDs in subject? EP1k is Altera's answer to Spartan. It's a 10k die shrink with a new pinout intended to compete for new small designs while keeping the cash flowing on old 10k designs. -- Mike TreselerArticle: 41899
Hi Folks, I am having problems with the Virtex Block RAMs. I want to implement a 4096 bit shift register using Virtex Block Rams. I used a 12 bit counter to address a dual ported BlockRAM: RAMB4_S1_S1. The write port is addressed by an output that is '1 clock cycle' behind the counter's output. That way the WRITE will occur 1 cycle behind the READ at any instance. Whenever I simulate the circuit, I am getting the following error each time the RAM address reaches 1024: /*** Memory Read - Exceeds memory Bounds **/ i.e. each time the 11th bit turn to 1, it complains about memory bounds being exceeded although the RAM configuration is 4096x1 bit!!?? Any help???
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