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dasari wrote: > hai, > > Is it possible to implement a 16-bit LFSR using one CLB of XC4000 > series. > By configuring One 4 to 1 LUT as a shift register, and assuming there > is only one 2-inout Xor gate in the feedback? (considering any tap > points!) > > Please let me know how many min. no. of CLB's might require to do > this. > > inputs: clk > outputs: dout(1 bit) (serially reading the data_out) I guess you need at least 16 Flipflops. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 50776
anglomont@yahoo.com (TI) wrote in message news:<18a34598.0212182353.4ff94ba4@posting.google.com>... > Dear all, > I am an Electrical Engineer > and I would like to specialize in the area of VLSI. > I wonder if there are any VLSI courses offered in Romania, Austria , > Greece or Russia > in English(or Russian) commercially/non-commercially that cover > perhaps: > -Techniques for digital system design > -Hardware description languages > -Design methodology for VLSI circuits and systems: ASIC, FPGA, PLD > -Employing EDA tools like: ModelSim, Leonardo, Xilinx, Altera, etc. > That could be either at some company or training center or maybe > through distance > internet course, > please let me know of any details > > PS How suitable are fpga for realisation of telecom chips for example > an OFDM modem core? Eminently esp the more recent virtex with many 18.18 multipliers included. I think the major block of OFDM would be the FFT engine, which can be designed from 1st principles or acquired from Xilinx and several othere parties. Last FFT I was involved in did 1024 complex about every 3us, forward and backwards plus a boat load of other math, ran at about 120MHz.Article: 50777
Rene Tschaggelar wrote: > I have an ACEX1k30 together with an EPC2 in JTAG multichain > configuration. The pair is prgrammeable with the Byteblaster > adapter, plus the relevant pins TMS, TDI, TDO and TCK of the > adapter are connected to a microcontroller (AVR), tristated while > not used. This to keep the normal way of programming. > > Before decoding the Byteblaster stream, I went to have a look > at the various application notes. To little avail. > They were AN116, AN111, AN100, AN88, AN95 > > Since the *.pof and the *.sof appear to require interpretation > by MaxPlus2 or Quartus2, the preferred format would be *.rbf > it appears. But is the created rbf sufficient for the ACEX as > well as for the configuration flash ? > Since *.pof and *.sof are not identical, I assume I require > two different files too. > > I tend to think the subject is far simpler than I now look at. > > Any hints ? It appears, the *.rbf is only available for some parallel modes plus the passive serial, but not the JTAG. I somewhere read the ACEX programming stream is CRC protected. I couldn't yet figure out what this means to the programming task. ReneArticle: 50778
On Thu, 19 Dec 2002 11:26:24 +0100, Rene Tschaggelar <tschaggelar@dplanet.ch> wrote: >dasari wrote: >> hai, >> >> Is it possible to implement a 16-bit LFSR using one CLB of XC4000 >> series. >> By configuring One 4 to 1 LUT as a shift register, and assuming there >> is only one 2-inout Xor gate in the feedback? (considering any tap >> points!) >> >> Please let me know how many min. no. of CLB's might require to do >> this. >> >> inputs: clk >> outputs: dout(1 bit) (serially reading the data_out) > > >I guess you need at least 16 Flipflops. The 4000 series (unlike Virtex) doesn't allow LUTs to be used directly as shift registers, but you *can* use them as ram. Solution 1: Use a LUT configured as a synchronous 1 bit ram to save a FF. This halves the hardware requirements to about 8 LEs. (1 LE = 1 LUT + FF). This would be 4 CLBs on a 4000 series part. Solution 2: Use a single LUT configured as a 16 bit ram and some control logic to mimic a shift register. This is more complicated, and I don't think there would be any saving in area because a 16 bit maximual length LFSR requires 4 taps (what did the OP hope to do with 2?), and this would increase the size of the control logic. Regards, Allan.Article: 50779
Hi all
I want to implement FPGA-based caller ID "FSK" .the algorithm
implementation is not difficult but the problem is how to lock to the
start of each bit .or by another word to "synchronize" .
As Baudrate =1200 and F1=1200 F2=2200 ... the mark & space is not
orthogonals and very close ....i don't know why they choose
frequencies like this ?? why they don't select orthogonal frequencies
in order to be easy to be detected ?
Any way , do you have any solution for demodulating BFSK with these
parameters ?
Thanks
Haytham
Article: 50780Hi, I Have 2 Flip Flops (FF1 and FF2). The actual combination logic delay in between these FFs are 10ns. Say i have defined a path between FF1 and FF2 as a multicycle path in synplify_pro synthesis. Here is my questions regarding this? 1. Will the synplify_pro tool will put an additional FF between these FF1 and FF2? or it will simple assume that the dealy between these Flip-Flops are 5ns. 2. I know that, this multicycle path information will be passed to the Place and Route tool. what the place and route tool will do? will it put some FFs in between ? or this is simply for timing report generation? Thanks in advance Best regards, MuthuArticle: 50781
What exactly is your goal? Are you trying to verify correctness of the logic, or tht
configuration has not been corrupted? With FPGAs, the application program can be treated
much like a software program for the purposes of testing. If the device is known good and
the application bitstream is fully debugged, it will be correct when put in the FPGA. You
can check the FPGA health with test vectors BEFORE putting your application in the FPGA,
then monitor the health with some relatively simple tests. You could go to the other end
of the spectrum and do full TMR on the whole design if it is critical, but that is not
cheap. So frankly, you need to define the goals of your BIST before you decide what
approach is to be used.
dasari wrote:
> Hai Ray!,
>
> True. I would like to know if there some proven BIST structures like
> LFSR, MISR, BILBO.., for standard arithmetics, test point insertion
> methods etc..
> targetted to Xilinx xc4000 architecture which consumes less area.
>
> If some one give info. regarding the specific BIST architectures for
> 16-/32-bit floating/Fixed point(IEEE standard) adders. (some proven
> results!), it helps me a lot.
>
> Thank you all,
> Dasari.
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3E00F72D.9711BDD5@andraka.com>...
> > There are no dedicated BIST structures, you include whatever you need for
> > testing in your design which then gets loaded into the FPGA. SRAM type
> > FPGAs do offer a distinct advantage over conventional logic in that you
> > can reconfigure to do board level testing, thereby taking the FPGA
> > functionality out of the loop. My paper "An FPGA Based Processor Yields
> > a Real Time High Fidelity Radar Environment Simulator", available on my
> > website at no charge, goes into some detail on system test with
> > reconfigurable FPGAs.
> >
> > dasari wrote:
> >
> > > hai,
> > >
> > > I would like to know the BIST structures for Xilinx FPGAs for on-line
> > > functional test. Please let me know if there are some specific
> > > configurable BIST structures for any generic logic/Arithmetic logic.
> > >
> > > Thanks,
> > > Dasari.
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50782
Depends on what the OP wanted to do with the LFSR output. If the goal is
just to get a pseudo-random bit output He could get a 17 or 18 bit LFSR
into 3 CLBs. Two for a 4 bit count to the memory address, one for the RAM,
a flip-flop and the xor. The counter can be shared among multiple LFSRs if
desired.
Allan Herriman wrote:
> On Thu, 19 Dec 2002 11:26:24 +0100, Rene Tschaggelar
> <tschaggelar@dplanet.ch> wrote:
>
> >dasari wrote:
> >> hai,
> >>
> >> Is it possible to implement a 16-bit LFSR using one CLB of XC4000
> >> series.
> >> By configuring One 4 to 1 LUT as a shift register, and assuming there
> >> is only one 2-inout Xor gate in the feedback? (considering any tap
> >> points!)
> >>
> >> Please let me know how many min. no. of CLB's might require to do
> >> this.
> >>
> >> inputs: clk
> >> outputs: dout(1 bit) (serially reading the data_out)
> >
> >
> >I guess you need at least 16 Flipflops.
>
> The 4000 series (unlike Virtex) doesn't allow LUTs to be used directly
> as shift registers, but you *can* use them as ram.
>
> Solution 1:
> Use a LUT configured as a synchronous 1 bit ram to save a FF.
> This halves the hardware requirements to about 8 LEs. (1 LE = 1 LUT +
> FF). This would be 4 CLBs on a 4000 series part.
>
> Solution 2:
> Use a single LUT configured as a 16 bit ram and some control logic to
> mimic a shift register. This is more complicated, and I don't think
> there would be any saving in area because a 16 bit maximual length
> LFSR requires 4 taps (what did the OP hope to do with 2?), and this
> would increase the size of the control logic.
>
> Regards,
> Allan.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50783Hi, Thanks everyone for the suggestions. My FPGA runs @ 40MHz and the RAM specs say its a 10ns RAM. I thought @ 40MHz the FPGA ran slow enough for the RAM to be accessed comfortably. But I will take your suggestion and give the RAM more time to fetch data. Thanks again, PrashantArticle: 50784
Christopher,
Of course the easy way to avoid the necessity to know
the pins of a vendors gate library is to use one of the
hardware description languages, such as VHDL.
Below is an asynchronous reset coded in VHDL:
AsyncRegProc : process(nReset, Clk)
begin
if (nReset = '0') then
MyReg <= '0' ;
elsif rising_edge(Clk) then
MyReg <= '1' ;
end if ;
end process ;
Now to do your circuit (my guess at what you described):
PhaseReset <= PhaseReg1 and PhaseReg2 ;
PhaseReg1Proc : process(PhaseReset, PhaseIn1)
begin
if (PhaseReset = '1') then
PhaseReg1 <= '0' ;
elsif rising_edge(PhaseIn1) then
PhaseReg1 <= '1' ;
end if ;
end process ;
PhaseReg2Proc process(PhaseReset, PhaseIn2)
begin
if (PhaseReset = '1') then
PhaseReg2 <= '0' ;
elsif rising_edge(PhaseIn2) then
PhaseReg2 <= '1' ;
end if ;
end process ;
Once you have a description in this fashion,
you can reuse it with other devices.
By the way, VHDL was developed by DARPA and
is often a program requirement for government
hardware design projects, so it would be a
good choice for you based on your email address.
Cheers,
Jim Lewis
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Christopher R. Carlen wrote:
> Hi:
>
> I am using a Xilinx XPLA3 CPLD and the WebPack 4.2 software.
>
> I am trying to make a simple circuit consisting of two D-flip flops and
> an AND gate. The Q outputs of the FFs go to the AND gate inputs, and
> the AND gate output goes to the asynchronous reset inputs of the FFs.
>
> This is to implement a 3-state phase/frequency detector for use in a
> PLL. The D inputs of the FFs go to VCC, and the clock inputs are the
> real world inputs. Likewise for the Q outputs as well.
>
> After discovering that the circuit didn't work as expected, I
> reprogrammed the chip to expose a single flip flop to the outside, that
> is, the D, clk, R, and Q signals buffered to four IOs.
>
> I have discovered that the R input is not in fact an asynchronous reset
> input, but instead it doesn't do its thing until a clock pulse comes
> along. This is very strange, but I suppose I simply assumed that R
> meant something that it doesn't seem to mean.
>
> How can I make an asynchronous flip flop reset input, or an asynchronous
> set for that matter?
>
> I am using the schematic editor, and using the flip flop that is called
> "FDR". I can post the HDL if you want, but I don't know how to write
> HDL yet. I think that the schematic creates what the software refers to
> as the "verilog functional model" which is a file that looks like
> program code. I suspect that I would write that by hand if I wanted to
> design without the schematic entry, right?
>
> Thanks for comments.
>
> Good day.
>
Article: 50785Muthu wrote: > Hi, > > I Have 2 Flip Flops (FF1 and FF2). The actual combination logic delay > in between these FFs are 10ns. Say i have defined a path between FF1 > and FF2 as a multicycle path in synplify_pro synthesis. > > Here is my questions regarding this? > > 1. Will the synplify_pro tool will put an additional FF between these > FF1 and FF2? or it will simple assume that the dealy between these > Flip-Flops are 5ns. It will increase the available time for paths between FF1 and FF2 according to the number of cycles you specify. > > 2. I know that, this multicycle path information will be passed to the > Place and Route tool. what the place and route tool will do? The same thing. > > will it put some FFs in between ? or this is simply for timing report > generation? No logic change is implied by a multi-cycle path specification. > > Thanks in advance > > Best regards, > Muthu >Article: 50786
> Thanks everyone for the suggestions. My FPGA runs @ 40MHz and the RAM
> specs say its a 10ns RAM. I thought @ 40MHz the FPGA ran slow enough
> for the RAM to be accessed comfortably. But I will take your
> suggestion and give the RAM more time to fetch data.
WHOA THERE! You didn't listen!
If it's 10ns SRAM with a 40MHz clock then you probably have plenty
of time to do the fetch (although you should check the delay through
the FPGA's I/O pads, since they can be quite slow). BUT..
THE PROBLEM IS PROBABLY RELATED TO DATA HOLD TIME AT THE END OF
WRITE CYCLES. I thought I'd said that clearly, but it's worth
saying again. You MUST ensure that write data and address
are held valid for some time AFTER the end of your write strobe
pulse. It's tedious, but it's important.
With a 25ns clock you should be able to play tricks with
2-phase clocking... (view in monospaced font)
WRITE CYCLE...
__ __ __ __
clk __| |__| |__| |__|
: :_____: :
data, adrs XXXXXXXXX_____XXXXXXXXX (clocked by rising edge)
___:_____: __:_____:__
nWE |__|
Note that nWE is asserted on rising edge and removed on
falling edge of clock. Get this by ORing together two
signals, one synchronised to clock rise and the other to
clock fall...
__ __ __ __
clk __| |__| |__| |__|
___:__ : __:_____:__
nWE_early |_____| (clocked by falling edge)
___:_____: :_____:__
nWE_late |_____| (clocked by rising edge)
___:_____: __:_____:__
nWE |__| (nWE_late OR nWE_early)
But be ready to go back to slower multi-cycle writes if
things don't quite go right. My suggestion may give rise
to problems because the address might be changing during the
early part of the write cycle. Read your RAM data sheet
very carefully.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 50787Ken, Just one comment on multi-cycle path contraints. I have found that if you use them, you must use the "from" "through" and "to" form (all three) in order not to confuse the tools (with no 'wild cards'). If you don't specify all three (and carefully), the constraints may actually be lessened, instead of tightened where intended. Is this your experience as well? Austin Ken McElvain wrote: > Muthu wrote: > > > Hi, > > > > I Have 2 Flip Flops (FF1 and FF2). The actual combination logic delay > > in between these FFs are 10ns. Say i have defined a path between FF1 > > and FF2 as a multicycle path in synplify_pro synthesis. > > > > Here is my questions regarding this? > > > > 1. Will the synplify_pro tool will put an additional FF between these > > FF1 and FF2? or it will simple assume that the dealy between these > > Flip-Flops are 5ns. > > It will increase the available time for paths between FF1 and FF2 > according to the number of cycles you specify. > > > > > 2. I know that, this multicycle path information will be passed to the > > Place and Route tool. what the place and route tool will do? > > The same thing. > > > > > will it put some FFs in between ? or this is simply for timing report > > generation? > > No logic change is implied by a multi-cycle path specification. > > > > > Thanks in advance > > > > Best regards, > > Muthu > >Article: 50788
Hello, I am currently looking for either : - a CDB 8959 Eval Board (Ethernet 10/100 Eval from Crystal) a used one (preferably still working :-) wld be fine. Any equivalent (10/100 PHY - MII) would be fine too. or : - a small FPGA board embedding Ethernet 10/100 PHY, apart from : * Nios board + extension * Xess 800 (too large & too many features) Thanks in advance for any offer/suggestion, Bert bcuzeau@_remove_this_and_keep_only:usa.net -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 50789
Hi, Try to use the jam-player. The source code and application notes for 80C51 are available for free on the Altera website. I done it with the Fujitsu controllers and it's fairly easy to do. Chris Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<3E009F1E.5070706@dplanet.ch>... > I have an ACEX1k30 together with an EPC2 in JTAG multichain > configuration. The pair is prgrammeable with the Byteblaster > adapter, plus the relevant pins TMS, TDI, TDO and TCK of the > adapter are connected to a microcontroller (AVR), tristated while > not used. This to keep the normal way of programming. > > Before decoding the Byteblaster stream, I went to have a look > at the various application notes. To little avail. > They were AN116, AN111, AN100, AN88, AN95 > > Since the *.pof and the *.sof appear to require interpretation > by MaxPlus2 or Quartus2, the preferred format would be *.rbf > it appears. But is the created rbf sufficient for the ACEX as > well as for the configuration flash ? > Since *.pof and *.sof are not identical, I assume I require > two different files too. > > I tend to think the subject is far simpler than I now look at. > > Any hints ?Article: 50790
Hi Tom,
Thomas Womack <pmxtow@merlot.uucp> wrote:
> This may be an incoherent request, but I'll go ahead.
>
> When I last played with electronics, resistors were little cylindrical
> things with long wire legs, and ICs had at most forty pins, which came
> out of the side at convenient 2.54mm spacing; you could design on
> bread-board. If you wanted to connect to a computer, you used the
> parallel port, or the four-channel analogue-digital converter on the
> BBC Micro joystick port. If you were really advanced, you might try to
> build a two-layer PCB with little metal fingers at the bottom to plug
> into an ISA slot on a PC.
Sounds like what I do at work :-) Seriously, just because everything has
gone surface mount isn't necessarily a good reason for you to do the same.
We deal almost exclusively with through-hole components because the boards
are easy to repair in the field (20000ukp machines in hospitals). Often you
can get away with using through-hole if you want, with perhaps daughter
boards with surface mount chips on them. The speed won't be wonderful, but
if you're hacking sometimes you don't really care about speed.
> So, what do people do to prototype now? As I read it, you do a lot in
> simulation and then, once you're happy with a design, you send a file
> to a boutiquie to get a PCB made and the components fitted to it. How
> much does it cost to get one two- or four-layer PCB made, how long
> does it take, and do you have to provide the company with all the
> components you want fitted, or will they have 1kohm surface-mount
> resistors and 555 oscillators in stock?
It depends. I'm just getting my first board built at home - through a
contact, so it isn't costing me anything - but I've heard
http://www.olimex.com/pcb recommended. They're in Bulgaria, but a double
sided 160x100mm board is $26 plus postage, which is very good (and $5
postage is probably cheaper for UK people than fabbing in the US).
You _can_ get people to build boards for you, but you'll be stung by the
tooling charge for small quantities. Also getting obscure components in small
quantities is difficult - you have to pretend[1] to be a company before
distributors will talk to you, but you can sometimes get samples (eg Maxim
give them free from their website).
[1] AFAIK completely legally. IANAL, but anyone can be a sole trader
without any paperwork if you don't make a profit - this is what I do to stop
silly web forms from telling me to go back and fill in the company field.
Surface mount soldering is possible by hand. I've done it with a piece of
wire wrapped around a free-with-cornflake-packet iron - not the best tools
for the job, but possible. If you don't go down the PCB route, another
method is to solder wires to each pad to convert the SMD to a through-hole
layout - tedious but possible. For an example, see a board I built:
http://www.chiark.greenend.org.uk/~theom/riscos/superio/
If you're into getting components (since I know you're in the UK), Maplin
are fairly useless these days unless you're near a shop, but it's often
still easier to mail order. Rapid http://www.rapidelec.co.uk/ are very good
and cheap (definitely worth getting a catalogue), whilst RS
http://rswww.com/ and Farnell http://www.farnell.com/ are more expensive but
have wider ranges. For credit cards, Farnell have a minimum order of 10ukp
whilst Rapid charge 3ukp postage below 30ukp of order (haven't used RS
recently from home, so can't comment). Rapid are better at selling things
in small quantities (sometimes Farnell/RS only sell things in packs of 5 or
10).
> How do you interface widgets to a computer nowadays? Are there chips
> which can convert USB or PCI to something easier to contemplate; is it
> practical for a hobbyist to connect things to the PCI bus?
There are USB microcontrollers out there; Cypress make some. There are also
USB to serial chips - there's a thread on comp.arch.embedded on this very
subject at the moment.
> Which is the right group for me to be asking these questions in?
comp.arch.hobbyist is another group to look at. It's fairly low traffic,
but mostly consists of people doing this sort of thing at home, as opposed
to full time (so can't afford $$$ for tools etc - but there are tricks to
get around this). It's bot-moderated (to stop floods of OT noise it was
receiving), but if you post you'll get an email explaining it all.
Hope this helps,
Theo
PS Tom, grab me (caliston) on #chiark if there's anything you want to
ask with a slightly lower latency :-)
--
Theo Markettos theo@markettos.org.uk
Liphook, Hampshire, UK theom@chiark.greenend.org.uk
http://www.markettos.org.uk/
Article: 50791I want to programme an ACEX1K (where I put a NIOS CPU) using a simple CPLD (as controller) and a Flash Eprom in which I have the FPGA configuration and the application. Do you have a VHDL source for the controller that download the FPGA? Thank you very much for your help. Giorgio Giaccaglini Aethra Telecommunication Italy +39 02 2189877 g.giaccaglini@aethra.it www.aethra.itArticle: 50792
......... > if CLKIN='1' and CLKIN'event then > QOUT <= cnt2; > cnt2 := "00000000"; ................................. Frankly I've never seen a counter been reset by a clock edge.... You propabbly invent something new... good luckArticle: 50793
Lorenzo Lutti wrote: > > "Allan Herriman" <allan_herriman.hates.spam@agilent.com> ha scritto nel > messaggio news:3e006906.33423169@netnews.agilent.com... > > > These won't even come close to being able to convert 10 > > bit values at > > 2.5MHz. > > In the previous message I haven't noticed the 2.5 MHz thing; I agree > with you. Anyway, I think that the delta-sigma approach (even with an > external ADC) should be better in order to avoid the switching noise: > they are inherently better for this kind of problems. > > Sadly, I'm not sure that you can find sigma-delta ADCs so fast. I have > seen some at 200-300 kSPS, not more. > > The other user can try with a flash converter. It should be better than > a SAR (obviously is costs more). Actually, I don't think a Flash converter of 10 bits at 5 MHz would cost any more than an SAR converter at the same speed. I have looked at a few high res SARs below 1 MSPS and they get very pricey. Perhaps a 12 bit SAR converter would not be so expensive, but I have not seen them at 2.5 MSPS. But then I haven't been looking. I do know that this is the low end for 10 bit Flash converters and Flash converters have up to 14 bits these days. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50794
I have seen this. I avoid multicycle constraints as much as possible because it
is too easy to inadvertantly relax a constraint you didn't intend on relaxing.
It also keeps those who maintain the design honest.
Austin Lesea wrote:
> Ken,
>
> Just one comment on multi-cycle path contraints. I have found that if you
> use them, you must use the "from" "through" and "to" form (all three) in
> order not to confuse the tools (with no 'wild cards'). If you don't specify
> all three (and carefully), the constraints may actually be lessened, instead
> of tightened where intended.
>
> Is this your experience as well?
>
> Austin
>
> Ken McElvain wrote:
>
> > Muthu wrote:
> >
> > > Hi,
> > >
> > > I Have 2 Flip Flops (FF1 and FF2). The actual combination logic delay
> > > in between these FFs are 10ns. Say i have defined a path between FF1
> > > and FF2 as a multicycle path in synplify_pro synthesis.
> > >
> > > Here is my questions regarding this?
> > >
> > > 1. Will the synplify_pro tool will put an additional FF between these
> > > FF1 and FF2? or it will simple assume that the dealy between these
> > > Flip-Flops are 5ns.
> >
> > It will increase the available time for paths between FF1 and FF2
> > according to the number of cycles you specify.
> >
> > >
> > > 2. I know that, this multicycle path information will be passed to the
> > > Place and Route tool. what the place and route tool will do?
> >
> > The same thing.
> >
> > >
> > > will it put some FFs in between ? or this is simply for timing report
> > > generation?
> >
> > No logic change is implied by a multi-cycle path specification.
> >
> > >
> > > Thanks in advance
> > >
> > > Best regards,
> > > Muthu
> > >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50795Bill Sloman wrote: > > Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3E010DF1.1685@designtools.co.nz>... > > Bill Sloman wrote: > > > > > > Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3E00C2F3.31A0@designtools.co.nz>... > > > > Multi-Cycle averaging makes a very important assumption about the > > > > errors, that they are random, and evenly distributed. > > > > Real ADCs do not always follow classic maths, so large base averages do > > > > not give the expected noise reductions. Use a better ADC... > > I made this point once when refereeing a paper for "Measurement > Science and Technology" - not clearly enough, becasue they published > it despite my objections. Perhaps I missed something. The noise created by the ADC may not average out if it is not evenly distributed, but the external noise is not related to the ADC noise. If this external noise is uncorrelated to the sample clock and it is evenly distributed, then you should see a noise improvement by mutisample averaging. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50796
Ray, Thought so, thanks for the sanity check. Austin Ray Andraka wrote: > I have seen this. I avoid multicycle constraints as much as possible because it > is too easy to inadvertantly relax a constraint you didn't intend on relaxing. > It also keeps those who maintain the design honest. > > Austin Lesea wrote: > > > Ken, > > > > Just one comment on multi-cycle path contraints. I have found that if you > > use them, you must use the "from" "through" and "to" form (all three) in > > order not to confuse the tools (with no 'wild cards'). If you don't specify > > all three (and carefully), the constraints may actually be lessened, instead > > of tightened where intended. > > > > Is this your experience as well? > > > > Austin > > > > Ken McElvain wrote: > > > > > Muthu wrote: > > > > > > > Hi, > > > > > > > > I Have 2 Flip Flops (FF1 and FF2). The actual combination logic delay > > > > in between these FFs are 10ns. Say i have defined a path between FF1 > > > > and FF2 as a multicycle path in synplify_pro synthesis. > > > > > > > > Here is my questions regarding this? > > > > > > > > 1. Will the synplify_pro tool will put an additional FF between these > > > > FF1 and FF2? or it will simple assume that the dealy between these > > > > Flip-Flops are 5ns. > > > > > > It will increase the available time for paths between FF1 and FF2 > > > according to the number of cycles you specify. > > > > > > > > > > > 2. I know that, this multicycle path information will be passed to the > > > > Place and Route tool. what the place and route tool will do? > > > > > > The same thing. > > > > > > > > > > > will it put some FFs in between ? or this is simply for timing report > > > > generation? > > > > > > No logic change is implied by a multi-cycle path specification. > > > > > > > > > > > Thanks in advance > > > > > > > > Best regards, > > > > Muthu > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 50797
Jonathan Bromley wrote: >>Thanks everyone for the suggestions. My FPGA runs @ 40MHz and the RAM >>specs say its a 10ns RAM. I thought @ 40MHz the FPGA ran slow enough >>for the RAM to be accessed comfortably. But I will take your >>suggestion and give the RAM more time to fetch data. > doable, yes, comfortable no ... > > WHOA THERE! You didn't listen! > > If it's 10ns SRAM with a 40MHz clock then you probably have plenty > of time to do the fetch (although you should check the delay through > the FPGA's I/O pads, since they can be quite slow). BUT.. > > THE PROBLEM IS PROBABLY RELATED TO DATA HOLD TIME AT THE END OF > WRITE CYCLES. I thought I'd said that clearly, but it's worth > saying again. You MUST ensure that write data and address > are held valid for some time AFTER the end of your write strobe > pulse. It's tedious, but it's important. > > With a 25ns clock you should be able to play tricks with > 2-phase clocking... (view in monospaced font) > > WRITE CYCLE... > __ __ __ __ > clk __| |__| |__| |__| > : :_____: : > data, adrs XXXXXXXXX_____XXXXXXXXX (clocked by rising edge) > > ___:_____: __:_____:__ > nWE |__| > I did the same kind of design (Spartan II, 10ns K6R4008V1C SRAM / 48Mhz) but with a minor change. As shown above, I keep the adrs bus on for the whole cycle, but I drive the data bus only during the active period of your nWE. Driving it for the whole cycle is likely to create bus contention if the write is followed by a read. The minor change is that I add "weak keeper" symbols to the data pins so that they keep their logic state even after I stop driving them (thus avoiding data hold time violation). It also works for read cycles where the data is sampled while releasing nOE (this might work simply with capacitive loading, the keepers are for peace of mind) For it to work properly , the SRAM must go hiZ cleanly (not driving transient garbage on the data bus) but I never saw this being a problem. > > Note that nWE is asserted on rising edge and removed on > falling edge of clock. Get this by ORing together two > signals, one synchronised to clock rise and the other to > clock fall... > __ __ __ __ > clk __| |__| |__| |__| > ___:__ : __:_____:__ > nWE_early |_____| (clocked by falling edge) > ___:_____: :_____:__ > nWE_late |_____| (clocked by rising edge) > ___:_____: __:_____:__ > nWE |__| (nWE_late OR nWE_early) > > > But be ready to go back to slower multi-cycle writes if > things don't quite go right. My suggestion may give rise > to problems because the address might be changing during the > early part of the write cycle. Read your RAM data sheet > very carefully. To prevent this problem, I drive the nCS signal using the same clock as addr, nCS is a fast "F16" driver, bidirectional signal. the nWE pin is driven with nCS feedback (delayed) input OR the logical value for nWE. I use a slower "F6" driver for it. Combinatorial delay for the nWE signal is : t(nCS Driver) + t(nCS receiver with built in delay element) + t(LUT [the OR gate]) + t(nWE driver) Combinatorial delay for the nCS signal is : t(nCS Driver) Combinatorial delay for the addr bus is : t(addr(x) Driver) This gives an extra few ns delay between address / nCS change & nWE assertion. If, due to process variation, this delay becomes shorter, so is the address bus switching time and nWE will always lag behind (if routing/placement is properly done) The SRAM I use have a 0ns specification for adress to nWE (this means nWE is internally delayed) and minimum nWE pulse width is a short 7ns. ---------- Another way to go at these frequencies would be to use the 90 deg output (or 2x out) of a DLL to double time resolution and correct clock mark/space ratio (another cause for timing errors and unreliable async SRAM operation). Going that way enables more predictable signal sequencing and avoid the frowned upon use of async delays. If I had to do it again, I'd probably go that way. hope this helps. Eric PS : For unobfuscated email, remove "not" and "me" Samsung K6R4008V1D datasheet : http://www.samsungelectronics.com/semiconductors/SRAM/High_Speed/Asynch_Fast/4M_bit/K6R4008V1D/k6r4008v1d.htm http://www.samsungelectronics.com/semiconductors/SRAM/High_Speed/Asynch_Fast/4M_bit/K6R4008V1D/ds_k6r4008v1d.pdf > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > >Article: 50798
rickman wrote: > > Bill Sloman wrote: > > > > Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3E010DF1.1685@designtools.co.nz>... > > > Bill Sloman wrote: > > > > > > > > Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3E00C2F3.31A0@designtools.co.nz>... > > > > > Multi-Cycle averaging makes a very important assumption about the > > > > > errors, that they are random, and evenly distributed. > > > > > Real ADCs do not always follow classic maths, so large base averages do > > > > > not give the expected noise reductions. Use a better ADC... > > > > I made this point once when refereeing a paper for "Measurement > > Science and Technology" - not clearly enough, becasue they published > > it despite my objections. > > Perhaps I missed something. The noise created by the ADC may not > average out if it is not evenly distributed, but the external noise is > not related to the ADC noise. If this external noise is uncorrelated to > the sample clock and it is evenly distributed, then you should see a > noise improvement by mutisample averaging. Yes, if the external noise is large, relative to the ADC errors and quantizing effects, then you can expect to see an average give improvement. Some 'wobble' on the IP signal can even help average below a LSB, but you do need to know and be confidant of the nature of the 'wobble' Using a better ADC is always a better alternative, and ~14 bits is doable at 2.5Mbits. Even using a single high performance ADC in the lab, to 'reality check' the noise/quantize/filtering assumptions is a good idea. -jgArticle: 50799
Just to avoid confusion: The only asynchronous operation in a Xilinx RAM is the reading of the distributed ( 16-bit deep) LUT-RAM. Everything else is synchronous and self-timed, without hold-time requirements. That means the writing of the LUT-RAM and the reading and the writing of the BlockRAM, in all flavors of Virtex and Spartan-II, are all synchronously referenced to the clock edge and have no address or data hold-time requirements. Peter Alfke, Xilinx Applications > > I did the same kind of design (Spartan II, 10ns K6R4008V1C > SRAM / 48Mhz) but with a minor change. >
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