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Hello, I am working on a project based on a Xilinx Spartan 2. The project inputs serial data encoded on two lines (A and B). The encoding is such that taking the xnor of both lines gives the serial clock. clk_sig <= A xnor B; The project seems to simulate correctly, but when programmed inchip does not work. I receive a warning "Gated clock. Clock net clk_sig is source by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop" which I think could be why it doesn't work when programmed. Is there a better way to do this xnor? I am using this clk signal as the clock for a state machine that is basically a serial to parallel converter. The clock is 1Mhz, but must be derived from the serial data somehow. The rest of the project runs on a 40Mhz clock that waits for the latched serial data. Thanks, TimArticle: 50951
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3E072DDD.7D8D5D26@yahoo.com>... > Jay wrote: > > > > Sometimes they're looking for nice credentials on paper because > > they're still trying to attract investment from people who couldn't > > judge a good engineer by any other means than the name of the school > > on the diploma, which is pretty funny because the correlation isn't > > all that high between a "top 5 school" and being a kick-ass designer. > > They'll figure it out eventually. > > That can go back to the principals being from the bio/chem world where > these credentials make all the difference. If they are trying to > attract investors, they will be selling the marketability of the end > result which will not be in the the engineering world, but in the > bio/chem world. > > -- > I thought the financing was already done hence the 50 odd employees already there. There is another angle, they are a European company and since I am too, I smell that all too familiar smell of stuffiness I thought I left behind. In my 1st job at Inmos, hiring was mostly limited to Oxford, Cambridge, Warwick, and some others for spice. I was not in the club then either, not well bred enough. The result was the Transputer project, quite radical, promising, intrigueing, unusual, .... It also was a commercial flop because in part of the culture that produced it refused to hire practiced experts in case they might produce something as ordinary as say the 68K. Perhaps they are hoping for some big out of the box thinking, Manhatten project class.Article: 50952
nachikap@yahoo.com (Nachiket Kapre) wrote in message news:<eadce17c.0212231014.41e76e89@posting.google.com>... > thanks a ton for the reply. those docs really helped a lot. Platform's > way is to spool off several tasks in parallel on several machines but > it is really pseudo parallel as each indiviual pc runs a unique test. > At the end of the day, you do get results quickly since multiple > simuations are running simultaneously. What i intended was to run a > single test on multiple PCs with the simulation poartitioned. Data > communication across simulators will then occur through sockets. > > regards, > Nachiket Kapre. > Design Engineer. > Paxonet Communications. > > "Steve Casselman" <sc@vcc.com> wrote in message news:<y_zN9.1278$sl.104130625@newssvr21.news.prodigy.com>... > > Sure why not? It is always possible to attempt anything. There are programs > > that will do distributed simulations... > > http://www.platform.com/PDFs/whitepapers/MUG_Oct2K1.pdf (this looks like the > > thing most people do) > > http://www.avery-design.com/web/simcluster.pdf > > > > DO a google search on > > > > distributed simulations modelsim > > > > > > Steve > > > > > > "Nachiket Kapre" <nachikap@yahoo.com> wrote in message > > news:eadce17c.0212220755.431fc33b@posting.google.com... > > > While simulating a complete ASIC (~5 million gates) consisting of > > > several individual blocks, is it possible to attempt a concurrent > > > simulation (functional or timing) in a distributed environment with a > > > pool of dedicated PCs simulating the individual blocks with > > > inter-block communication handled by PLI/FLI wrappers in Modelsim > > > which take care of "forcing" the signals driven by other blocks into > > > this block? Each individual PC needs to load only a small part of the > > > whole design and wait for new updates from interacting blocks. Pakcets > > > keep travelling to and fro between the PCs progressing the simulation. > > > It may also be possible to avoid IDLE time by allowing the individual > > > PCs to assume a certain set of inpout values and start simulating, if > > > later an update arrives that invalidates this assumption, all > > > subsequent operatins are rerun with these new inoouts and the > > > corresponding outputs generated invalidated. This will definitely > > > require mor thinking than can fit in a single email, but how is the > > > idea for starters?...and has it been tried before ? > > > It would'nt be wrong to mention that attempting such a simulation on a > > > single PC would be too tedious and time consuming. > > > > > > regards, > > > Nachiket Kapre. > > > Design Engineer. > > > Paxonet Communication Inc. I don't believe distributed ASIC/FPGA simulation is best done by chopping up blocks & distributing across a pool of cpus. The bandwidth needed to send signals between the blocks would slow down the overall result considerably. On the other hand if you want to run many smaller sims of lots of different test cases, then that usually just means separate license 1 per simulator and some workload SW like Compaq? has. If a very fast cycle C model is available that can run atleast say 10-1000x faster than HDL simulation, then you could run a C sim for the no of cycles desired and collect full state say every 1M cycles. Then a single HDL sim can be split into time chunks of 1M cycles each per cpu, now there is no communication between cpus save for collecting the desired detail results. Of course if you had a HDL->C compiler, then your C model comes for free & I assume it would run 10.. faster too but less detailed. I personally wouldn't do any project without a V2C compiler. C sims for most of the work, Verilog for detailed checks. Of course this is really meant for simpler clock schemes that have predicable time flows.Article: 50953
Tim <timdet@san.rr.com> wrote: : Hello, : I am working on a project based on a Xilinx Spartan 2. The project : inputs serial data encoded on two lines (A and B). The encoding is : such that taking the xnor of both lines gives the serial clock. : clk_sig <= A xnor B; : The project seems to simulate correctly, but when programmed inchip : does not work. : I receive a warning "Gated clock. Clock net clk_sig is source : by a combinatorial pin. This is not good design practice. Use the : CE pin to : control the loading of data into the flip-flop" : which I think could be why it doesn't work when programmed. : ... You probably don't instantiate a Clockbuffer to the clk_sig) signal. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50954
I'm not usually this dense, but some advice would be appreciated. I just upgraged my ISE software to the latest version and I can seem to figure out how to split a prom anymore. In 4.2.03i, the option "Generate Programming File -> Gnerate PROM File" lead to a program that had "Split Prom" on its file menu. The new one in 5.1.03i leads to a "Wizard" that does not end up splitting the prom. I have a design I have been working on with 3 18V04's and the bit stream is split between the three (its an XCV2000 part). Perhaps someone would be so kind as to do a step by step help note to get me back to splitting proms again so I can actually use the new software. -- Charles Krinke http://home.pacbell.net/cfk cfk@pacbell.netArticle: 50955
Since I brought up the Bio computing post, I have to wonder why there isn't more interest in using FPGA accelerators to speed up some of the EDA tools in a general way, ie given a std FPGA board, do a MMX SSE like check for turbo HW. I know at DAC, you can find any no of companies pushing HW accelerators but each seems very expensive and thoroughly proprietory to a vendor and the particular tool they are speeding up. I have seen Verilog simulation & ASIC emulation engines, but I can't recall HW used to speed up anything else. If you use one of those kits, the HW won't help any other task and it also comes in another big box. My XMAS wish would be to see standardized FPGA HW available to the power developer in a way that could be used for many tasks. It could mean using say a HandelC flow for some things of less importance, but for critical bottlenecks, a full blown C to HDL convert. I wouldn't mind working on such a problem myself, last time I did an ASIC Place n Route it took a week of cpu, you would think that engineers would want such a solution. happy holidays JJArticle: 50956
Hello, Having a small problem when generating a SOPC core using the SOPC Builder application. After I press "Generate", the system begins building the binary files. It runs into a problem when running the "nios-convert" application. The following errors are generated: # 2002.12.23 21:13:53 (*) cd d:/quartus/testproj ; nios-convert --outfile=nios_dev_board_flash_0_contents.srec --address_low=16384 --address_high=32768 Can't locate strict.pm in @INC (@INC contains: /cygdrive/d/altera/excalibur/sopc_builder_2_5/bin/perl_lib:/cygdrive/d/altera/excalibur/sopc_builder_2_5/bin/europa:/cygdrive/d/altera/excalibur/sopc_builder_2_5/bin: .) at - line 3. BEGIN failed--compilation aborted at - line 3. # mk_custom_sdk: WARNING 512 cd d:/quartus/testproj ; nios-convert --outfile=nios_dev_board_flash_0_contents.srec --address_low=16384 --address_high=32768 ERROR: Could not build Peripheral Contents for nios_0 Error in processing. System NOT successfully generated. As you can see, the perl interpreter cannot find strict.pm, although it is indeed located within: /cygdrive/d/altera/excalibur/sopc_builder_2_5/bin/perl_lib So the @INC array is correct, but it cannot find the proper perl module. Any help here? Thanks.Article: 50957
Hal Murray wrote: > > >I understand what you are saying, but this would not protect them from > >that. This protects them from someone revealing any information they > >may have gotten while visiting. I don't think you can get any > >protection for a patent since anyone claiming that you stole their idea > >would have to prove that they *had* an idea prior to the visit and prior > >to any of your proof of your idea. > > A company can protect its ideas by not telling the visitor about > them. > > The sign-in sheet probably says that the visitor won't reveal any > secrets. Or rather that anything he says isn't secret. So he can't > come back in a year or two and say they used his (secret) idea. No, the sheet said what I posted before. It was a non-disclosure that said you would not reveal any proprietary information you gained outside the company. Seems silly that anyone would try to protect their trade secrets this way since they have the onus to "protect" them. They are just trying to blanket cover everyone who walks into the facility, but I seriously doubt that this could be defended if vistors are not explicitly told that they had been given trade secrets. There is no point to anyone trying to claim trade secret theft against this company since if you are given a trade secret without an explicit non-disclosure agreement it is no longer a trade secret. The law puts the onus on you to protect your trade secrets. Unless they break into your building or violate a non-disclosure agreement there is no "theft". Once you give that secret to one person who is not under non-disclosure, it is no longer a trade secret. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50958
john jakson wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3E072DDD.7D8D5D26@yahoo.com>... > > Jay wrote: > > > > > > Sometimes they're looking for nice credentials on paper because > > > they're still trying to attract investment from people who couldn't > > > judge a good engineer by any other means than the name of the school > > > on the diploma, which is pretty funny because the correlation isn't > > > all that high between a "top 5 school" and being a kick-ass designer. > > > They'll figure it out eventually. > > > > That can go back to the principals being from the bio/chem world where > > these credentials make all the difference. If they are trying to > > attract investors, they will be selling the marketability of the end > > result which will not be in the the engineering world, but in the > > bio/chem world. > > > > -- > > > > I thought the financing was already done hence the 50 odd employees > already there. > > There is another angle, they are a European company and since I am > too, I smell that all too familiar smell of stuffiness I thought I > left behind. In my 1st job at Inmos, hiring was mostly limited to > Oxford, Cambridge, Warwick, and some others for spice. I was not in > the club then either, not well bred enough. The result was the > Transputer project, quite radical, promising, intrigueing, unusual, > .... It also was a commercial flop because in part of the culture that > produced it refused to hire practiced experts in case they might > produce something as ordinary as say the 68K. > > Perhaps they are hoping for some big out of the box thinking, > Manhatten project class. I always wondered why the Transputer was the way it was. It actually put off a lot of people because there were so many things that seemed strange about it. Not so much the unique architectural features, but a lot of the supporting software and debug things. I don't remember too many details, but for example, there was an instruction or assembler directive called "guy". Several people remarked on that. So even in a company that was embarking on a major project with an array of these processors, it was hard to get people to like the idea. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50959
Hi, This could be a silly question to many of you. But very important and unknown to me. Does Virtex DLL preserve wave shape? 1) If I give 30MHz square wave will the 1X output be 30MHz square wave? 2) If the input is 30MHz sine wave what will be the 1X output freq and wave shape? regards, NagarajArticle: 50960
Not a answer, more a question. What are the advantages of this serial encoding scheme? Is there a specific name for this kind encoding? Perhaps it's something I can put in my toolbox. Thanks Ralph "Tim" <timdet@san.rr.com> wrote in message news:3629ef86.0212231717.152eede1@posting.google.com... > Hello, > I am working on a project based on a Xilinx Spartan 2. The project > inputs serial data encoded on two lines (A and B). The encoding is > such that taking the xnor of both lines gives the serial clock. > clk_sig <= A xnor B; > > The project seems to simulate correctly, but when programmed inchip > does not work. > I receive a warning "Gated clock. Clock net clk_sig is source > by a combinatorial pin. This is not good design practice. Use the > CE pin to > control the loading of data into the flip-flop" > which I think could be why it doesn't work when programmed. > > Is there a better way to do this xnor? > I am using this clk signal as the clock for a state machine that is > basically a serial to parallel converter. The clock is 1Mhz, but must > be derived from the serial data somehow. > The rest of the project runs on a 40Mhz clock that waits for the > latched serial data. > Thanks, > TimArticle: 50961
On Tue, 24 Dec 2002 18:47:16 +1300, "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote: >Not a answer, more a question. > >What are the advantages of this serial encoding scheme? Is there a specific >name for this kind encoding? > >Perhaps it's something I can put in my toolbox. > >Thanks >Ralph > >"Tim" <timdet@san.rr.com> wrote in message >news:3629ef86.0212231717.152eede1@posting.google.com... >> Hello, >> I am working on a project based on a Xilinx Spartan 2. The project >> inputs serial data encoded on two lines (A and B). The encoding is >> such that taking the xnor of both lines gives the serial clock. >> clk_sig <= A xnor B; >> >> The project seems to simulate correctly, but when programmed inchip >> does not work. >> I receive a warning "Gated clock. Clock net clk_sig is source >> by a combinatorial pin. This is not good design practice. Use the >> CE pin to >> control the loading of data into the flip-flop" >> which I think could be why it doesn't work when programmed. >> >> Is there a better way to do this xnor? >> I am using this clk signal as the clock for a state machine that is >> basically a serial to parallel converter. The clock is 1Mhz, but must >> be derived from the serial data somehow. >> The rest of the project runs on a 40Mhz clock that waits for the >> latched serial data. >> Thanks, >> Tim > The encoding scheme sounds like 1394 where it's called data strobe encoding. It's supposed to have better jitter characteristics. Both strobe and data lines are used to recover clock which might be the reason why jitter is lower as oppposed to data and clock begin received on separate wires where there might be a systematic bias on one or the other. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 50962
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3E07E84E.4E15AAA1@yahoo.com... (snip) > > I always wondered why the Transputer was the way it was. It actually > put off a lot of people because there were so many things that seemed > strange about it. Not so much the unique architectural features, but a > lot of the supporting software and debug things. I don't remember too > many details, but for example, there was an instruction or assembler > directive called "guy". Several people remarked on that. So even in a > company that was embarking on a major project with an array of these > processors, it was hard to get people to like the idea. I don't want to start a big discussion about it, because that happened before. IBM S/360 (and successors) have a HER instruction. Also, the 6809 has a Sign EXtend instruction. Apparently the original 8086 documentation had that instruction, too, but it was later renamed. I don't believe the 6809 instruction was ever renamed. -- glenArticle: 50963
John; I agree. I would like a HW accelerator tool, and it would be welcome by me. This is especially true for developers who really need to simulate a whole system on their pc. The whole system being a real physical plant plus the FPGA or ASIC design. If one uses a commerically avialable tool like Matlab, for example, when simulating systems across multiple time scales, i.e. from the nano-second, to micro, to milli, to second levels, the simulation just bogs down. Why not create a language or methodology whereby the HW accelerator could implement a physical system model perhaps by translating C or C++ to HDL? Or Matlab to HDL? The FPGA or ASIC design could reside in the main computer, and the physical system could reside in the FPGA HW accelerator board. I've had serious consideration of doing something like this in the past. My question to all is this: has anyone done it before? Kindest Regards, James johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0212231933.5472641c@posting.google.com>... > Since I brought up the Bio computing post, I have to wonder why there > isn't more interest in using FPGA accelerators to speed up some of the > EDA tools in a general way, ie given a std FPGA board, do a MMX SSE > like check for turbo HW. I know at DAC, you can find any no of > companies pushing HW accelerators but each seems very expensive and > thoroughly proprietory to a vendor and the particular tool they are > speeding up. I have seen Verilog simulation & ASIC emulation engines, > but I can't recall HW used to speed up anything else. If you use one > of those kits, the HW won't help any other task and it also comes in > another big box. > > My XMAS wish would be to see standardized FPGA HW available to the > power developer in a way that could be used for many tasks. It could > mean using say a HandelC flow for some things of less importance, but > for critical bottlenecks, a full blown C to HDL convert. I wouldn't > mind working on such a problem myself, last time I did an ASIC Place n > Route it took a week of cpu, you would think that engineers would want > such a solution. > > happy holidays > > JJArticle: 50964
Jeff wrote: > Hi, > The new ISE 5.1 webpack on Xilinx website requires Windows XP. The OS of my > PC is just Windows ME. Now I just want to be familiar with ISE. So, ISE 4.x > is enough for my use. Anyone knows where can I get ISE 4.x? It should run on win2k SP2: http://www.xilinx.com/ise/products/webpack_faq.htm#platforms http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack Hell will freeze over before i install XP.Article: 50965
--------------86E82422A2A3AF1FD7D16E5E Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Guys, I'm very interested in this topic, and I think the whole process is more complicated than it looks 1. The most important bottleneck is the simulation of the netlist (the design) not the behavioral model. The simulation time for a design is dependent on time resolution, complexity of the netlist (internal nets) and of course the total time (clock periods) 2. Another challenge is to conversion of stimuli from the test bench in "real life signals" (or in other words to cross the sw to haw domain) to achieve this are many methods like: -Make a synthesizeble test bench - Not so easy, and time consuming -Run a simulation with the test bench and the behavioral model only, capture the relevant signals in a VCD file (value change dump file) and than convert these VCD files in vectors (binaries) . You need to do this only once if you are not changing the the test bench and/or behavioral models -Another method is to capture the signals using PLI interface with the simulators 3. Now we need to apply these signals to our design (after MAP+PAR) and read back the results - not so easy as it seems especially if you need to make it quick (the clk speeds are modest around 5 Mhz but it's fast enough to speed up the process 10x at least) 4. Convert back the signals in software domain (reverse method form point 2) The simulation time (which can be called run-time in hardware) has nothing to do with the complexity of the netlist and is only a function of the length of the vector file (the stimuli file) what I'm trying to say here is : the time to run a FFT core or a "pipe of registers" (with the same latency of course) is exactly the same in hardware but in software simulation time is different Any comments? Aurash James Bonanno wrote: > John; > > I agree. I would like a HW accelerator tool, and it would be welcome > by me. This is especially true for developers who really need to > simulate a whole system on their pc. The whole system being a real > physical plant plus the FPGA or ASIC design. If one uses a > commerically avialable tool like Matlab, for example, when simulating > systems across multiple time scales, i.e. from the nano-second, to > micro, to milli, to second levels, the simulation just bogs down. Why > not create a language or methodology whereby the HW accelerator could > implement a physical system model perhaps by translating C or C++ to > HDL? Or Matlab to HDL? The FPGA or ASIC design could reside in the > main computer, and the physical system could reside in the FPGA HW > accelerator board. I've had serious consideration of doing something > like this in the past. My question to all is this: has anyone done it > before? > > Kindest Regards, > James > > johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0212231933.5472641c@posting.google.com>... > > Since I brought up the Bio computing post, I have to wonder why there > > isn't more interest in using FPGA accelerators to speed up some of the > > EDA tools in a general way, ie given a std FPGA board, do a MMX SSE > > like check for turbo HW. I know at DAC, you can find any no of > > companies pushing HW accelerators but each seems very expensive and > > thoroughly proprietory to a vendor and the particular tool they are > > speeding up. I have seen Verilog simulation & ASIC emulation engines, > > but I can't recall HW used to speed up anything else. If you use one > > of those kits, the HW won't help any other task and it also comes in > > another big box. > > > > My XMAS wish would be to see standardized FPGA HW available to the > > power developer in a way that could be used for many tasks. It could > > mean using say a HandelC flow for some things of less importance, but > > for critical bottlenecks, a full blown C to HDL convert. I wouldn't > > mind working on such a problem myself, last time I did an ASIC Place n > > Route it took a week of cpu, you would think that engineers would want > > such a solution. > > > > happy holidays > > > > JJ -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 50966
Hi, Slices are referred by their co-ordinates like X0Y0. and similarly BRAMs also having some co-ordinates. But How can i view the Location of the DCM in the Floor Planner? How it will be Located? Thanks in advance Best regards, MuthuArticle: 50967
> On a more serious note, broad knowledge of many areas on one discipline, > or even knowledge of more than one discipline is considered to be a mark > of a guru. I remain, humbly, a guru in training. > I've heard that people who can hop from one discipline to another could be considered "kan-gurus" RobArticle: 50968
--------------DD4AE0629E2A037B2617F80A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Charles, 1. Run impact program in gui mode -> Check "Prepare Configuration files" 2. Next dialog window -> check PROM file 3. Chose format (MCS in your case) and check Xilinx Serial PROM (and name of the file etc...) 4. Chose your PROM (18v04 in your case) and hit "Add" button 5.Hit next button 6. Add the files in the order of the chain (fpga1 + fpga2 .....) check the chain in the GUI 7. Generate the file Hope this helps Aurash cfk wrote: > I'm not usually this dense, but some advice would be appreciated. I just > upgraged my ISE software to the latest version and I can seem to figure out > how to split a prom anymore. In 4.2.03i, the option "Generate Programming > File -> Gnerate PROM File" lead to a program that had "Split Prom" on its > file menu. The new one in 5.1.03i leads to a "Wizard" that does not end up > splitting the prom. I have a design I have been working on with 3 18V04's > and the bit stream is split between the three (its an XCV2000 part). Perhaps > someone would be so kind as to do a step by step help note to get me back to > splitting proms again so I can actually use the new software. > > -- > Charles Krinke > http://home.pacbell.net/cfk > cfk@pacbell.net -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 50969
--------------EDBB7C1A5E999266F4975B46 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Errata: At point #4 add all your proms (hit add button 3 times) and chose only one file at point #6 Aurash Aurash Lazarut wrote: > Charles, > > 1. Run impact program in gui mode -> Check "Prepare Configuration > files" > 2. Next dialog window -> check PROM file > 3. Chose format (MCS in your case) and check Xilinx Serial PROM (and > name of the file etc...) > 4. Chose your PROM (18v04 in your case) and hit "Add" button > 5.Hit next button > 6. Add the files in the order of the chain (fpga1 + fpga2 .....) check > the chain in the GUI > 7. Generate the file > > Hope this helps > > Aurash > > > cfk wrote: > >> I'm not usually this dense, but some advice would be appreciated. I >> just >> upgraged my ISE software to the latest version and I can seem to >> figure out >> how to split a prom anymore. In 4.2.03i, the option "Generate >> Programming >> File -> Gnerate PROM File" lead to a program that had "Split Prom" >> on its >> file menu. The new one in 5.1.03i leads to a "Wizard" that does not >> end up >> splitting the prom. I have a design I have been working on with 3 >> 18V04's >> and the bit stream is split between the three (its an XCV2000 part). >> Perhaps >> someone would be so kind as to do a step by step help note to get me >> back to >> splitting proms again so I can actually use the new software. >> >> -- >> Charles Krinke >> http://home.pacbell.net/cfk >> cfk@pacbell.net > > -- > __ > / /\/\ Aurelian Lazarut > \ \ / System Verification Engineer > / / \ Xilinx Ireland > \_\/\/ > > phone: 353 01 4032639 > fax: 353 01 4640324 > > -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 50970
--------------D6A0388E6D0D009340581865 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Muthu, DCMs are located on the top and bottom of the bram column (on the IOB ring) if you stay with the mouse on these resources in graphical rep. of the die, you can see the coordinates (the same in fpga_editor) Hope this helps, Aurash Muthu wrote: > Hi, > > Slices are referred by their co-ordinates like X0Y0. and similarly > BRAMs also having some co-ordinates. But How can i view the Location > of the DCM in the Floor Planner? > > How it will be Located? > > Thanks in advance > > Best regards, > Muthu -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 50971
On Mon, 23 Dec 2002 17:32:37 -0500, Theron Hicks <hicksthe@egr.msu.edu> wrote: > > >rickman wrote: >Rick, > The situation is that the EMI is being generated in the cooling fans for the >unit itself. Thus the unit is effectively interfering with itself. I have tried >ferrite beads and capacitors to reduce the posibility of conducted EMI. The >chassis of the fan is aluminum so it prety much shields itself. However, I tried >to shield the fan with a screen on top of the fan between the boards and the fan. It sounds like the hotwire itself is a receiver antenna... though how do you distinguish between the acoustic interference from the fan, and the electrical interference? Older styles of fan with all-metal construction may provide better shielding for the motor. Or maybe it's time to look at a belt-driven fan. Or maybe this will help! http://users.moscow.com/oiseming/lc_ant_p/pic_Prj1.htm :-) - BrianArticle: 50972
Hi, What is the main differences between the variuos HSTL I/O technologies: HSTL-I HSTL-II HSTL-III HSTL-IV ? JohnArticle: 50973
--------------9240952D9AA61A8EB2761767 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit You can use a "Peltier" element (if you have a considerable power budget) Aurash Theron Hicks wrote: > Hello, > I have an EMI noise problem with a cooling fan on an FPGA based system. > As a result, I am considering using a thermostat to control my cooling fans > in my system. I would like to attach the thermostat directly to the worst > case element on the board. To do so I need to decide what the likely > maximum allowable case temperature is. I am using a Spartan2E > XC2S50E-7TQ144C. I believe that the part is dissipating about a watt > although I haven't measured this yet. When I look at XAPP415 I see that > they list a maximum Theta J-A of 57.6 C/W with a typical value of 33.5C/W. > They also list Theta J-C of 5.5 W/C (typical). The first question is, "What > are the assumtions about heatsinking through the ground plane in the PCB for > theta J/C ?" The second question is can I use the 5.5 number to calculate > the temperature setting for my thermostat? Thus the maximum junction > temperature is 85C and the part dissapates 1 watt for a J/C temperature rise > of 5.5C. Thus the temperature of the thermostat could be set at say 79.5C. > For safety, I could use a 65C thermostat. The intent of all this is to > allow the customer to run the part in a low noise condition if the > environment is cool enough, but yet protect the system from overheating. > > As I think about it turning the fan on will generate a nasty EMI glitch > that would corrupt the user's measurements. Perhaps, I should provide any > idiot light/beeper that would tell the user to turn on the fan. Still, how > do I make the determination as to what the allowable case temperature should > be. > > By the way, the system is a low noise pulse width modulated anemometer > which is intended to be used in the field (i.e. in the sun on the salt flats > in Utah.) > > Thanks, > Theron Hicks -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 50974
lebrase@yahoo.fr (Erwan) wrote in message news:<65edfa70.0212170408.1d1ad3d8@posting.google.com>... > Hi, > > working for a software MPEG company that want to provide now hardware > solutions as well, I would like to have your opinion about how > implementing this new configuration. We found that a DSP only solution > would not provide enough power. > Something like a board with DSP plus FPGA(s) should be better. > What is the process to go from evaluation to specification and then > implementation of such a system ? We already have source code and > technical knowledge in MPEG and DSP. > From your point of view, is hiring FPGA specialized engineer mandatory > ? I guess many of you would answer yes :) , but using consulting is an > option too, and eventually learning ourselves (?). > Is mixing C code (on DSP) and hardware optimized functions (on FPGA) a > good choice for speed ? (versus C only on DSP) > How long (man/month) should it take in this situation ? This is not > the case, but suppose that the encoder is MPEG-4 video with > DCT/IDCT/Motion Est/ and perhaps interpolation in FPGA. > And as a starting point what would you recommend ? > > thanks, > > Erwan Erwan, I think there are many different things you must consider before you can make a decision that will fit best your needs. Sure, I'm the business as well and would like to do the job. BUT, using an FPGA might be more expensive than adding another DSP. I know some of the 54 series TI DSP sell for less than $10. A low cost Spartan 2e FPGA, that can hold 200K "fpga gates" will cost about $30 plus the PROM. So if you already have one DSP in your system, it might be cheaper to add a second one and be done. You must decide which function you want to push off to the FPGA and what size FPGA you will really need. If you determine you need a larger FPGA you might be looking at several hundred dollars just for the FPGA. In respect to hiring/contracting the job out, it also depends on several things: Is it going to be a one time deal or will you be going in to the hardware business ? Doing hardware is more than the know how. Sure you'll are bright engineers and can learn how to write RTL code, but it takes a bit more than learning VHDL/Verilog to successfully bring up an FPGA. Also you must consider the investment of tools and equipment. It will be cheaper to contract the entire job out if you are doing a one-time deal. A professional company can do it much faster and much lower cost than you could do it at the beginning. If you are planning to continue doing small design, you will be better of long term, buying the tools and hiring somebody full-time to do the job and to train you. Check out some of the Free IP cores we are developing, some of them are for Motion Video ... Perhaps that a start if you want to do it yourself ! Hope this helps ! Best regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - NEW ! 3 New Free IP Cores this months (so far :*) FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----
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