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hello,
just upgrade from foundation 3.1 to 4.
i have a design which simulated perfectly on 3.1, now all the outputs
waveforms with 4.2 are greyed out!
The design is fully synchrnous
i am getting this error:
incomplete MNM specification.MAX assumed for undefined NOM value
checked the line in time-sim.edn, found such thing
(instance GSUH_t24_tW1
(viewRef view_1 (cellRef x_suh (libraryRef SIMPRIMS)))
(property SUINHICLK (miNoMax (mnm 4327 (undefined) 5358)) (unit TIME)
(owner "Xilinx"))
property SUINLOCLK (miNoMax (mnm 4327 (undefined) 5358)) (unit TIME)
(owner "Xilinx"))
)
any help please!!, i am absolutely stuck!
Article: 50901i have set an environment variable set Xil_anno_...=1 the previous error does not occur anymore, but still the waveforms are greyed!! design contain heavy busses is there any setting to do [i am under big time pressure] thanksArticle: 50902
Theron Hicks (Terry) wrote: > > Actually Glen, the device I am building _is_ a hot wire anemometer. The control > system is Pulse Width Modulated as opposed to the conventional Whetstone Bridge > based constant temperature anemometer. By using PWM we can get a better > transfer function and use a simple counter instead of an A/D converter. Also, > the system has a few other advantages. (See United States Patent #03603147.) > The real problem is that the fan ENI shows up in the Spectral Plot for the > recovered data from the anemometer. I would have expected the two to have different frequency bands - the FAN will be 100's of Hz, and the airflow sub-Hz ? > I am looking at several options including > grounding the fan cases, filtering their input lines, and shielding the fan > cases. I am currently using the best specified fans for EMI that I can find. Piezo fans maybe ? - not the same airflow, but quieter. Or, you could invest more in Copper/Aluminium, and try and eliminate the FANS, or move them into a 'shielded tunnel' ? > The fans are 119mm square by 35mm high (however height is somewhat > negotiable). I have even considered using a remote fan and ducting the coolant > flow into the system via some large diameter hose. > > Thanks, > Theron > > glen herrmannsfeldt wrote: > > > "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message > > news:au01e8$17oj$1@msunews.cl.msu.edu... > > > > (snip) > > > As I think about it turning the fan on will generate a nasty EMI > > glitch > > > that would corrupt the user's measurements. Perhaps, I should provide any > > > idiot light/beeper that would tell the user to turn on the fan. Still, > > how > > > do I make the determination as to what the allowable case temperature > > should > > > be. > > > > > > By the way, the system is a low noise pulse width modulated anemometer > > > which is intended to be used in the field (i.e. in the sun on the salt > > flats > > > in Utah.) > > > > How about a hot-wire anemometer? > > > > Do you have to worry about the effect of the fan on the > > anemometer itself? > > > > -- glen -- ======= 80x51 Tools & IP Specialists ========= = Want to work smarter than C ? = http://www.DesignTools.co.nz/modbench.htm = http://www.DesignTools.co.nzArticle: 50903
Your English isn't so good? OMG, thats an understatment but hey, I only 2 words in Japanese so you're doing pretty good! If I underatnd what you're asking is about what we call in America "environment variables" which aren't needed to run Max+Plus2 under 98. There's got to be a Altera rep in Japan. Regards "Toshihiro" <bear@minos.ocn.ne.jp> wrote in message news:<au3udf$9n$1@nn-os106.ocn.ad.jp>... > Hello, > > This is not FPGA's problem. but I couldn't discover at the CPLD(software). > so please tell for this group. > > now I think that altera's chip used to will make a small computer. > but I couldn't understand these plan what into will be used software, > max+plus2's setting up in the windows 98 second edition. I am > software's licensing setting is probably okey. but my computer's > global variable??(japanese call kankyo-hensu) isn't understood. > I don't know how to set up global variable. > I know about windows XP and 2000's setting up because my buying > magazine wrote. but windows 98 second edition and windows 98 > is not written this magazine. so please teach me global variable > in windows 98 second edition using and who altera's max+plus2 > using user you. please teach me setting up global variable...or > Would you teach me these informaiton knew user.....sorry > not well my english. > > Thank you very much. > > I would do my best. > Toshihiro YazawaArticle: 50904
Sometimes they're looking for nice credentials on paper because they're still trying to attract investment from people who couldn't judge a good engineer by any other means than the name of the school on the diploma, which is pretty funny because the correlation isn't all that high between a "top 5 school" and being a kick-ass designer. They'll figure it out eventually. Regards "Austin Franklin" <austin@da98rkroom.com> wrote in message news:<v0927ljbjg1815@corp.supernews.com>... > Hi Ray. > > Not even one of the best engineers I know are PhD's, and I've worked > with many many many exceptional engineers from the top engineering > companies. In fact, most of the best engineers I know don't even have a > masters, and probably half of them don't have a degree at all....as the > programs to do what they do weren't around when they were in school. > > Austin > > "Ray Andraka" <ray@andraka.com> wrote in message > news:3E03860B.DA2A741A@andraka.com... > Seems somewhat limiting, but then it is an employer's market more or > less. It would rule me out too, as well as the few people I know to be > very strong in both FPGAs and computer arithmetic/DSP. > > --Article: 50905
I remember seeing appnote on Xilinx's web page about running ISE and WebPack under Wine.. Petter Gustad wrote: > Russell <rjshaw@iprimus.com.au> writes: > >> I need a linux version of webpack with a gui >> that works. If it wasn't for spartan-II devices >> with distributed ram (SRL16) and some floorplanning >> ability, i'd be using altera now. > > The Qaurtus II Web Edition is not available for Linux. However, the > full version of Quartus II is. > > PetterArticle: 50906
Try to compile again with these 2 lines added to your defparam... lpm_ram_dp_component.use_eab = "ON", lpm_ram_dp_component.lpm_type = "LPM_RAM_DP"; lpm_ram_dp_component.rden_used = "TRUE", lpm_ram_dp_component.intended_device_family = "UNUSED", And remove this line: > lpm_ram_dp_component.lpm_hint = "USE_EAB=ON"; ____________ Brian Guralnick innerdimension@hotmail.com "Jamil" <jamilkhatib@haridy.com> wrote in message news:3156b636.0212220243.834ddd@posting.google.com... > Hi, > > I generated a verilog module of lpm_ram_dp using Quartus > megafunction wizard. > > module dpmem ( > data, > wraddress, > rdaddress, > wren, > rden, > wrclock, > rdclock, > q); > > input [31:0] data; > input [4:0] wraddress; > input [4:0] rdaddress; > input wren; > input rden; > input wrclock; > input rdclock; > output [31:0] q; > > wire [31:0] sub_wire0; > wire [31:0] q = sub_wire0[31:0]; > > lpm_ram_dp lpm_ram_dp_component ( > .rdclock (rdclock), > .wren (wren), > .wrclock (wrclock), > .rden (rden), > .data (data), > .rdaddress (rdaddress), > .wraddress (wraddress), > .q (sub_wire0)); > defparam > lpm_ram_dp_component.lpm_width = 32, > lpm_ram_dp_component.lpm_widthad = 5, > lpm_ram_dp_component.lpm_indata = "REGISTERED", > lpm_ram_dp_component.lpm_wraddress_control > = "REGISTERED", > lpm_ram_dp_component.lpm_rdaddress_control > = "REGISTERED", > lpm_ram_dp_component.lpm_outdata = "REGISTERED", > lpm_ram_dp_component.lpm_hint = "USE_EAB=ON"; > > > endmodule > > I am trying to synthesize it using altera Leonardo spectrum but I > get error message indicating that this module is not a defined > module or gate in a library knowing that I loaded Apex library from > Leonardo. > > This problem occured also when I try to make a instance of this > module in my design which is the most important for me. > > I tried it using VHDL and it went OK but I had to change the > instance name in the resulted EDF file to compile it in Quartus. > > do you have any suggestion to this problem? > > pls reply to my email (jamilkhatib@haridy.com) if it is possible > > Thanks in advance > Jamil KhatibArticle: 50907
pmxtow@merlot.uucp (Thomas Womack) wrote in message news:<at4pse$k8m$1@oyez.ccc.nottingham.ac.uk>... > > How do you interface widgets to a computer nowadays? Are there chips > which can convert USB or PCI to something easier to contemplate; is it > practical for a hobbyist to connect things to the PCI bus? > > Tom You might want to look into the FT8U245AM from FDTI (see http://www.beyondlogic.org/usb/ftdi.htm). It gives you fast data transfers over USB. Interface with the device is like a parallel FIFO. On the PC side, you can write to it like to a normal serial port. Regards, MarcArticle: 50908
Hi, The new ISE 5.1 webpack on Xilinx website requires Windows XP. The OS of my PC is just Windows ME. Now I just want to be familiar with ISE. So, ISE 4.x is enough for my use. Anyone knows where can I get ISE 4.x? ThanksArticle: 50909
Jamil, You should blackbox the instance of the memory generated using the Megawizard before synthesizing with Leonardo. This is described in detail in the Quartus II online help. Open the Online Help and search for "Black box". This will identify several articles. Select the one with the title "Creating & Instantiating a Verilog HDL Function for Use with the LeonardoSpectrum Software". This discusses the steps needed to blackbox a Megawizard generated function properly. Hope this helps. - Subroto Datta "Jamil" <jamilkhatib@haridy.com> wrote in message news:3156b636.0212220243.834ddd@posting.google.com... > Hi, > > I generated a verilog module of lpm_ram_dp using Quartus > megafunction wizard. > > module dpmem ( > data, > wraddress, > rdaddress, > wren, > rden, > wrclock, > rdclock, > q); > > input [31:0] data; > input [4:0] wraddress; > input [4:0] rdaddress; > input wren; > input rden; > input wrclock; > input rdclock; > output [31:0] q; > > wire [31:0] sub_wire0; > wire [31:0] q = sub_wire0[31:0]; > > lpm_ram_dp lpm_ram_dp_component ( > .rdclock (rdclock), > .wren (wren), > .wrclock (wrclock), > .rden (rden), > .data (data), > .rdaddress (rdaddress), > .wraddress (wraddress), > .q (sub_wire0)); > defparam > lpm_ram_dp_component.lpm_width = 32, > lpm_ram_dp_component.lpm_widthad = 5, > lpm_ram_dp_component.lpm_indata = "REGISTERED", > lpm_ram_dp_component.lpm_wraddress_control > = "REGISTERED", > lpm_ram_dp_component.lpm_rdaddress_control > = "REGISTERED", > lpm_ram_dp_component.lpm_outdata = "REGISTERED", > lpm_ram_dp_component.lpm_hint = "USE_EAB=ON"; > > > endmodule > > I am trying to synthesize it using altera Leonardo spectrum but I > get error message indicating that this module is not a defined > module or gate in a library knowing that I loaded Apex library from > Leonardo. > > This problem occured also when I try to make a instance of this > module in my design which is the most important for me. > > I tried it using VHDL and it went OK but I had to change the > instance name in the resulted EDF file to compile it in Quartus. > > do you have any suggestion to this problem? > > pls reply to my email (jamilkhatib@haridy.com) if it is possible > > Thanks in advance > Jamil KhatibArticle: 50910
What's a serdes, and do I need it?Article: 50913
I have found ISE 4.2 on Xilinx's website. Thanks. By the way, what requirements of ISE 4.2 for PC hardware and OS? I haven't found that on the web. Can you tell me? ThanksArticle: 50914
Hi all, I want to resample(at a lower rate,say 'y' Hz) an already sampled signal(at a higher rate, say 'x' Hz). I am not talking about "UPSAMPLING->FILERING->DOWNSAMPLING". I am talking about resampling by deriving clock 'y' from 'x'. Let me illustrate with an example. Say x=100MHz and y=43.3125MHz. Generate 43.3125MHz from 100MHz using an NCO and use this clock to get samples. Assume that clock 'x' to sample delay is more than clock 'x' to clock 'y' delay, by the setup time requirement for sampled signal w.r.t. clock 'y' (that is no problem in obtaining the current sample as current sample). My question is, will there be any problem with this method regarding spectrum of the resultatnt signal,SNR degradation etc. Also is it true that while the "UPSAMPLING->FILERING->DOWNSAMPLING" method only works for y/x = p/q, where p and q are integers, the above proposed method works for any ratio? P.S.: Could you tell me any existing practicle system which uses this method of resampling? regards, Nagaraj CSArticle: 50915
Sure why not? It is always possible to attempt anything. There are programs that will do distributed simulations... http://www.platform.com/PDFs/whitepapers/MUG_Oct2K1.pdf (this looks like the thing most people do) http://www.avery-design.com/web/simcluster.pdf DO a google search on distributed simulations modelsim Steve "Nachiket Kapre" <nachikap@yahoo.com> wrote in message news:eadce17c.0212220755.431fc33b@posting.google.com... > While simulating a complete ASIC (~5 million gates) consisting of > several individual blocks, is it possible to attempt a concurrent > simulation (functional or timing) in a distributed environment with a > pool of dedicated PCs simulating the individual blocks with > inter-block communication handled by PLI/FLI wrappers in Modelsim > which take care of "forcing" the signals driven by other blocks into > this block? Each individual PC needs to load only a small part of the > whole design and wait for new updates from interacting blocks. Pakcets > keep travelling to and fro between the PCs progressing the simulation. > It may also be possible to avoid IDLE time by allowing the individual > PCs to assume a certain set of inpout values and start simulating, if > later an update arrives that invalidates this assumption, all > subsequent operatins are rerun with these new inoouts and the > corresponding outputs generated invalidated. This will definitely > require mor thinking than can fit in a single email, but how is the > idea for starters?...and has it been tried before ? > It would'nt be wrong to mention that attempting such a simulation on a > single PC would be too tedious and time consuming. > > regards, > Nachiket Kapre. > Design Engineer. > Paxonet Communication Inc.Article: 50916
Article: 50917
"Jay" <kayrock66@yahoo.com> schrieb im Newsbeitrag news:d049f91b.0212221545.406ce726@posting.google.com... > Sometimes they're looking for nice credentials on paper because > they're still trying to attract investment from people who couldn't > judge a good engineer by any other means than the name of the school > on the diploma, which is pretty funny because the correlation isn't > all that high between a "top 5 school" and being a kick-ass designer. > They'll figure it out eventually. ;-)))) A brother in mind. -- MfG FalkArticle: 50919
serdes is short for Serializer-Deserializer (like modem is
short for modulator-demodulator). If you have to ask what
it is, you probably don't need it, at least not now. It is
used for high speed serial communication between chips or
systems.
FPGA wrote:
> What's a serdes, and do I need it?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 50921I'm tired of defining pin numbers in a gui. Is there a way to import a text file (cvs) for the pin definition in quartus? When I used Max+Plus I closed the projet, opened the relevant .acf file and copied the pin definitions in. Is this possible in Quartus? Have not found the relevant file till now. A little bit off topic, but for the next step: Is it possible to generate some kind of library definition for a PCB tool (again with pin definition of signals and VCC, VCCINT, GND,...) MartinArticle: 50922
valentin tihomirov wrote: <nothing> You can use an oscillator (HCMOS) as clock. If speed is not critical I use the same for the microcontroller and the FPGA. Otherwise use a standalone Oscillator. They usually are in a DIP14 or DIP8 and are available from 1 to 80 or so MHz. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 50923
FPGA wrote: > What's a serdes, and do I need it? > > Hi FPGA (!?), Look up TexasInstruments http://www.ti.com and search for SERDES. The have chipsets serializing 16 or 32 bits parallel to 2.5GBit and back again to 16 or 32 bit parallel. It is thought to simplify backplanes. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 50924
Hal Murray wrote: > > They also had > >obsessive demands for privacy. They would not allow anyone to enter the > >building unless they signed the visitors log which was a small > >non-disclosure agreement. Very odd. > > Not uncommon where serious patents are involved. > > They are worried about some little guy suing them for > stealing his ideas, claiming he told them about something > critical when he visited. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. I understand what you are saying, but this would not protect them from that. This protects them from someone revealing any information they may have gotten while visiting. I don't think you can get any protection for a patent since anyone claiming that you stole their idea would have to prove that they *had* an idea prior to the visit and prior to any of your proof of your idea. They are just plain paranoid about a visitor getting any little glimmer of information on a trade secret since this is the only thing protected by a non-disclosure agreement. Instead of taking responsibility to not disclose trade secrets, they put the onus on visitors to not talk about *anything* revealed during the visit. Since a visitor would not know what was secret and what was not secret, it would make it hard to be able to discuss anything from the visit. Absurd. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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