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I am new to this group. I am doing Master Degree in VLSI in college of Engg Guindy , Anna Univ Chennai. Now currently I am facing a doubt in configuring Xilinx FPGA for space application.I am doing project in Xilinx FPGA. How configuration is done in Xilinx FPGA? If configuration logic is stored in SRAM how SRAM is booted while the power is ON? If the SRAM is active by using OTP (One time PROM) while the power is ON then my question is if any Single Event Upset or Latchup happened in OTP what is the remedy for it in Xilinx rad hard OTP configuration? Is it possible for me to configure the CLB and routing wires only by OTP without SRAM? Because for space application I am not going to reconfigure the FPGA. I have studied the SEU and SET and SEL in SRAM and how it can be rectified.But I am not having a solution for OTP configuration.Is there any technique to make OTP configured Xinix FPGA rad hard? Kindly tell me. Bye Thanx for advance. S.Thiruppathirajan.Article: 50576
sthiruppathirajan wrote: <snip> > Is there any technique to make OTP configured Xinix FPGA > rad hard? > Kindly tell me. If you do not need to reconfigure the FPGA in flight then you should use a rad-hard anti-fuse (one time programmable) FPGA. Using an OTP ROM to configure an SRAM-based FPGA (as you propose) seems like overkill, and opens up potential for new failures. The HPC reconfigurable logic payload (launching tomorrow on FedSat from Tanegashima!) uses a different approach - configurations are stored in error corrected Flash, and uploaded to a xilinx rad-hard SRAM FPGA under control of a space-qual microprocessor, via an Actel antifuse FPGA (sounds complex doesn't it?!). This allows on-orbit reconfiguration with uplinked bitstreams. More details if you are interested: http://www.xilinx.com/appnotes/AIMpaper.pdf Separate to this discussion there are methods you can use to reduce the impact of SEUs - ie triple mode redundancy, voting etc etc. Regards, JohnArticle: 50577
Hi, I am using XC95144XL in my design.Now,I configured a pin as input port,but in fact I use this pin as a floating one.In the scenario,I think the buskeeper will insure I can get a working-well logic '1' signal. Could anybody in the group tell me whether I am true or not? Thanks. Regards, wosiqiuArticle: 50578
Hi, I am using the XC95144XL in my design.Now,I configure a pin as input,but in fact I make it floated externally.I think its bus keeper will insure I can get a working-well logic '1' signal. Can anybody tell me whether I am true or not?Thanks. Regards, wosiqiuArticle: 50579
Hi,
Thank you for the reply. I also calculated for MTBF with XAPP094
and 4000 series device. But I wanted it for Virtex-E. As you have
mentioned i assume that whatever MTBF I calculate for XC4000 series
will be less than for that for newer device like Virtex-E.
I have one more question. What do you mean by "allowing 1 ns of
slack time" ?
This slack time part i am not clear for my design. Could you give some
detailed information about knowing alloable slack time for my design?
Regards,
Nagaraj
Peter Alfke <peter@xilinx.com> wrote in message news:<3DF8CB3B.E96CBE23@xilinx.com>...
> The MTBF depends on device type, clock rate, data rate, but also very
> much on the available slack time between the output of the synchronizing
> flip-flop ( which inevitably will go metastable) and the logic that it
> drives.
> At 80 MHz clock rate I assume you might be able to afford 2 extra ns of
> metastable delay.
>
> Now you can use the table in XAPP094. It is based on older technology,
> so the answer will be overly pessimistic (conservative = short MTBF).
> For an extra 2 ns with XC4005, the MTBF for 10 MHz/1 MHz is > 10 million
> years.
> Since you use an 8 times higher clock rate the MTBF would be 8 times
> shorter, but since you use only 8 kHz instead of 1 MHz, the MTBF would
> be 125 times longer.
> So you get an MTBF of 15 times 10 million years = 150 million years.
> Might be long enough...
>
> But if you allow for only one ns of slack, the MTBF will be less than a
> year !
>
> Peter Alfke, Xilinx Applications
>
>
> Nagaraj wrote:
>
> > Hi,
> > I have an asynchronous input to a synchronous system. I want to
> > calculate MTBF for a simple synchronizer(using only one synchonizing
> > FF).
> > Details are here below.
> > 1.Device Virtex-E, -8 speed grade, CLB flip-flops used
> > 2.Asynchronous input rate = 8KHz
> > 3.Clock frequency = 80MHz
> >
> > Could anybody in the group help me in finding out the MTBF?
> >
> > Regards,
> > Nagaraj
Article: 50580In article <b053419c.0212122238.7d8c7232@posting.google.com>, qiu.xiaoyong@zte.com.cn says... > Hi, > I am using XC95144XL in my design.Now,I configured a pin as input > port,but in fact I use this pin as a floating one.In the scenario,I > think the buskeeper will insure I can get a working-well logic '1' > signal. Could anybody in the group tell me whether I am true or not? > Thanks. > Regards, > wosiqiu > A buskeepers will held the last state, this can be either '1' or '0', you can not grant a defined state. You need a pullup resistor, but although they are present in the XC9500XL they are not accessible. The only solution is to use a external pullup. -- Klaus Falser Durst Phototechnik AG kfalser@IHATESPAMdurst.itArticle: 50581
Rudolf Usselmann <russelmann@hotmail.com> wrote: : Hmm, Even if you can generate a shorter bit stream that will be : sufficient for your implementation, the FPGA will try to read the : entire 1.3 mil. bits. So I wonder what will the 18V01 return above : the first 1 mil. bits ? Will it wrap around and deliver the original : bit stream again, or will it return garbage or will it return some : other pattern ? As the boards are in production now, and have forseen a SO20 package not available for the XC18V02, this probably needs a sandwich and some yellow wires. Argh! Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50582
"Saurabh Pal" <saupal@indiatimes.com> wrote in message news:62ef09ee.0212120101.12969041@posting.google.com... > Hi, > > Following is a Handel-C program which reads a 128-bit data, > copies the data to a buffer and, finally, the buffer contents are > given to the output pins. > > The data input/output interface is 32-bit unidirectional. > > After implementing the given design on a Xilinx Virtex-II FPGA, > I'm getting a clock speed of 126.374MHz. > > How can a better clock speed can be achieved? > > Any assistance appreciated. <snippped code> Firstly, try and track down where the problem is. You can get DK1.1 to give you delay and area estimates by going to Project -> Settings -> Linker and tick the "generate estimation info" box. You might also want to experiment with getting DK1.1 to do mapping by ticking "use technology mapper". You then target EDIF, and DK1.1 will put an HTML report in the EDIF sub-directory of the project which contains the details of timing and area. This cross-references to the lines of code, and shows you exactly where the longest path is. This should then help you to concentrate on the correct area. My guess is that by using arrays, you are generating complex addressing logic; so if you can re-write your algorithm to use block ram (where the addressing logic is built-in for you by Xilinx) you should get better results. Another thing to do is to see if you can pipeline your design by overlapping part of the calculations. This depends on the algorithm, and whether you can accept a number of clock cycles delay in your code. regards Alan -- Alan Fitch [HDL Consultant] DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 50583
"Muthu" <muthu_nano@yahoo.co.in> wrote in message news:28c66cd3.0212122042.3a03f484@posting.google.com... > Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3DF8A4F3.C042BA5C@xilinx.com>... > > Muthu, > > > > When using RLOC_ORIGIN, make sure you're appending it to comp that has > > RLOC of X0Y0 since RLOC values accumulates. > > > > How to find which component is Located in X0Y0. I searched the .ncf > file, none of the elements are placed in that Location. <snip> There's an article at http://www.xilinx.com/support/techxclusives/RPMs-techX30.htm which might help, regards Alan -- Alan Fitch [HDL Consultant] DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 50584
Alan Fitch <alan.fitch@doulos.com> wrote: ... : This e-mail and any attachments are confidential and Doulos Ltd. : reserves : all rights of privilege in respect thereof. It is intended for : the use of : the addressee only. If you are not the intended recipient please : delete it : from your system, any use, disclosure, or copying of this : document is : unauthorised. The contents of this message may contain personal : views which : are not the views of Doulos Ltd., unless specifically stated. What a strange disclaimer for a news posting ... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50585
Martin Schoeberl wrote: > Jim Granville wrote > > Did you ever compare the .NET byte code, or consider a .NET FPGA engine > > ? > > Have not tried it. I think it's just a copy of the JVM idea for the Win32 > world. The most important thing about .NET are the libraries. But you don't > need them in embedded systems. > > Martin > -- > JOP - a Java Optimized Processor for FPGAs. > http://www.jopdesign.com You could be interested in the work at http://www.citi.qut.edu.au/research/plas/projects/cp_files/ComponentPascal.html and http://www.citi.qut.edu.au/research/plas/projects/cp_files/cpnet.html This is a compiler to either .JVM , or .NET, and the .NET versions can create ilasm, or a program executable file. Thus you could compare ilasm -> FPGA, JVM -> FPGA, and P4 .EXEs, using the same source codes. Further out in left field is this work http://research.microsoft.com/foundations/AsmL/doc/StartHere.html which also compiles to .NET, and could form the basis of compile to HDL/FPGA synthesis. - jgArticle: 50586
> Hmm, Even if you can generate a shorter bit stream that will be > sufficient for your implementation, the FPGA will try to read the > entire 1.3 mil. bits. So I wonder what will the 18V01 return above > the first 1 mil. bits ? Will it wrap around and deliver the original > bit stream again, or will it return garbage or will it return some > other pattern ? No, that is not correct. There is _no_ set count for the Virtex devices. Xilinx devices have a generic programmable engine that gets loaded with packets that contins commands and data. You have to give the device the correct frame sizes and word counts. If you put the correct start up packets at the end of the difference of your design and a blank the part should load and drive done high. SteveArticle: 50587
Hi all I am new to this group. I am doing Master Degree in VLSI in college of Engg Guindy , Anna Univ Chennai. Now currently I am facing a doubt in configuring Xilinx FPGA for space application.I am doing project in Xilinx FPGA. How configuration is done in Xilinx FPGA? If configuration logic is stored in SRAM how SRAM is booted while the power is ON? If the SRAM is active by using OTP (One time PROM) while the power is ON then my question is if any Single Event Upset or Latchup happened in OTP what is the remedy for it in Xilinx rad hard OTP configuration? Is it possible for me to configure the CLB and routing wires only by OTP without SRAM? Because for space application I am not going to reconfigure the FPGA. I have studied the SEU and SET and SEL in SRAM and how it can be rectified.But I am not having a solution for OTP configuration.Is there any technique to make OTP configured Xinix FPGA rad hard? Kindly tell me. Bye Thanx for advance. S.Thiruppathirajan.Article: 50588
Hi- I use 16 bits of memory (16X1, 16 deep, 1 wide) and 80 nos for different instances. kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0212121903.6bba1d63@posting.google.com>... > First, what are your 80 16X1 rams used for, and in what configuration > (e.g. 80 wide by 16 deep, etc..) > > fpga_wonderkid@yahoo.com (FPGA Wonderkid) wrote in message news:<23069c63.0212120205.478a78c@posting.google.com>... > > Hi, I am planning to use an Altera Cyclone/ACEX device in place of my > > existing XC2S200E device. However, as I use lot of distributed RAM, I > > cannot easily go to Cyclone/ACEX as they do not support distributed > > RAM like Xilinx. Can anyone tell me how to efficiently convert the > > spartan-2e distributed RAM primitives into Cyclone/ACEX block ram > > architecture. What i need to know is how to convert 80 nos of 16X1 > > RAM, I have implemented in spartan-2e to cyclone architecture w/o > > consuming too much space. > > > > > > Thanks!Article: 50589
Thanx for reply. What will happen if OTP ROM faced SEU or SEL? IS Xilinx OTP made of antifuse or MOS technique? waiting for reply. S.Thiruppathirajan sthiruppathirajan@yahoo.com (sthiruppathirajan) wrote in message news:<5253b962.0212122121.2dfc4928@posting.google.com>... > I am new to this group. > I am doing Master Degree in VLSI in college of Engg Guindy , Anna Univ > Chennai. > Now currently I am facing a doubt in configuring Xilinx FPGA for space > application.I am doing project in Xilinx FPGA. > How configuration is done in Xilinx FPGA? If configuration logic is > stored in SRAM how SRAM is booted while the power is ON? If the SRAM > is active by using OTP (One time PROM) while the power is ON then my > question is if any Single Event Upset or Latchup happened in OTP what > is the remedy for it in Xilinx rad hard OTP configuration? Is it > possible for me to configure the CLB and routing wires only by OTP > without SRAM? Because for space application I am not going to > reconfigure the FPGA. I have studied the SEU and SET and SEL in SRAM > and how it can be rectified.But I am not having a solution for OTP > configuration.Is there any technique to make OTP configured Xinix FPGA > rad hard? > Kindly tell me. > Bye > Thanx for advance. > S.Thiruppathirajan.Article: 50591
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> ha scritto nel messaggio news:mV1K9.10145$ab2.280679@news1.tin.it... > Thank you, I'll try. In the meanwhile I've found a way > that works, but I > don't fully understand how: :-) I lied, it doesn't work. :( I tried in several ways (schematic, VHDL, state machines), but when the two clock edge overlap, I always get a FF setup violation and soon the simulation gets lost. I think this is unavoidable when you have to do with asynchronous signals. Or it isn't? May I assume that this isn't a big issue? In the reality a FF setup violation simply means that the FF output can change or not, but in this specific case this isn't a problem (it's enough that the signal gets sampled the next clock cycle). I have some other similar designs where I sample asynchronous signals with the "main" clock; in those cases I didn't noticed the problem with the simulator because the signals were slower, but I haven't had any problem with the physical implementation. P.S. Books are arriving. :) -- LorenzoArticle: 50592
http://www.xilinx.com/products/military/radhardv.htm This should get you started, especially the SEU paper. Xilinx's FPGA's have their configuration stored in an external PROM, probably OTP. To summarize, suggested solutions involve Triple mode redundancy, and CRC checking the bitstream using periodic repeated reconfiguration. One thing to watch out for, though, is current surges during reconfiguration/power up. Definitely an issue in a space design. I believe one workaround to the powerup problem was ramping up the various supply voltages slowly. (e.g. QPRO part minimum powerup current is 2A if you follow their ramping guidlines, more if you don't. ref: AnswerBowser record 13899) You might also want to check out ACTEL (www.actel.com) their device seem to lag behind xilinx's in most ways, with some notable exceptions. 1) I though their quadrent clocks were a nifty idea 2) Everybody uses them for space-- they're on a ton of programs already, I believe xilinx is pretty new to the field the drawback is that you'll have to pawn a limb to get them, they're expensive as all get out. --Josh Model MIT Lincoln Laboratory "sthiruppathirajan" <sthiruppathirajan@yahoo.com> wrote in message news:5253b962.0212130157.6d6f5bc5@posting.google.com... > Hi all > I am new to this group. > I am doing Master Degree in VLSI in college of Engg Guindy , Anna Univ > Chennai. > Now currently I am facing a doubt in configuring Xilinx FPGA for space > application.I am doing project in Xilinx FPGA. > How configuration is done in Xilinx FPGA? If configuration logic is > stored in SRAM how SRAM is booted while the power is ON? If the SRAM > is active by using OTP (One time PROM) while the power is ON then my > question is if any Single Event Upset or Latchup happened in OTP what > is the remedy for it in Xilinx rad hard OTP configuration? Is it > possible for me to configure the CLB and routing wires only by OTP > without SRAM? Because for space application I am not going to > reconfigure the FPGA. I have studied the SEU and SET and SEL in SRAM > and how it can be rectified.But I am not having a solution for OTP > configuration.Is there any technique to make OTP configured Xinix FPGA > rad hard? > Kindly tell me. > Bye > Thanx for advance. > S.Thiruppathirajan.Article: 50593
"Austin Franklin" <austin@da98rkroom.com> wrote in message news:<uvf6jceb5nh8b5@corp.supernews.com>... > Hi Hal, > > > The PCI connector has power pins for 5V, and 3.3V, and also a > > few more pins for IO power. > > No, there is no guarantee you will get 3.3V power, unless you are in a 3.3V > slot! My understanding is that a PCI 2.2 compliant motherboard is guaranteed to have 3.3V and 5V power available on the connector. With PCI 2.1 or older, all bets are off. Wayne [snip] > AustinArticle: 50594
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> ha scritto nel messaggio news:P6lK9.13754$ab2.391568@news1.tin.it... > clock edge overlap, I always get a FF setup violation and > soon the > simulation gets lost. I think this is unavoidable when you > have to do with > asynchronous signals. Or it isn't? [...] Looks like I'm entering in the painful world of metastabilities. I've read some technical documentats but, as far as I've undestood, the only true answer could be given by the test of the "real" circuit. However it should be very useful to have some idea of what will be the magnitude of problems I'm going to have. Just a couple of questions (I hope they are less trivial than the last ones): -In the Xilinx site I've found an interesting document (xapp094, "Metastable recovery") which gives a statistical distribution of metastabilities' duration for XC3000 and XC4000 family. Is there something similar for modern FPGAs (for example I use a XC2S50-5)? Can I suppose they are equal or better than XC4000? In my application I have an accettable extra delay of roughly 4-5 ns, which gives very different MTBF between the various models. -Is there a way to instruct ModelSim to simulate the metastabilities, i.e. to set the extimated maximum metastability duration as a parameter so that it will mark the signals as undefined only when really needed? -Is there a way to define some constraints that take account of this problem? I suppose it should be enough to impose a longer clock-to-setup time for the "critical" flip-flops, but I don't know how to do it. -- LorenzoArticle: 50595
Hi!
I started writing a FPGA core for a given harware layout that includes a
Xilinx XC5204 using vhdl . And I have some questions
What are the meaning of the signals in the startup component?
What are Q2, Q3 and Q1Q4?
I know that GR ist intended to connect a signal to the global reset net, but
I can't find information about the other signals.
And if I don't have an external RST signal but want to write Code like this
in the toplevel:
component pwm8 is
port (
rst: in STD_LOGIC;
CLK: in STD_LOGIC;
Value: in STD_LOGIC_VECTOR(3 downto 0);
PClk: out STD_LOGIC;
PulseOut: out STD_LOGIC
);
end component;
...
pwm1: pwm8 port map( RST=>Rst, Clk =>MyClk, Value =>B_STM_Reg1, PulseOut
=>sig_pwm);
PWM8.vhd:
entity pwm8 is
port (
rst: in STD_LOGIC;
CLK: in STD_LOGIC;
Value: in STD_LOGIC_VECTOR(3 downto 0);
PulseOut: out STD_LOGIC
);
end pwm8;
....
process(CLK,rst)
begin
if(rst='1') then SigPulse<='0';
Counter<="0000";
elsif (CLK'event and CLK='1') then
...
end if;
end process;
How do I get the (global ) RST signal?
Thanks
Dirk Dörr
Article: 50596Muthu, Floorplanner writes out RLOC constraints according to the placement in the floorplan view. Therefore, if the RPM that you wish to write doesn't have any component placed at SLICE X0Y0, then you'll not find it in the UCF. What you may want to do is either. 1. When doing RLOC_ORIGIN, take into account of the RLOC offset. 2. Prior to RPM2NCF, make sure your lower left corner component lined up to SLICE X0Y0 in Floorplanner. Regards, Wei Muthu wrote: > Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3DF8A4F3.C042BA5C@xilinx.com>... > > Muthu, > > > > When using RLOC_ORIGIN, make sure you're appending it to comp that has > > RLOC of X0Y0 since RLOC values accumulates. > > > > How to find which component is Located in X0Y0. I searched the .ncf > file, none of the elements are placed in that Location. > > > ex. RLOC_ORGIN at slice_x10Y10 on comp that has RLOC of X5Y5 will result > > in the comp be loc-ed at X15Y15. > > > > So when you're trying to Loc down the RPM, make sure the accumulated > > RLOC_ORIGIN value isn't pushing part of your RPM out of the device slice > > boundary. > > > > As for BRAMs, MULTs, Floorplanner's RPM creation will leave them > > unconstrained. You can either manually create another RPM for the > > BRAM/MULTs, or go over XAPP416 on the exact detail of using it. > > Basically, user has to read teh RPM_GRID coordinate from FPGA Editor and > > manually append the RPM_GRID coordinate value to the RPM. > > > > Note that Floorplanner doesn't fully support RPM_GRID yet. > > > > Regards, WeiArticle: 50597
Most readers of this group will have their copy of the 1988 Xilinx "Programmable Gate Array Data Book" :-) This is the edition which has neither the year number nor "First Edition" on the spine. An application brief by Brad Fawcett (hello, Brad) on page 6-51 of that book is for a "Logic Analyzer/In-Circuit Emulator", and Brad's suggestion has been implemented many times in the intervening 15 years. Now there is yet another implementation of the Logic Analyzer part, with some extra stuff added. You can check out www.rockylogic.com for the Ant8 - a 500MSample/s USB-connected (USB-powered) Logic Analyzer. By the erudite standards of the group, the Ant8 is nothing to get excited about. The hardest part was cooking up a flexible state machine implementation which allows for a range of fancy triggering modes. And it turns out that just about everyone is only interested in triggering on a single rising edge. Sigh. The rest of the development was just engineering, and it is well known that any fool can do that ;-) Pls hit me here with any technical questions of general interest - I promise to keep away from product pitches. Thanks TimArticle: 50598
I think Quartus II automatically assigns clk to a global clock pin. In any case I went ahead and set it to a global signal. But that didn't seem to help. Prashant Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3DF92E69.7070301@flukenetworks.com>... > Prashant wrote: > > > I appreciate your response and that definitely helps my understanding. > > I was under the impression that the wire delays were estimated > > accurately in the synthesis process, but I guess not. > > > "Wire" delays in fpgas are very sensitive to place and route > because the switch elements and parts of the path itself > are silicon rather than aluminum. > > Consider using one of the global clock pins > to rule out hold violations. > > -- Mike TreselerArticle: 50599
Tim wrote: > Now there is yet another implementation of the Logic Analyzer > part, with some extra stuff added. You can check out > www.rockylogic.com for the Ant8 - a 500MSample/s USB-connected > (USB-powered) Logic Analyzer. I don't suppose there is any sort of Linux support for this device? -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
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