Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, I am trying to port a Nios-32 system on the SOPC Development board with the Apex "EP20k1500EBC652-1X" chip. I am using the simple UART core provided in Altera's Nios Development Kit to interface with the RS-232 DTE interface provided on the board. But I can't get it to work. Does anybody have a solution to this problem? thanks in advance. regards, SatchitArticle: 51427
2Penny wrote: > Gentlement: > > I've built a small computer board I've made for a small college here. > I'd like to simplify the design by putting the glue logic into an > fpga, but I know nothing about fpgas. I think I can ask the college > to spring for the software if it isn't too much, but how do I download > this to the chip. I do this fairly regularly with ABEL and PLDs, but > I think I should update my skills, but I don't know where to turn. > I'm looking for clues. Please point me in the right direction. > > TIA > > 2Penny Why not use the same Xilinx Webpack tools that support Abel for CPLD design to design a Spartan? Of course, I'm biased ;-) -Dennis McCrohan Xilinx CPLD S/WArticle: 51428
"tk" <tokwok@hotmail.com> schrieb im Newsbeitrag news:avsfjl$5jb$1@www.csis.hku.hk... > thx Falk > > the PC_INIT is a reset signal > I don't quite understand problem 1, could you elaborate more ? The FPGA has its own clock source, the PC has its own clock source. SO there are two systems with unrelated clocks talking to each other. So there is NO guarantee when a signal from the PC will change in relation to your FPGA clock. This can (no, WILL!!!!) mess up the state machine. If the FSM (finite state machine) uses a one-hot encoding, you have a 100% chance to freeze it, as you have noticed. So when you synchronize the signals comming from your PC using two FlipFlops, it will be practically safe. I say practically, because there is a pure mathematical chance that the bad asynchrounus signal get through the synchronizer, but the probability is somewhere in 1 out of milliards of years. Have a look on the xapps on the xilinx website, there are some that discuss this problem (metastability). The main problem is that, if one asynchronous signal from the PC goes to more than one FlipFlop in FSM, tha ich can (WILL!!!) happen, that it changes just a fraction of a ns before the FPGA clock arrives. And since the delay from the IO cell to the two FlipFlops are never identical, one FlipFLop will see a LOW, the other a HIGH. Depending on the state encoding, this will cause a jump into a wrong state or total mess up (freezing). Regards FalkArticle: 51429
nagaraj_c_s@yahoo.com (Nagaraj) wrote in message news:<91710219.0301130254.a53508d@posting.google.com>... > Hi, > I have my design in FPGA. I wish to migrate to a customized ASIC. > Could anybody tell me some sites/companies which do this? They should > give information about time taken/cost involved etc. > > regards, > Nagaraj CS AMI, Lightspeed?, Altera?, maybe others used/still do straight conversions of FPGAs. Don't know if they can handle all the special modern features like blockrams, serdes, multipliers, fancy IOs etc. If you own all the IP blocks in your design & the HDL was written with ASICs in mind, you could just take the HDL & retarget to ASIC process. Having FPGAed the design, the foundries will usually have a faster sign off procedure since most of the risks have been worked out. Also any no of ASIC design centere will do the conversion project for you for $$$$$. google asic fpga conversionsArticle: 51430
Here you go, AMI Semiconductor: http://www.amis.com Flextronics Semiconductor: http://www.flextronicssemi.com Lightspeed Semiconductor: http://www.lightspeed.com Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.) Nagaraj wrote: > > Hi, > I have my design in FPGA. I wish to migrate to a customized ASIC. > Could anybody tell me some sites/companies which do this? They should > give information about time taken/cost involved etc. > > regards, > Nagaraj CSArticle: 51431
Steve Casselman wrote: > The 302 patent doesn't stop Altera or Triscend or others. Xilinx gives all > the data to reverse engineer the bitstream. It is not very well documented > however. Look at the xdl command. Does the xdl command give the data to reverse engineer the bitstream or is this in some datasheet somewhere on the Xilinx website? I have had a quick look at the website but could not find anything relating to the bitstream. Presumably any data on reverse enginneering could be used for forward engineering. > You could write a program that translates > the xdl output into and out of the U of Toronto place and route tool. You > could take JBits and write a program to figure out the V1 bitstream. I think > it would take a small group of programmers (5-10) a year or so but it is > possible. I thought I had JBits and the source until I discovered that I actually had jbittools which uses JBits. I am now waiting to see if Xilinx will honour my request for the JBits SDK. Thanks Andrew RogersArticle: 51432
I forgot to add Chip Express (http://www.chipexpress.com/) and LSI Logic to the list. I hope you are not using IP cores from an FPGA vendor because most FPGA vendors legally prohibit you from doing that (Since they sell the IP cores very cheap, they need to recover the investment in IP cores by selling you the chips.). Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.) Kevin Brace wrote: > > Here you go, > > AMI Semiconductor: http://www.amis.com > Flextronics Semiconductor: http://www.flextronicssemi.com > Lightspeed Semiconductor: http://www.lightspeed.com > > Kevin Brace (If someone wants to respond to what I wrote, I prefer if > you will do so within the newsgroup.) >Article: 51433
you need to include the library and use clauses to invoke the unisim library.
Jim Raynor wrote:
> hi,
>
> I am having problem in simulating the Virtex's Primitive (e.g CLKDLL,
> BUFG...) using Modelsim. Could anyone tell me how to do it? I got errors
> in the Modelsim like
>
> # WARNING[1]: main.vhd(244): No default binding for component: "ibufg".
> (No entity named "ibufg" was found)
> # WARNING[1]: main.vhd(247): No default binding for component: "clkdll". (No
> entity named "clkdll" was found)
> # WARNING[1]: main.vhd(248): No default binding for component: "bufg". (No
> entity named "bufg" was found)
>
> Thanks.....
>
> Chris
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 51434"David" <gretzteam@hotmail.com> wrote in message news:<WNlU9.9442$sn2.131167@wagner.videotron.net>... > Hi > I'm having a hard time figuring out how to implement the coefficient > multiplication in a vhdl dsp design. Let's say every registers are 16 bits > wide in two's complement representation and suppose there are no overflow. > The input data is normalised betwen -1 and 1. How can I implement the > following block diagram in vhdl? How is the *0.1 implemented...I'm really > lost here thanks for any help. > > > x(n)-------------- * 0.1----------- +---------- y(n) > | | > | | > |______z^-1_________| > > > David well in proto verilog it might look just like the drawing, wire [15:0] xn,xn_1,yn; dff z0 (CK,Clr, xn,xn_1); assign yn = xn_1 + xn*0.1; now change the 0.1 to a hex const 0cc.. ie 07ff../0a the multiplier can often be replaced by balanced tree of additions of the shifted input i*k is equiv to (((i>>k0) + (i>>k1)) + ((i>>k2) + (i>>k3))) ..... depending on precision & technically >>n is not exactly / 2^n either for signed nos in an asic, the additions would go into a csa array, but since fpgas use ripple adders group the terms into a balanced tree ((..)+(..)) + .. with the wider additions closer to the top if possible. if the konst has too many terms, you may well be better off using a proper * just for starters JJArticle: 51435
Ray,
Thanks for the response. Could you tell me where to download the
library?
Thanks again
Chris
"Ray Andraka" <ray@andraka.com> wrote in message
news:3E231694.F2763AE6@andraka.com...
> you need to include the library and use clauses to invoke the unisim
library.
>
> Jim Raynor wrote:
>
> > hi,
> >
> > I am having problem in simulating the Virtex's Primitive (e.g
CLKDLL,
> > BUFG...) using Modelsim. Could anyone tell me how to do it? I got
errors
> > in the Modelsim like
> >
> > # WARNING[1]: main.vhd(244): No default binding for component:
"ibufg".
> > (No entity named "ibufg" was found)
> > # WARNING[1]: main.vhd(247): No default binding for component: "clkdll".
(No
> > entity named "clkdll" was found)
> > # WARNING[1]: main.vhd(248): No default binding for component: "bufg".
(No
> > entity named "bufg" was found)
> >
> > Thanks.....
> >
> > Chris
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
>
>
Article: 51436I am glad to hear this :-) So i don't have to use some additional 74HCT4066 ?!! THX TigerMole On 13 Jan 2003 15:56:44 GMT, mikeandmax@aol.com (Mikeandmax) wrote: >Tiger growled- >>Is it possible to implement a bidirectional digital switch >>in a CPLD ? I want to cut off a databus ... >> > >sure! I/O on most CPLDs is tristate-able - >here is a snippet of code fer-instance - > >port ( data_a, data_b :inout std_logic; > a__to_b, b_to_a : in std_logic) >. >. >. >.architecture >. >begin >data_a <= data_b when b_to_a else 'Z'; >data_b <= data_a when a_to_b else 'Z'; > >end;Article: 51437
In article <39b51bc5.0301100933.1c71cd53@posting.google.com>, tbiggs <tnbiggs@yahoo.com> wrote: >2. FPGA logic is much easier and faster to test than processor logic. >You can create test patterns to test every gate pretty quickly in an >FPGA. Testing processor logic is more difficult and time consuming. So >testing costs will be a bit higher for the Pro. I wonder about this. LUTs are trivial to test, but that interconnect is a nightmare. The only saving graces are the partial-reconfiguration facilities and the regularity of the interconnect. >Will the Virtex II Pro be cheaper? Only Xilinx can say. Their answer, so far, is yes. >Our designs use lots of logic and lots of IO. A small amount of logic >and IO was sacrificed in the Virtex II Pro to make room for the SerDes >and processors. Yes, Peter, we don't have to use the Pro, but the >salesman was really pushing it on us, telling us that it is the future >of the Virtex line. > >A point solution is one that solves one specific problem, rather than >a large number of problems. > >Are the SerDes and processor point solutions? I'll argue NO. External bandwidth, like luts, is something where "Yes, I want more". No matter how much I/O bandwidth you have, no matter how many LUTs you have, there will be people who want more. Sacrificing a couple of BlockRAMs on the perphery to enable much higher I/O is definatly worth it. Similarly, the processor... There are a lot of tasks where FPGAs can totally trash a processor, both in terms of latency (time to process a single datum through a feedback loop) and throughput (total processing per unit time). But there are other tasks where the processor wins, hands down. These tasks may be critical as part of the system. And you can't just say "throw down a soft-core". First, soft-cores, even something like the Microblaze, are very inefficient compared with a hard core. But these soft cores are much lower on the clock rate, therefore much worse on the latency. >Anyone want to guess how many of Xilinx's customers are using all four >405 embedded processors in an FPGA? My guess is that you could count >them on one hand. "Cisco"... A LOT of network/telecom/processing tasks really really benefit from lots of processors. Look at all these network processor designs. Do people use all 8 threads on each of 8 microengines on an Intel network processor? Yes. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51438
In article <3E230EAB.5010309@rogerstech.co.uk>, Andrew Rogers <andrew@rogerstech.co.uk> wrote: >Does the xdl command give the data to reverse engineer the bitstream or >is this in some datasheet somewhere on the Xilinx website? I have had a >quick look at the website but could not find anything relating to the >bitstream. Presumably any data on reverse enginneering could be used for >forward engineering. XDL is a tool which you can use to interface your own work between placement, routing, and bitgen. It is a format which describes the xilinx netlist in a textual form, with all the slices, etc defined. You could use it to reverse engineer the bitstream, by seeing what interconnect points do what, but why bother? If you want to do your own P&R tool, you could output .xdl with all the interconnect points defined, convert it back to .ncd, and throw it into bitgen and static timing analysis. The Virtex bitstream format these days is an "Open Secret". If you want to decompile/reverse engineer it, you can pretty easily, either using Jbits or .xdl. But you don't need to bother, since most usages (design manipulation, new tools) can be accomplished using .xdl or JBits so you don't have to. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51439
Marc Randolph wrote: > > $80 may be expensive to some people. > > Thorsten can cascade two DLL's on a Virtex-E or Spartan-IIE to get a > multiply by 4. More info can be found in app note 132. > > Marc Multiply by 4 isn't the problem. A lot of FPGAs are able to that, e.g. Altera ACEX. But all Altera devices do not allow feeding the PLL by internal signals. ThorstenArticle: 51440
Chris, Check out (you'll need current Mentor Graphics support): http://www.mentor.com/supportnet/appnotes/1308.html The library should have been shipped with your place and route software. Len -- Len_Harold@mentor.com 800-547-4303 Sign up for SupportNet at www.mentor.com/supportnet Jim Raynor wrote: > > Ray, > Thanks for the response. Could you tell me where to download the > library? > > Thanks again > > Chris > > "Ray Andraka" <ray@andraka.com> wrote in message > news:3E231694.F2763AE6@andraka.com... > > you need to include the library and use clauses to invoke the unisim > library. > > > > Jim Raynor wrote: > > > > > hi, > > > > > > I am having problem in simulating the Virtex's Primitive (e.g > CLKDLL, > > > BUFG...) using Modelsim. Could anyone tell me how to do it? I got > errors > > > in the Modelsim like > > > > > > # WARNING[1]: main.vhd(244): No default binding for component: > "ibufg". > > > (No entity named "ibufg" was found) > > > # WARNING[1]: main.vhd(247): No default binding for component: "clkdll". > (No > > > entity named "clkdll" was found) > > > # WARNING[1]: main.vhd(248): No default binding for component: "bufg". > (No > > > entity named "bufg" was found) > > > > > > Thanks..... > > > > > > Chris > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 > >Article: 51441
Dmitri Katchalov wrote:
>
> rickman <spamgoeshere4@yahoo.com> wrote in message news:<3E1F1F12.A6722E19@yahoo.com>...
>
> > The main issue is to keep the address and data stable while the write
> > strobe is asserted.
>
> Just wondering if I can achieve that without extra wait state.
You can operate async RAMs in just one clock cycle if you want to get
fancy. But this requires a lot of attention to all the delays. But
certainly you can use any number of clock cycles less than the 4 I
suggested. My suggestion was based on the simplest way to make sure all
timing was met with a very simple design.
> My RAM has 0 min hold time for address and data with respect to /WE and /CS.
> If I drive /CS and /WE with fast slew rate drivers and drive address lines
> with slow drivers, is it too risky?
You likely can do this, but there are simpler ways. If you want to use
two clock cycles, you can change address and data on one phase and
generate the strobes on the other, like this.
| Write | Read |
FPGA Clock ____----____----____----____----____----___
RAM Addr ====<--addr-stable--><-addr-stable-->======
RAM Data ====<--data-stable-->zzzzzzzzzzzzzzz>======
RAM WR ---------________--------------------------
RAM OE -------------------------________----------
RAM CS ---------________--------________----------
^
FPGA Reads Data |
This is actually the same as the four clock cycle timing, but it uses
four *half* clocks by generating the strobes on the falling edges. Is
that good enough for your design? This will not require you to worry
about detailed timings of trace runs, etc.
> Also someone suggested using bus keepers on the data bus to ensure enough
> data hold time. If I set /WE high and at the same time set data bus to HiZ,
> this should be work, right?
Not sure. You would need to post your design timing.
> Finally SpartanIIE has 2.2 ns max clock-to-HiZ and my RAM has 3ns min
> /WE-to-LoZ. This gives me 0.7ns plus clock-to-pad delay (which has no
> specified minimum) to aviod bus contention. Is it sufficient?
I would try to stay away from this sort of timing. Contention really is
not a big problem in my experience, but it is easier to just give
yourself large margins rather than work with delays at a sub nanosecond
level.
> On a separate note I couldn't find any numbers for the max *difference*
> in clk-to-pad time between two outputs. I don't think one output can be
> upto 2.9ns either ahead or behind another given that they both are at
> the same Vcc and temperature.
We call that skew and it should be spec'd somewhere. Looking at the
Xilinx SpartanIIE data sheet, I don't find it either. Even more reason
to not depend on delays for your timing rather than clock periods.
> BTW my project is a one-off hobby stuff, not for production.
>
> Thanks,
> Dmitri
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 51442Andrew Rogers wrote: > > It would seem that the Open Source software developers haven't quite > managed to produce a complete tool chain for programming FPGAs. The > remaining issue seems to be that FPGA manufactures are not willing to > supply the necessary bit-stream specification and make excuses, giving > the details of the bit-stream would allow reverse engineering of > commercial products that use their FPGAs. That's probably true, but any > one wishing to clone such a product only has to duplicate the bit-stream > and no reverse engineering is required. > > If FPGA manufactures continue this ridiculous trend then maybe the only > option is to develop a new FPGA which has all of its specifications > available. > > I know that this issue has been raised in the past, but this time I am > following up a different approach, the development of an Open FPGA. > > Can anyone (Xilinx maybe) estimate the cost and time involved in > development of a new and open FPGA? > > Maybe I could test out the new Open FPGA with my University Ph.D. work > on Turbo codecs! Actually, most of the effort involved is software rather than hardware. I think most people underestimate the amount of effort involved in developing the design software. The other issue is the fact that you can't design one FPGA or even one line of FPGAs and expect this to remain viable over time. FPGAs are on the cutting edge of technology and keep advancing in significant ways (not just bigger) as the underlying technology advances. If you design an FPGA today and have the software for it ready, you have to immediately start on a new effort just to keep up with where the technology is going tomorrow. I just don't think this is an effort that can be developed by anything other than a for-profit company. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51443
My question is a big: WHY? Yes, you might grow your own. When I was a kid we grew our own potatoes and vegetables and made butter and slaughtered a pig every year. But that was out of necessity, not choice. Now I much rather make a decent salary and buy most of these things, and for a hobby do some gardening, just for the fun of it.... The benefit of the closed FPGA architecture ( and the intense competition between "you know who") is an almost unbelievable rate of progress in capabilities and ease of design. Does anybody really want to go back to XC3000 and EXACT-like tools? For the user, the FPGA should just be a device that gets the job done with a minimum of fuss and headache, sweat, risk, delay and money. Only for Xilinx and Altera (plus a few others) is it the raison d'etre, but we are a small community that gets their kicks ( and salary ) out of this effort. If you are so eager to design an FPGA, come and join us and help us speed up progress even more ! But none of this griping about "open bitstreams". That's not where the real progress could possibly be! The exciting progress is in innovative FPGA applications. End of soapbox. Peter Alfke ================================== "Nicholas C. Weaver" wrote: > In article <3E230EAB.5010309@rogerstech.co.uk>, > Andrew Rogers <andrew@rogerstech.co.uk> wrote: > >Does the xdl command give the data to reverse engineer the bitstream or > >is this in some datasheet somewhere on the Xilinx website? I have had a > >quick look at the website but could not find anything relating to the > >bitstream. Presumably any data on reverse enginneering could be used for > >forward engineering. > > XDL is a tool which you can use to interface your own work between > placement, routing, and bitgen. It is a format which describes the > xilinx netlist in a textual form, with all the slices, etc defined. > > You could use it to reverse engineer the bitstream, by seeing what > interconnect points do what, but why bother? > > If you want to do your own P&R tool, you could output .xdl with all > the interconnect points defined, convert it back to .ncd, and throw it > into bitgen and static timing analysis. > > The Virtex bitstream format these days is an "Open Secret". If you > want to decompile/reverse engineer it, you can pretty easily, either > using Jbits or .xdl. But you don't need to bother, since most usages > (design manipulation, new tools) can be accomplished using .xdl or > JBits so you don't have to. > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51444
2Penny wrote: > > Gentlement: > > I've built a small computer board for a small local college (mostly > from one of the professor's designs and partly from designs in the > book). The machine uses PLDs in several places and I figured I could > simplify the board some (and improve by skills) by (learning about and) > using FPGAs, but I don't know where to get the initial software or > download equipment. If you want to simplify the board, you might do better using a CPLD. FPGAs can be used, but they are not ready for operation at power up. They must be configured. Most of the CPLDs are EEPROM or Flash based and once programmed, will operate immediately on power up. The CPLDs are mostly organized as multiple PLDs with extra interconnections. Can you tell us what PLDs the board currently uses? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51445
Andrew Rogers wrote: > john jakson wrote: > > Andrew Rogers <andrew@rogerstech.co.uk> wrote in message news:<3E214B75.5080507@rogerstech.co.uk>... > > > >>It would seem that the Open Source software developers haven't quite > >>managed to produce a complete tool chain for programming FPGAs. The > >>remaining issue seems to be that FPGA manufactures are not willing to > >>supply the necessary bit-stream specification and make excuses, giving > >>the details of the bit-stream would allow reverse engineering of > >>commercial products that use their FPGAs. That's probably true, but any > >>one wishing to clone such a product only has to duplicate the bit-stream > >>and no reverse engineering is required. > >> > >>If FPGA manufactures continue this ridiculous trend then maybe the only > >>option is to develop a new FPGA which has all of its specifications > >>available. > >> > >>I know that this issue has been raised in the past, but this time I am > >>following up a different approach, the development of an Open FPGA. > >> > >>Can anyone (Xilinx maybe) estimate the cost and time involved in > >>development of a new and open FPGA? > >> > >>Maybe I could test out the new Open FPGA with my University Ph.D. work > >>on Turbo codecs! > >> > >>Thanks > >>Andrew Rogers > > > > > > Indeed it is an old subject that is pretty much been flogged to death. > > > > You could chase after some 6200 stuff or look out for meta FPGA. > > > > Is the XC6200 still available? No. The XC6200 was discontinued after Virtex was introduced. Steve > I can't find any info on it from the > Xilinx website. I did manage to a datasheet from elsewhere on the web. > The XC6200 datasheet does have the bitstream details. > > www.vcc.com/Papers/6200.pdf > > Regards > Andrew RogersArticle: 51446
Hello, I have a newbie style question in VHDL: I declared 8 discrete signals, connected to IO pins of my FPGA: signal d0,d1,d2,d3,d4,d5,d6,d7 : in std_logic; Now I would like to manipulate them as an array, to assign them in a single statement for example. I thought aggregates were the right thing to use, but XST complains about type ambiguity when I write: (d7,d6,d5,d4,d3,d2,d1,d0) <= "ZZZZZZZZ"; Using an alias does not seem to be the right solution either, one can not write alias data(0) : std_logic is d0; I also have to manipulate an 18 bit address define as 18 discrete signals connected to IO pins of my FPGA: having 18 assignments every time I have to update this address is not very elegant... I am sure there is a better solution do you have any suggestions? Thank you for your help, Frederic Bastenaire (fba@free.fr)Article: 51447
There are two ways that xdl helps you figure out is going on. One gives all the resources on the die like wires, pips slices... I use this data to read in a blank part and draw it to the screen. Then you can use it to get data about what your design used. I use this to color the blank and show what resources are used. You can make compile it to ncd go to xdl and change little parts of it in the xdl send it back to ncd and then go into the bit format. You can see what bits change and start to understand what a tile is like. If you wrote a program to read in the die information and use that in a design then get the bit data you could find out exactly how to do everything yourself. There is 110 MB of data for the V300. Maybe we should start a project to build tools for Xilinx Virtex. Anybody want to try?? Steve "Andrew Rogers" <andrew@rogerstech.co.uk> wrote in message news:3E230EAB.5010309@rogerstech.co.uk... > Steve Casselman wrote: > > The 302 patent doesn't stop Altera or Triscend or others. Xilinx gives all > > the data to reverse engineer the bitstream. It is not very well documented > > however. Look at the xdl command. > > Does the xdl command give the data to reverse engineer the bitstream or > is this in some datasheet somewhere on the Xilinx website? I have had a > quick look at the website but could not find anything relating to the > bitstream. Presumably any data on reverse enginneering could be used for > forward engineering. > > > You could write a program that translates > > the xdl output into and out of the U of Toronto place and route tool. You > > could take JBits and write a program to figure out the V1 bitstream. I think > > it would take a small group of programmers (5-10) a year or so but it is > > possible. > > I thought I had JBits and the source until I discovered that I actually > had jbittools which uses JBits. I am now waiting to see if Xilinx will > honour my request for the JBits SDK. > > Thanks > Andrew Rogers >Article: 51448
Steve Casselman wrote: > There are two ways that xdl helps you figure out is going on. One gives all > the resources on the die like wires, pips slices... I use this data to read > in a blank part and draw it to the screen. Then you can use it to get data > about what your design used. I use this to color the blank and show what > resources are used. You can make compile it to ncd go to xdl and change > little parts of it in the xdl send it back to ncd and then go into the bit > format. You can see what bits change and start to understand what a tile is > like. If you wrote a program to read in the die information and use that in > a design then get the bit data you could find out exactly how to do > everything yourself. There is 110 MB of data for the V300. > > Maybe we should start a project to build tools for Xilinx Virtex. Anybody > want to try?? ever tried visualising a .bit file as a rectangular binary image of size (rows * cols), where rows and cols are as defined in the Virtex doco? you can do the same thing with the bit mask file (overlay it to see where "your" bits are). then compare against the display from floor planner. Cheers, JohnArticle: 51449
Nicholas C. Weaver wrote: > In article <3E230EAB.5010309@rogerstech.co.uk>, > Andrew Rogers <andrew@rogerstech.co.uk> wrote: > >>Does the xdl command give the data to reverse engineer the bitstream or >>is this in some datasheet somewhere on the Xilinx website? I have had a >>quick look at the website but could not find anything relating to the >>bitstream. Presumably any data on reverse enginneering could be used for >>forward engineering. > > > XDL is a tool which you can use to interface your own work between > placement, routing, and bitgen. It is a format which describes the > xilinx netlist in a textual form, with all the slices, etc defined. > > You could use it to reverse engineer the bitstream, by seeing what > interconnect points do what, but why bother? > > If you want to do your own P&R tool, you could output .xdl with all > the interconnect points defined, convert it back to .ncd, and throw it > into bitgen and static timing analysis. > > The Virtex bitstream format these days is an "Open Secret". If you > want to decompile/reverse engineer it, you can pretty easily, either > using Jbits or .xdl. But you don't need to bother, since most usages > (design manipulation, new tools) can be accomplished using .xdl or > JBits so you don't have to. Just took a look at the free WebPack ISE software for Windows and found some documentation on XDL that seems to have Linux like commands. D:\Xilinx\help\data\xdl\xdl-ucs-ext.html Does this mean that the free WebPack ISE is also available for Linux or Unix? If I can get free FPGA software for Linux then I can get by without Open Source software tools. Regards Andrew Rogers
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z