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rk wrote: > > Bob Perlman wrote: > > >>There are also FPGAs on the way to Saturn on the Cassini > >>spacecraft. > > > > I'm pretty sure some FPGAs that I RMA'd a while back ended up going > > to Pluto. > > That's probably a bit doubtful as no spacecraft has yet gone to Pluto > and none are en route. There is one project that is going to go to > Pluto but it's still in the early stages (the early stages can last a > while ;-) and hasn't yet had it's Critical Design Review. Perhaps what > you RMA'd was for a development project for a mission to project and > those sorts of things go back many, many years. I think you need to reread his message with a smiley (possibly winking) at the end. RMA means "Return Material Authorization" and is usually used to return defective parts. Sometimes I think we have too many engineers in this group. ;) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56401
Hello folks, I want to be able to run Altera FIR Compiler 2.6.3 from the command line specifying the details of the filter I require. When I use the gui manually, a file called "fir_alt_singlerate_silent_param.txt" is created whose name does indicate that this is possible but I cannot find anything in the documentation or the web that explains how to do this. The fir_alt_singlerate_silent_param.txt file does not specify the coefficients or where to find them so I guess this must be a 2nd param perhaps in addition to the fir_alt_singlerate_silent_param.txt file? I have found the mac_gui.exe file in the megacore directory but it does not seem to accept params in the manner I want to use it. I want to do this so I can script several filter generation and compilation runs in Quartus II varying the number of channels on the filter each time - maybe I can do this from with Quartus II? I can run quartus from the command line successfuly and have done so in conjunction with Synplify within a batch file so I am sure I can make the scripts work if someone can tell me how to kick fir compiler to do it! Thanks very much for your time, KenArticle: 56403
Thanks for your aid. The rate is 1/2 and with puncturing I obtain 2/3 (The code length is 8 and puncture code is 11 and 10 (each four bit I keep only the first, the second and the third). The bits I have indicated in the message are only a short sample. Best regards. VenexArticle: 56404
rickman wrote: > rk wrote: >> >> Bob Perlman wrote: >> >> >>There are also FPGAs on the way to Saturn on the Cassini >> >>spacecraft. >> > >> > I'm pretty sure some FPGAs that I RMA'd a while back ended up >> > going to Pluto. >> >> That's probably a bit doubtful as no spacecraft has yet gone to >> Pluto and none are en route. There is one project that is going >> to go to Pluto but it's still in the early stages (the early >> stages can last a while ;-) and hasn't yet had it's Critical >> Design Review. Perhaps what you RMA'd was for a development >> project for a mission to project and those sorts of things go back >> many, many years. > > I think you need to reread his message with a smiley (possibly > winking) at the end. RMA means "Return Material Authorization" and > is usually used to return defective parts. > > Sometimes I think we have too many engineers in this group. ;) No, just thought that perhaps he was involved in one of the many Pluto development projects. We of course know that all of the RMA'd parts get sent to Mars. -- rk, Citizen, Noooo Yawk "Sometimes when you connect the dots you get a picture. Other times you just have a bunch of dots." -- rk, January 23, 2003Article: 56405
Putting a non-volatile ID number on every chip is not so difficult, but it must be redable after the device is packaged ( logistic nightmare otherwise). That readback must be stoppable, otherwise no security. Your suggestion still requires a decryption engine of at least DES quality, costing silicon area and thus increasing the price for everybody. Regarding key length and relative security: The goal should be to cause a "cost of cracking" of $100 000 or more. (Once it is cracked on one chip, the enemy can make unlimited numbers of unprotected copies). The availability of ever cheaper computer power (extrapolated over the next several years) means that the encryption algorithm has to be "pretty good" and the key has to be "pretty long", and "pretty well hidden" ( no visibly readable fuses ). Just some thoughts, and why this is more complex than just adding a serial number... Peter Alfke raymund hofmann wrote: > > > Why don't put a kind of "Host ID/Serialnumber" on the FPGA in some kind of > "one time programmable" way at Manufacturing the FPGA ? > I think Intel CPU's already each have different ID's since some time. > > I doubt this is a cost/performance penalty like manufacturing a FPGA on a > flash-process. > > This ID can then be used to decrypt a bitstream. > And the device should accept two kinds of bitstreams: > Encrypted with it's ID + Unencrypted. > And this ID should be electronically readeable off the FPGA. > > I think it is only a matter of time when one FPGA company starts such a > thing even for the "low cost" Parts. > > Of course will the FPGA Customer have to care about generating individual > Bitstreams for each device ID of the Part's used, if he wants "security". > As there often is a MCU with the FPGA(s) on Board there is additional > flexibility in handling the "design security". > Or he may choose not to encrypt. > > Raymund HofmannArticle: 56407
In paper http://klabs.org/richcontent/Papers/desplats2.pdf "23 Actel FPGAs can be found in the Mars Pathfinder and the Mars Sojourner" A 1999 Actel press release http://www.actel.com/company/press/1999pr/SpaceContribution.html mentions Mars missions, HST, SIRTF and STARDUST which is on the way to Comet Wild 2 with about 100(!) Actel FPGAs Kate "Mike Butts" <reconfigurable_logic@yahoo.com> wrote in message news:9d031b1e.0305281738.6c23822e@posting.google.com... > The May 2003 issue of IEEE Spectrum has a nifty and > detailed article on the exciting British Beagle 2 > lander hitching a ride on ESA's Mars Express orbiter, > set to launch soon and arrive in December. > > Its robotic arm carries a bunch of instruments and > other devices. "Discrete electronic interfaces > between each instrument and the lander would have > been complex to build and heavy as well. So the > PAW uses a single interface with a field-programmable > gate array that can reconfigure itself to match each > instrument's needs." > > Excellent! One of you must be able to tell us more. > Who's the clever designer? Who's the lucky vendor? > What device? Rad-hard? Fault-tolerant? Designed > in what language? Verified how? Bitstreams stored > where and loaded by what? Can they upload new > bitstreams from Earth? (Now that's an UPload!) > What if DONE doesn't go high? > > Will this be the first FPGA in Mars space? > > Most important of all, will they send a paper to > FPL 2003 or FPGA 2004 or FCCM 2004? > > --MikeArticle: 56408
Raymund, Laser popping of fuses is a well known, and well used technology in low cost manufacturing, but as a means of keying the device, pretty lousy security. Imagine just popping the lid and examining the blown holes in the polyamide? Basically, remember that we really really really want to do what you are suggesting, and it isn't for lack of trying, or experimentation, that it isn't there. We have two issues: no good practical low cost secure way to put keys into a standard CMOS process, and very few customers willing to pay a premium. Right now we have the feature in V2 and V2P with the battery backed up RAM. Cost? One lithium coin cell, (coind cell holder), a diode, and a capacitor (to prevent memory loss when you replace the battery). Maybe throw in a 1Mohm resistor in series to help prevent memory loss if someone shorts out the battery while replacing it. Not the best solution (I would love to have NVRAM in standard CMOS, too), but one that allows folks who absolutely have to have triple DES level encryption to succeed. Austin raymund hofmann wrote: > "Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag > news:3EDB8423.29CA2C46@xilinx.com... > > > > > > emanuel stiebler wrote: > > > > > But, anybody out here has an idea, why there is no bitstream encryption > > > on the spartan 3 ? With all this gates & memory, you could do impressive > > > designs, but to keep them for safe you still have to go to the virtex > > > chips ... > > > > It's really quite simple: > > The priorities for Spartan are: Low cost first, features and speed second. > > For Virtex the priorities are reversed. > > Makes a lot of sense, avoids unproductive overlap, and gives the user a > > fair choice. Cheap or fancy. There is no free lunch... > > > > Now, if encryption were a popular feature in the low-cost market (please > > tell us), then it would make sense to dedicate some silicon and a pin > > for the on-chip decryption. > > Why don't put a kind of "Host ID/Serialnumber" on the FPGA in some kind of > "one time programmable" way at Manufacturing the FPGA ? > I think Intel CPU's already each have different ID's since some time. > > I doubt this is a cost/performance penalty like manufacturing a FPGA on a > flash-process. > > This ID can then be used to decrypt a bitstream. > And the device should accept two kinds of bitstreams: > Encrypted with it's ID + Unencrypted. > And this ID should be electronically readeable off the FPGA. > > I think it is only a matter of time when one FPGA company starts such a > thing even for the "low cost" Parts. > > Of course will the FPGA Customer have to care about generating individual > Bitstreams for each device ID of the Part's used, if he wants "security". > As there often is a MCU with the FPGA(s) on Board there is additional > flexibility in handling the "design security". > Or he may choose not to encrypt. > > Raymund HofmannArticle: 56409
Hi, You could try the following (i am assuming you are using the Nios development Board): Press SW3 and while it is depressed, press SW4. If it doesn't work, also try the reverse, i.e. press SW4 and while it is depressed, press SW3. I have found that one of these works in my case. regards, Satchit arkagaz@yahoo.com (arkaitz) wrote in message news:<c1408b8c.0306020106.9475338@posting.google.com>... > Hi there, > > I'm working with the Nios Excalibur Kit and I have a problem with the > GERMS which is included in the ROM of the Nios. > > I have a software program stored in the FLASH memory of the Nios > Development > Kit and it works correctly: when I reset the board, the GERMS looks > for the software application in the FLASH and it copies to the SRAM > memory to be able to execute it. > > But when I want to access to the Nios microprocessor directly from my > NDK Shell, I push the SW4 button while I reset the board as it appears > in the manual, but it doesn't work. > > I don't know why, but it only works with the tutorial applications > such as "standard 32", etc... > > Does anybody know the reason of this strange situation? > > Thanks.Article: 56410
Sorry Peter but I think you can say your product are better because you
have more sales. Most of the time the selection of a part is historical.
What I mean is if a company use fpga supplier Y for their old product, they
have 99% of the chance they will use a fpga supplier Y part for their new
product whatever the technology is the best or not because they have the
tools (no learning curve), they have volume price discount on all fpga
supplier Y parts independently of the volume target of this new project,
they have good relationship with the supplier/rep/distributor, ...
If people would switch company each time a product from one company is
better then an other, I think you would have been in bankrupt in around 1994
when you had your 4000 family product with your stupid tool who wasn't able
to route anything against altera 8000 family with it easy tool max+plusII.
Most of the time, when a company start, they select the designer's known
fpga supplier (not necessarly the best technology) at the startup moment and
stick with it for the rest of their life.
regards
FE
"Peter Alfke" <peter@xilinx.com> wrote in message
news:3EDD0E8C.A88643AF@xilinx.com...
>
> rickman wrote:
> >
> >
> > I think Peter is very good at being professional. But claiming that the
> > competition's technology *must* be inferior because the company is not
> > doing well is just plain silly.
>
> Peter replies: Here is what I posted, verbatim:
>
> "Then we have to ask ourselves:
> Why are all these companies so small and/or doing so poorly?
> The market is the final arbiter. Success in this industry is defined by
> a profitably growing sales volume..."
>
> > When they started trashing the
> > competition, and in this case in spite of the facts, I let it push a
> > button.
>
> Peter replies:
> I was not trashing the competition. In a way, I was saying: If their
> stuff is so good, why is that company not successful?
> Lattice, once one of the Big Three in sales volume is now far behind
> (inspite of having absorbed AMD's and Lucent's programmable logic lines.)
>
> I maintain: A profitably growing sales volume, and a rising share of
> market, are both a favorable vote from the user community, voting with
> their money. That's the advantage of capitalism: Feedback is pretty
> swift, either encouraging or devastating.
> And we, as well as all our competitors, are watching that feedback,
> daily.
> Now let me get back to the technical issues...
> Peter Alfke
Article: 56411christopher.saunter@durham.ac.uk (Christopher Saunter) wrote in message > : Confluence actually originated from a Python based HDL called > : ParaCore (http://www.dilloneng.com/paracore.html). > > I use a rather simpler (read naffer ;-) Python based simulater for > synchronous logic I wrote to help design some dspish projects. One thing > I use is a GUI front end, primarily for visualising dataflow through a > desgin - I find visual feedback drastically simplifies aligning data > pipelines and control flow etc. From a brief look at the Confluence docs > on the Python model, it should not be to involved to produce a GUI > front end for it. Is this something Launchbird plan, or is there > scope / interest for a GUI front end for visualisation of the Python > models? Of the various suported languages, I expect Python would be the > best suited to such a task. I also believe dataflow visualization (aka. block diagrams) greatly aids design and debugging. Before coding, we used to sketch out components in Simulink, just using subsystems, ports, and wires; nothing else. Simulink is great for this. I just wish Matlab sold a low-cost non-simulation version. I've search the net many times, but have never found a good open-source block diagram editor -- a tool that is not only invaluable for hardware design, but also very practical for software applications, especially hard real-time systems. For the near future, Confluence will stay strictly command line. At one point, we did consider incorporating model visualization, but we were just too busy to get it off the ground. However, if an open-source Python/wxWindows block diagram editor project were to appear on the seen, we would certainly contribute development time. And given the BDE's file format, we'd build up code to translate from our internal representation. > > Also, from reading the docs, maybee it's time I revived my side project of > investigating Haskell... > May I recommend Ocaml? We couldn't have gotten Confluence flowing without it. -Tom -- Tom Hawkins Launchbird Design Systems, Inc. 952-200-3790 tom1@launchbird.com http://www.launchbird.com/ > : The first Confluence seat is free, indefinite, and > : enables the full compiler -- no size or performance restrictions. > : Our revenue comes from the medium to larger design firms. > > Nice one. I hope that aproach proves fruitfull - it is certianly > appreciated at my end of the world. > > Cheers, > Chris SaunterArticle: 56412
Can we generate Post P&R Verilog or VHDL netlist from ISE that can be synthesiable ? I used ngd2ver but the output verilog netlist contains lots of statements that are not synthesizable. Same is the case with VHDL. Thanks -VsArticle: 56413
Karsten Becker <KB@karsten-becker.de> wrote: : Uwe Bonnes wrote: :> Support in Webpack only goes up to the 400 size : This http://www.xilinx.com/ise/products/webpack_config.htm claims : webpack to even just support the 50 one... Look in the answer database at answer #17109 But remember: It will probably be a long time before normal consumer may get the Spartan3 in a normal way. Even XC2VP still seems to be in the "engineering sample" phase, at least judging from the nunet/avnet product queries. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 56414
"rk" <stellare@NOSPAMPLEASE.erols.com> wrote in message news:Xns938FF0629C949rk@199.184.165.240... > Mike Butts wrote: > > > The May 2003 issue of IEEE Spectrum has a nifty and > > detailed article on the exciting British Beagle 2 > > lander hitching a ride on ESA's Mars Express orbiter, > > set to launch soon and arrive in December. > > > > Its robotic arm carries a bunch of instruments and > > other devices. "Discrete electronic interfaces > > between each instrument and the lander would have > > been complex to build and heavy as well. So the > > PAW uses a single interface with a field-programmable > > gate array that can reconfigure itself to match each > > instrument's needs." > > > > Excellent! One of you must be able to tell us more. > > Who's the clever designer? Who's the lucky vendor? > > What device? Rad-hard? Fault-tolerant? Designed > > in what language? Verified how? Bitstreams stored > > where and loaded by what? Can they upload new > > bitstreams from Earth? (Now that's an UPload!) > > What if DONE doesn't go high? > > > > Will this be the first FPGA in Mars space? > I worked on Mars Express. I participated in the construction of the PCU (Power Conditioning Unit) and worked on the HW MPPT (Maximum Power Point Tracking) and the super-buck converter for the solar array SMPS. Also I made test equipment for automated test of the engineering and flight models (only the PCU). One of my colleages worked on the CM (Command Module) and that one had an Xilinx Rad Hard FPGA that controlled the status and setpoints for the PCU. The FPGA had some sort of provision for digital voting of all the signals. On our modules we used analog voting for all critical functions. One thing that puzzled me. We had extensive reviews with Astrium (Subsidiary/contractor of ESA) on the hardware circuits. But the programming/structure of the FPGA were never checked. I often asked about this - but no-one seemed to care?? Cheers KlausArticle: 56415
Hi, Sundance do a 3u carrier on which you can plug FPGA daughter cards of various sizes (www.sundance.com) Don't suppose you could go to a 6U rack, as there are a lot of good candidates in this format: Nallatech do a cPCI 6U carrier with a single XCV2000E and two daughtercard sites, each of which can take dual XC2V8000 daughtercards. (www.nallatech.com) Mel "Peter Matthijs" <peter.matthijs@verhaert.com> wrote in message news:<3edda4d4$0$13246$4d4efb8e@news.be.uu.net>... > Hi, > For the test/debugging of our VHDL designs we're looking for a development > board that has a Xilinx Virtex FPGA directly connected to a compact PCI > (cPCI) bus. The board must fit in a 3U 3.3V rack system. The FPGA chip > should have at least 1M system gates but if its less then we'll settle for > that. > Any research labs that might have this kind of board and are interested to > sell one? > If this exists on the market i'm also interested but haven't found it yet. > Thanks, > PeteArticle: 56416
Anybody know of Cyclone EP1C12 (preferably) or EP1C20 (also ok) based PCI development boards? Do such things even exist - or in other words, what is the approximate timline after chip availability that one can expect such to be around? -- Sander +++ Out of cheese error +++Article: 56417
Hi, I have a question about clock synchronization between multiple boards. I'm trying to capture data from one board on to another. For this I will need the clocks to be synchronized, which I'm unable to do. What would happen if I did the following : I connect the outputs from one board to the inputs of the 2nd board. I run the 2nd board at the same clock speed as the 1st board (but use the individual board's clocks). Meanwhile, I also take the clk from board 1 as an input to board 2. Now I try to capture data in board 2 using clk from board 1 as an enable signal. What are the pitfalls using such a design ? Notes: 1. The two boards run at the same speed but use their own internal clocks. Hence the 2 boards are not synchronized. 2. Board 1 clk is provided to board 2 as an enable input. 3. The data to be captured from board 1 is available at the rising edge of board 1's clk. 4. I have to do all this, since I may not be able to supply board 2's clk input with board 1's clk (inaccessible). Thanks, PrashantArticle: 56418
Sander Vesik wrote: > Anybody know of Cyclone EP1C12 (preferably) or EP1C20 > (also ok) based PCI development boards? Do such things > even exist - or in other words, what is the approximate > timline after chip availability that one can expect such > to be around? > While looking for a dev. board for myself I can't remeber to have seen a pci-enabled cyclone board. The only shipping EP1C20 board I know is the one from MJL. KarstenArticle: 56419
Is anyone out there using a third-party schematic entry tool (or even HDL tool) for Xilinx FPGAs? I'll exclude Synplicity from my poking and prodding because I know it's used a lot. There are several situations where schematic entry would be a nice alternative to HDL for building an RPM. ECS is a waste of bits in my opinion and Viewlogic isn't so hot anymore. I know Protel offers schematic entry with Xilinx primitives and I assume OrCAD has something similar. Are they worth using? As always, you make yourself a slave to the tool by doing this and I see that as one big advantage of the HDL route, but I thought I'd ask. JakeArticle: 56420
Legacy acts like hysteresis ( Schmitt trigger ) and like a low-pass filter in the feedback path, but it can never guarantee the (monopolistic) protection that Microsoft and Intel enjoy in their businesses. We in Programmable Logic land have to earn our success every day again. Just remember the bad days Xilinx had in the late XC4000 period, and the bad time Altera had, until Stratix rescued them from their long series of family blunders. We can and will never rest on our laurels. "Only the paranoid will survive" as Intel's Andy Grove once said. Peter Alfke FE wrote: > > Sorry Peter but I think you can say your product are better because you > have more sales. Most of the time the selection of a part is historical. > What I mean is if a company use fpga supplier Y for their old product, they > have 99% of the chance they will use a fpga supplier Y part for their new > product whatever the technology is the best or not because they have the > tools (no learning curve), they have volume price discount on all fpga > supplier Y parts independently of the volume target of this new project, > they have good relationship with the supplier/rep/distributor, ... > > ñArticle: 56421
Karsten Becker <KB@karsten-becker.de> wrote: > Sander Vesik wrote: >> Anybody know of Cyclone EP1C12 (preferably) or EP1C20 >> (also ok) based PCI development boards? Do such things >> even exist - or in other words, what is the approximate >> timline after chip availability that one can expect such >> to be around? >> > > While looking for a dev. board for myself I can't remeber to have seen a > pci-enabled cyclone board. The only shipping EP1C20 board I know is the > one from MJL. Thanx for the info. The MJL board looks quite nice for a system board development - but I doubt it would be a large help at all for an add-on card... > > Karsten > -- Sander +++ Out of cheese error +++Article: 56422
If the two clocks are generated by independent oscillators, then they will never be the same, so you have to cope with a frequency as well as a phase difference / uncertainty. If your transmitter is (even ever so slightly) faster than your receiver, you have a fundamental problem. The telecom people solve this by having identifiable stuffing data that the receiver is allowed to throw away ( or insert when the timing relationship is such that the receiver is faster than the transmitter.) Your transmitter somehow has to communicate the bit boundary to the receiver (imagine sending a string of a dozen zeros across the interface.) All these problems become trivial if the data rate is slow and a high-speed clock is available. But they are tough when these conditions are not met... http://support.xilinx.com/support/techxclusives/MovingData-techX16.htm might provide some help. Peter Alfke =========================== Prashant wrote: > > Hi, > > I have a question about clock synchronization between multiple boards. > I'm trying to capture data from one board on to another. For this I > will need the clocks to be synchronized, which I'm unable to do. What > would happen if I did the following : > > I connect the outputs from one board to the inputs of the 2nd board. I > run the 2nd board at the same clock speed as the 1st board (but use > the individual board's clocks). Meanwhile, I also take the clk from > board 1 as an input to board 2. Now I try to capture data in board 2 > using clk from board 1 as an enable signal. > > What are the pitfalls using such a design ? > > Notes: > 1. The two boards run at the same speed but use their own internal > clocks. Hence the 2 boards are not synchronized. > 2. Board 1 clk is provided to board 2 as an enable input. > 3. The data to be captured from board 1 is available at the rising > edge of board 1's clk. > 4. I have to do all this, since I may not be able to supply board 2's > clk input with board 1's clk (inaccessible). > > Thanks, > PrashantArticle: 56423
christopher.saunter@durham.ac.uk (Christopher Saunter) wrote in message news:<bbks5h$cu9$1@sirius.dur.ac.uk>... > Tom Hawkins (tom1@launchbird.com) wrote: > : christopher.saunter@durham.ac.uk (Christopher Saunter) wrote in message news:<bbi8rq$glp$1@sirius.dur.ac.uk>... > : > Tom Hawkins (tom1@launchbird.com) wrote: > > : Confluence actually originated from a Python based HDL called > : ParaCore (http://www.dilloneng.com/paracore.html). > > Also, from reading the docs, maybee it's time I revived my side project of > investigating Haskell... In that case, you'd really want to look at BlueSpec at bluespec.org, which is based off Haskell in the same way that Confluence is based off Ocaml. The BlueSpec compiler is freely available at the website. Among the major differences between the two is that BlueSpec generates VHDL and is, like Haskell, strongly-typed. The theoretical underpinnings of BlueSpec are documented in a PhD thesis by James Hoe written while at MIT. BlueSpec is operating under less publicized conditions, but IMO, its symbolic computation capabilities, particularly the term-rewriting features, are noteworthy. In other words, if your hardware designs call for extremely complex control structures, modelling in BlueSpec could very well accelerate your projects. (P.S. I am affiliated to neither companies.)Article: 56424
rickman wrote: <snip> I can tell you that Xilinx is losing some sockets to them. My design > has replaced two Coolrunner parts with the Lattice parts. I thought the > Coolrunners were perfect for the job. But Xilinx would not come down on > price on one and they put the part in too large a package for the > other. I am sure I am not the only engineer who sees the advantages of > some of the new flash parts, even compared to the FPGAs. BTW, Xilinx > FPGAs were never considered for these sockets because none of the > current families have 5 volt tolerance. Seems that is making a comeback > these days. Steering this back into technical arenas :- Lattice do seem to have responded well to 5V IO needs, but one interesting fine-print in their 4000Z spec, is a limit on the total number of IO allowed to have 5V - no explanation as to why ? Any comments on Lattice tools, relative to Xilinx ? -jg
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