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> I don't know where you got the 1.2 W and 0.605 W from, and I do not know > what you mean by "image". I guess the 0.605W came from the Xilinx power spreadsheet at http://www.xilinx.com/ise/power_tools/virtex2p_power_estimator_v120.xls although this is only for the 1.5V Vccint rail- the 2.5V Vccaux consumes another 400mW, giving a max quiescent of over 1W. Peter Alfke <peter@xilinx.com> wrote in message news:<3EEA3E28.161260@xilinx.com>... > I don't know where you got the 1.2 W and 0.605 W from, and I do not know > what you mean by "image". > Anyhow: > I assume that you have no strange dc loads on your outputs, and that the > inputs are not left floating. > There is always a certain static or idle current consumption. It used to > be very low (this is CMOS), only milliamps, but has gone up dramatically > with the newer submicron processes. The supply voltage was reduced > substantially, but the transistor threshold voltage cannot be reduced > proportionally. The result is that the off-transistors are not perfectly > turned off, each conducting fractional microamps in the off state. With > many millions of transistors on the chip, this current adds up. This > idle current increases with temperature, but is always there, > independent of the configuration, and independent of the static data > content. (Consider it the metabolism of the chip) > > Once you run data through the FPGA, you also have dynamic charging and > discharging of internal and also external capacitors, and the formula is: > P = C times f times (Voltage squared). The voltage is Vcc, but C and f > are specific to each internal node. Obviously, this dynamic power is > proportional to the clock frequency. Calculating the effective C is far > more complicated. > > Your total power is the sum of static and dynamic power. > > I have not divulged any secrets, and nothing here is Xilinx specific. > Pentium, Virtex2Pro, Stratix and all other modern CMOS devices show the > same behavior. > Ultra-low static power consumption is not compatible with > high-performance circuits using < 0.2 micron technology. We all have to > learn to live with that. :-( > Peter Alfke > ================ > "U. Hernandez" wrote: > > > > Hi, > > > > I am using a Virtex-II Pro (XC2VP30-FG676) and need to estimate the power > > consumed by this chip for different stages: > > > > (Note that I don't have an eval board or the prototype board yet) > > > > 1) Normal operation, DONE with XPower (~1.2W, with blah, blah logic) > > > > 2) Blank Image, DONE (~605mW, the h*ll of a lot and is only what I've got in > > there, the QUIESCENT POWER is massive) > > > > 3) When is not configured, how can I do this? > > > > I'd use a uP to fetch data from Flash and 'upload' different images to the > > FPGA, I'd like to know what happens when is powered up but there is nothing > > on it. > > > > Thanks in advance > > > > Ulises Hernandez > > ECS Technology Ltd. > > www.ecs-tech.comArticle: 56776
Peter Alfke wrote: > Ultra-low static power consumption is not compatible with > high-performance circuits using < 0.2 micron technology. We > all have to learn to live with that. :-( So is this it, a sort of "low power FPGA" middle age? Things will never get better/faster/denser in the low-power FPGA arena.Article: 56777
Tim wrote: > > Peter Alfke wrote: > > Ultra-low static power consumption is not compatible with > > high-performance circuits using < 0.2 micron technology. We > > all have to learn to live with that. :-( > > So is this it, a sort of "low power FPGA" middle age? > Things will never get better/faster/denser in the > low-power FPGA arena. :) Static power middle age was some while back.... (Faster and denser have yet to peak ) -jgArticle: 56778
Hello everyone. I would like to perform a series of tests automatically on my design. For each test, I need to change the input to the design, run the test, and examine the output. I can implement the testing logic in VHDL and run everything under my VHDL simulator, but there is a major problem with that. Every time I ran an exceptionally long VHDL simulation, my computer crashed. I'm using quite a strong server, so I don't think the problem is in the computer. I'm assuming that the long VHDL simulation simply "ate up" all of my system's memory. The only solution I can see, is to implement the input generation and output examination in software, and call the VHDL simulator on each test at a time. Does anyone know a better solution to the long VHDL simulation problem? Thanks, Gilad.Article: 56779
Here's a new tutorial. http://www.fpga4fun.com/LCDmodule.html Next week, I'll try to put a pong game. JeanArticle: 56781
Hi, I have a xilinx 9536 CPLD ISP demo board with a parallel cable III. I am using webpack with VHDL. I am trying to program the chip with a my simple design but I get this error: "Error: impact: 583 - the idcode read from the device does not match the idcode in the bsdl file" My chip is a couple years old, does this error mean there is some damage to the chip? I am new to webpack so am not sure of what I'm doing yet! :) thanks for any help, cheers, Jamie MorkenArticle: 56782
On Sun, 15 Jun 2003 23:08:15 GMT, "Jamie Morken" <truespace1@hotmail.com> wrote: >Hi, > >I have a xilinx 9536 CPLD ISP demo board with a parallel cable III. I am >using webpack with VHDL. I am trying to program the chip with a my simple >design but I get this error: >"Error: impact: 583 - the idcode read from the device does not match the >idcode in the bsdl file" > >My chip is a couple years old, does this error mean there is some damage to >the chip? I am new to >webpack so am not sure of what I'm doing yet! :) > Check the package type in your project. The 9536 is available in PC44, VQ44 and CS48 packages and BSDL files are both chip- and package.-specific. Maybe you specified VQ44 in your project though you have a PC44 chip.Article: 56783
Hi, > Check the package type in your project. The 9536 is available in PC44, > VQ44 and CS48 packages and BSDL files are both chip- and > package.-specific. Maybe you specified VQ44 in your project though you > have a PC44 chip. Thanks I tried that, I also downloaded some bsd files from the support.xilinx.com site but these failed to work as well. I'll keep trying anyway! cheers, Jamie MorkenArticle: 56784
"Jamie Morken" <truespace1@hotmail.com> wrote in message news:z%6Ha.235070$Vi5.6216826@news1.calgary.shaw.ca... > Hi, > > I have a xilinx 9536 CPLD ISP demo board with a parallel cable III. I am > using webpack with VHDL. I am trying to program the chip with a my simple > design but I get this error: > "Error: impact: 583 - the idcode read from the device does not match the > idcode in the bsdl file" > > My chip is a couple years old, does this error mean there is some damage to > the chip? I am new to > webpack so am not sure of what I'm doing yet! :) > I had this problem, also. The WebPack Impact software doesn't work with the older 9536, you will have to download the earlier programming software from the Xilinx web site (JTAG programmer 3.3WP8.x). I sent a msg to the group about it a year or so ago. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 56787
Hello, Does anyone know when Spartan3 devices other than the 50K will be supported by ISE WebPack. Also, does anybody know what the largest Spartan3 supported by the WebPack tools will be? ThanksArticle: 56788
I have the following error message in mapping stage. Anybody know how to encounter this error messages ? ERROR:MapLib:32 - lut4_l symbol "iRD/iCMA0" (output = signal=3DiRD/iCMA0/O) has an equation that uses an input pin connected to a trimmed signal. Make sure that all the pins used in the equation for this LUT have signals that are not trimmed (see trim report for details on which signals were trimmed). Thanks. Basuki Keren Ps: I am using ISE 5.1iArticle: 56789
Followup to: <a25b4de5.0306131111.412e82d8@posting.google.com> By author: TheCppMaster@aol.com (John) In newsgroup: comp.arch.fpga > > The kit seems to have nothing more than ethernet and serial (as far as > I/O). Is there some way to easily expand to add other I/O ports (PS/2, > USB, parallel, video, audio, ide, etc). I am looking for something > that will give me access to many of the industry standard I/O methods. > Well, it does have GPIOs, as well as CompactFlash. www.fpga.nl has a daughterboard with audio/video/PS2 mouse+keyboard that attaches to one of the two GPIO clusters. You should be able to just use the GPIOs directly as parallel (they're 3.3V LVTTL and 5V tolerant.) USB should also be reasonably easy to do with the GPIOs but might require some external passive components; I don't know. (For all I know hooking up two of the GPIOs, +5V and ground might make a perfectly acceptable USB interface.) -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 56790
"Wes." <spamthis@hayclan-oz.com> wrote in message news:RIKdnYeX9Omq9HijXTWcpw@giganews.com... > Hi All, > > I have several embedded system boards and one of them has a faulty MACH210A > IC and I am unable to get the data off the other boards due to the security > fuse on the IC is blown. Does anyone know if it is possible to overcome the > security fuse and recover the data? Are there any specialty companies that > can do this kind of work? > > Thanks in advance > > Wes. Thanks for the help, after drawing out what the Mach210 was doing I found it was a simple Chip Select function. It was using five address lines and some CPU control lines. Borrowed a Logic Analyser and with the help of our R&D hardware pro, reverse engineered its logic table. Cool, first time to play with Logic Analyser and writing PLD code <grin> Wes.Article: 56791
Hi, there was a TMS320C54 core on www.opencores.org. However, it is not in the projects list for some time now, but I think you can still track it on their CVS. I think it is not finished, maybe because they had legal problems with TI? BTW the company called CAST (www.cast-inc.com) has TMS320C25 IP core but it costs A LOT ): Goran > Just like the TI DSP or some simple DSP. > I heard that someone had develop TMS320 3x core.But I can't find it.Article: 56792
Hi guys,
Thanks all for the answers, very appreciated. When I say "image" I am
talking about "design" (I can't believe this is new therminology for FPGA
gurus :O) and to get the 605mW:
1) I wrote the RTL for a very symple design, a mux and considered that as an
almost empty design
2) Synthesized if with Synpl!fy
3) PARd with ISE in a XC2VP30-FG676-> NCD
4) I use NCD with XPower (5.2.02i) and I got 605mW, and this is what you
get:
Power summary: I(mA) P(mW)
----------------------------------------------------------------
Total estimated power consumption: 605
---
Vccint 1.5V: 400 600
Vcco 2.5V: 2 5
---
Nets: 0 0
Inputs: 0 0
Outputs: 0
Quiescent 1.5V: 400 600
Quiescent 2.5V: 2 5
So it's seems that the quiescent power is 605mW, a lot but as Peter Alfke
said:
Peter Alfke" <peter@xilinx.com> wrote in message
news:3EEA3E28.161260@xilinx.com...
> There is always a certain static or idle current consumption. It used to
> be very low (this is CMOS), only milliamps, but has gone up dramatically
> with the newer submicron processes. The supply voltage was reduced
> substantially, but the transistor threshold voltage cannot be reduced
> proportionally. The result is that the off-transistors are not perfectly
> turned off, each conducting fractional microamps in the off state. With
> many millions of transistors on the chip, this current adds up. This
> idle current increases with temperature, but is always there,
> independent of the configuration, and independent of the static data
> content. (Consider it the metabolism of the chip)
But I guess that you agree that is a lot for being just "standby".
To get the 1.2W I use the whole design, 68% of Slices are used in the chip
and parts of it are running @ 160MHz.
So when you have your FPGA powered up and it hasn't been programmed (no
"image" :o) this quiescent power is still consumed?
So my next question is, what will happen with Spartan 3? Smaller technology
but what about the transistor threshold voltage, has it been reduced
proportionally?
Ulises Hernandez
ECS Technology Ltd.
www.ecs-tech.com
Peter Alfke" <peter@xilinx.com> wrote in message
news:3EEA3E28.161260@xilinx.com...
> I don't know where you got the 1.2 W and 0.605 W from, and I do not know
> what you mean by "image".
> Anyhow:
> I assume that you have no strange dc loads on your outputs, and that the
> inputs are not left floating.
> There is always a certain static or idle current consumption. It used to
> be very low (this is CMOS), only milliamps, but has gone up dramatically
> with the newer submicron processes. The supply voltage was reduced
> substantially, but the transistor threshold voltage cannot be reduced
> proportionally. The result is that the off-transistors are not perfectly
> turned off, each conducting fractional microamps in the off state. With
> many millions of transistors on the chip, this current adds up. This
> idle current increases with temperature, but is always there,
> independent of the configuration, and independent of the static data
> content. (Consider it the metabolism of the chip)
>
> Once you run data through the FPGA, you also have dynamic charging and
> discharging of internal and also external capacitors, and the formula is:
> P = C times f times (Voltage squared). The voltage is Vcc, but C and f
> are specific to each internal node. Obviously, this dynamic power is
> proportional to the clock frequency. Calculating the effective C is far
> more complicated.
>
> Your total power is the sum of static and dynamic power.
>
> I have not divulged any secrets, and nothing here is Xilinx specific.
> Pentium, Virtex2Pro, Stratix and all other modern CMOS devices show the
> same behavior.
> Ultra-low static power consumption is not compatible with
> high-performance circuits using < 0.2 micron technology. We all have to
> learn to live with that. :-(
> Peter Alfke
> ================
> "U. Hernandez" wrote:
> >
> > Hi,
> >
> > I am using a Virtex-II Pro (XC2VP30-FG676) and need to estimate the
power
> > consumed by this chip for different stages:
> >
> > (Note that I don't have an eval board or the prototype board yet)
> >
> > 1) Normal operation, DONE with XPower (~1.2W, with blah, blah logic)
> >
> > 2) Blank Image, DONE (~605mW, the h*ll of a lot and is only what I've
got in
> > there, the QUIESCENT POWER is massive)
> >
> > 3) When is not configured, how can I do this?
> >
> > I'd use a uP to fetch data from Flash and 'upload' different images to
the
> > FPGA, I'd like to know what happens when is powered up but there is
nothing
> > on it.
> >
> > Thanks in advance
> >
> > Ulises Hernandez
> > ECS Technology Ltd.
> > www.ecs-tech.com
Article: 56793eternal_nan@yahoo.com (Ljubisa Bajic) writes: > You are right, I was refering to the v2 PRO. Incorrectly. > No probs. Looks like I may have to do some experimentation... Thanks anyway, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 56794
"Christian Widtmann" <e0125145@student.tuwien.ac.at> writes: > Hi! > > I'm trying to develop a PS/2-host in VHDL, whose entity naturally includes > the two inout-ports data and clock. Whenever the line is floating, the host > and the testbench both set it to high impedance = Z. That complies with the > PS/2-specification, and the synthesis log says that the pins are correctly > translatet into tri-state-pins. > > The problem is, I'm shifting the clock-signal into a 8-bit-FIFO to cope > with noise and spikes and to ensure that it is a real falling edge on the > clock-signal, but as soon as I shift the Z of the floating bus into the > FIFO the whole circuit goes nuts. This only happens after systhesis in > pre-layout-simulation, before that everything works fine. Same happens with > data, since I have to listen for a potential device's start-bit, which is > 0, and a falling edge on the clock, I have to listen to both lines all the > time, including the time they are Z. > In real life, if both host and device leave the line floating, a > pull-up-resistor would pull it to 1, so I tried to model this by the > testbench, leaving the line at H rather than Z, which should overwrite the > Z supplied by the host, which it did. But still, the same effect, just > after a clock-cycle of the fpga (30 MHz) in pre-layout-simulation both data > and clock turn from Z or H to X, along with some other signals, and this > propagates through the whole circuit. I don't know if this X on data and > clock is caused by some feedback from the curcuit or if they are the cause > for the Xs within the curcuit, so I'm not sure who is cause and who is > effect. > > Any ideas how to model this or how to model tristate-inout-pins with > pull-up-resistor in general? > You've got most of the way there - you just need to put a to_X01() translation between your bus pin and the logic that uses it. This will convert the 'H' on the bus from the 'pull-up-resistor' to a '1' that the logic can use. This can be tricky with the post-synth results as it means you'll have to track down the appropriate bits of code to insert your to_X01() call in. Maybe you can put some intermediate signals in your source with syn_keep attributes (or whatever *your* synthesiser uses) so that you can automate the inclusion of the function call with a script or something... HTH, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 56795
Sorry there was a typo in the previous post, these newbies....:O), see
further down about the metabolism stuff.
Hi guys,
Thanks all for the answers, very appreciated. When I say "image" I am
talking about "design" (I can't believe this is new therminology for FPGA
gurus :O) and to get the 605mW:
1) I wrote the RTL for a very symple design, a mux and considered that as
an
almost empty design
2) Synthesized if with Synpl!fy
3) PARd with ISE in a XC2VP30-FG676-> NCD
4) I use NCD with XPower (5.2.02i) and I got 605mW, and this is what you
get:
Power summary: I(mA) P(mW)
----------------------------------------------------------------
Total estimated power consumption: 605
---
Vccint 1.5V: 400 600
Vcco 2.5V: 2 5
---
Nets: 0 0
Inputs: 0 0
Outputs: 0
Quiescent 1.5V: 400 600
Quiescent 2.5V: 2 5
So it's seems that the quiescent power is 605mW, a lot but as Peter Alfke
said:
Peter Alfke" <peter@xilinx.com> wrote in message
news:3EEA3E28.161260@xilinx.com...
> There is always a certain static or idle current consumption. It used to
> be very low (this is CMOS), only milliamps, but has gone up dramatically
> with the newer submicron processes. The supply voltage was reduced
> substantially, but the transistor threshold voltage cannot be reduced
> proportionally. The result is that the off-transistors are not perfectly
> turned off, each conducting fractional microamps in the off state. With
> many millions of transistors on the chip, this current adds up. This
> idle current increases with temperature, but is always there,
> independent of the configuration, and independent of the static data
> content. (Consider it the metabolism of the chip)
But I guess that you agree that is a lot for being just "standby".
To get the 1.2W I use the whole design, 68% of Slices are used in the chip
and parts of it are running @ 160MHz.
In summary when you have your FPGA powered up and it hasn't been programmed
(no
"image" :o) this quiescent power is still consumed, as Peter said is like
the "metabolism of the chip", I like the expression.
So my next question is, what will happen with Spartan 3? Smaller technology
but what about the transistor threshold voltage, has it been reduced
proportionally?
Ulises Hernandez
ECS Technology Ltd.
www.ecs-tech.com
>
>
> Peter Alfke" <peter@xilinx.com> wrote in message
> news:3EEA3E28.161260@xilinx.com...
> > I don't know where you got the 1.2 W and 0.605 W from, and I do not know
> > what you mean by "image".
> > Anyhow:
> > I assume that you have no strange dc loads on your outputs, and that the
> > inputs are not left floating.
> > There is always a certain static or idle current consumption. It used to
> > be very low (this is CMOS), only milliamps, but has gone up dramatically
> > with the newer submicron processes. The supply voltage was reduced
> > substantially, but the transistor threshold voltage cannot be reduced
> > proportionally. The result is that the off-transistors are not perfectly
> > turned off, each conducting fractional microamps in the off state. With
> > many millions of transistors on the chip, this current adds up. This
> > idle current increases with temperature, but is always there,
> > independent of the configuration, and independent of the static data
> > content. (Consider it the metabolism of the chip)
> >
> > Once you run data through the FPGA, you also have dynamic charging and
> > discharging of internal and also external capacitors, and the formula
is:
> > P = C times f times (Voltage squared). The voltage is Vcc, but C and f
> > are specific to each internal node. Obviously, this dynamic power is
> > proportional to the clock frequency. Calculating the effective C is far
> > more complicated.
> >
> > Your total power is the sum of static and dynamic power.
> >
> > I have not divulged any secrets, and nothing here is Xilinx specific.
> > Pentium, Virtex2Pro, Stratix and all other modern CMOS devices show the
> > same behavior.
> > Ultra-low static power consumption is not compatible with
> > high-performance circuits using < 0.2 micron technology. We all have to
> > learn to live with that. :-(
> > Peter Alfke
> > ================
> > "U. Hernandez" wrote:
> > >
> > > Hi,
> > >
> > > I am using a Virtex-II Pro (XC2VP30-FG676) and need to estimate the
> power
> > > consumed by this chip for different stages:
> > >
> > > (Note that I don't have an eval board or the prototype board yet)
> > >
> > > 1) Normal operation, DONE with XPower (~1.2W, with blah, blah logic)
> > >
> > > 2) Blank Image, DONE (~605mW, the h*ll of a lot and is only what I've
> got in
> > > there, the QUIESCENT POWER is massive)
> > >
> > > 3) When is not configured, how can I do this?
> > >
> > > I'd use a uP to fetch data from Flash and 'upload' different images to
> the
> > > FPGA, I'd like to know what happens when is powered up but there is
> nothing
> > > on it.
> > >
> > > Thanks in advance
> > >
> > > Ulises Hernandez
> > > ECS Technology Ltd.
> > > www.ecs-tech.com
>
>
Article: 56796I have never used MSK files but here http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= 1&getPagePath=14468 it says that "this data should NOT be used to configure the device". I always go for BIT, RBT, EXO for PROMs, easy ones :O) Ulises Hernandez www.ecs-tech.com "Ed Stevens" <ed@stevens8436.fslife.co.uk> wrote in message news:bccnqc$9jc$1@newsg1.svr.pol.co.uk... > Hi, > > Im trying to program a Spartan 2E using the XILINX 4.2i software and iMPACT. > When I tell iMPACT to program the device I get the following error: > > > Device #1 selected > PROGRESS_START - Starting Operation. > Validating chain... > Boundary-scan chain validated successfully. > ERROR:Bitstream:2 - The input bitstream file > "C:\Xilinx\ISEexamples\intro\intro.msk" is not in the specified location. > Please check the correct location of the file. If the .bit file was not > created consult the "BitGen" Section in Chapter Twelve of the Development > System Reference Guide for the appropriate command-line options to create a > bitstream file or consult the "Implementation Options" Section of the Design > Manager/Flow Engine Reference/User Guide for Configuration Template > Settings. > ERROR:iMPACT:123 - Mask file C:\Xilinx\ISEexamples\intro\intro.msk is > invalid. > PROGRESS_END - End Operation. > Elapsed time = 2 sec. > => > > > Anyone got any ideas on what im doing wrong? In the XILINX Project > Navigator I've generated the programming file without any errors. > > Thanks for any help, > > >Article: 56797
"Martin Thompson" <martin.j.thompson@trw.com> schrieb im Newsbeitrag news:uptleeajt.fsf@trw.com... > You've got most of the way there - you just need to put a to_X01() > translation between your bus pin and the logic that uses it. This > will convert the 'H' on the bus from the 'pull-up-resistor' to a '1' > that the logic can use. Where would I have to put this? Into the original VHDL-code or into a file generated by synopsis' design_analyzer? Best regards.....Article: 56798
Hi,
Is there any way to implement Mux-DFF Logic( D-flop with 2-1 Mux at
the Data line, .. like scan flop.) "without" using the LUTs(for the
Mux logic..)in the CLBs for Virtex series FPGAs ?
Code:
-----------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rtl is
port(clk,d,se,sin: in std_logic;
y: out std_logic);
end rtl;
architecture arch of rtl is
begin
process(clk,se,sin,d)
variable new_d : std_logic;
begin
if(se='1') then
new_d := sin;
else
new_d :=d;
end if;
If(clk'event and clk='1') then
y <= new_d;
end if;
end process;
end arch;
--------------------------
Thanks,
Valli.
Article: 56799
HI Fellows,
The process given below is to read and write to Vertex device ( only
vhdl part is shown here not C ). I want to tristate SR_DATA_IO_int
when not driven as read.
First of all the code below for write and read is correct or not!!!!
SR_DATA_IO_int pins ( which are 32 , I am using upper 7 bits only )
will be acting as bi directional pins. While writing these will take
bits from PCI interface to device and while reading they will exactly
opposite. But while writing I have to tristate SR_DATA_IO_int so as to
avoid short circuiting. Any help on tristate will be highly
appreciated.
process(CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IRD_int,SR_IWR_int,SR_IVCS_V3_int)
begin
if RISING_EDGE(CLK_2X) then
if SR_IVCS_V3_int = '0' then
if SR_IWR_int = '0' then
if SR_ADDR_IO_int = "001100" then
RESULT <= SR_DATA_IO_int(6 downto 0);
End if ;
Elsif SR_IRD_int = '0' then
if SR_ADDR_IO_int = "001101" then
SR_DATA_IO_int(6 downto 0)<=RESULT ;
End if;
End if;
End if;
End if;
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