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Hi all, Other than Xilinx, are there any good online tutorials/references/projects that are helpful in learning Virtext II Pro ? Cheers, tkArticle: 56751
Hi! I'm trying to develop a PS/2-host in VHDL, whose entity naturally includes the two inout-ports data and clock. Whenever the line is floating, the host and the testbench both set it to high impedance = Z. That complies with the PS/2-specification, and the synthesis log says that the pins are correctly translatet into tri-state-pins. The problem is, I'm shifting the clock-signal into a 8-bit-FIFO to cope with noise and spikes and to ensure that it is a real falling edge on the clock-signal, but as soon as I shift the Z of the floating bus into the FIFO the whole circuit goes nuts. This only happens after systhesis in pre-layout-simulation, before that everything works fine. Same happens with data, since I have to listen for a potential device's start-bit, which is 0, and a falling edge on the clock, I have to listen to both lines all the time, including the time they are Z. In real life, if both host and device leave the line floating, a pull-up-resistor would pull it to 1, so I tried to model this by the testbench, leaving the line at H rather than Z, which should overwrite the Z supplied by the host, which it did. But still, the same effect, just after a clock-cycle of the fpga (30 MHz) in pre-layout-simulation both data and clock turn from Z or H to X, along with some other signals, and this propagates through the whole circuit. I don't know if this X on data and clock is caused by some feedback from the curcuit or if they are the cause for the Xs within the curcuit, so I'm not sure who is cause and who is effect. Any ideas how to model this or how to model tristate-inout-pins with pull-up-resistor in general? With best regards, Christian Widtmann Vienna University of TechnologyArticle: 56752
Hi Ulises, By "image" do you mean a design ? If so, there is no software tool for calculating design-dependent quiescent power for Virtex-II Pro. XPower can calculate design-dependent quiescent power for Virtex and Spartan-II families only. Brendan "U. Hernandez" wrote: > Hi, > > I am using a Virtex-II Pro (XC2VP30-FG676) and need to estimate the power > consumed by this chip for different stages: > > (Note that I don't have an eval board or the prototype board yet) > > 1) Normal operation, DONE with XPower (~1.2W, with blah, blah logic) > > 2) Blank Image, DONE (~605mW, the h*ll of a lot and is only what I've got in > there, the QUIESCENT POWER is massive) > > 3) When is not configured, how can I do this? > > I'd use a uP to fetch data from Flash and 'upload' different images to the > FPGA, I'd like to know what happens when is powered up but there is nothing > on it. > > Thanks in advance > > Ulises Hernandez > ECS Technology Ltd. > www.ecs-tech.comArticle: 56753
Hi I need to update my implementation options in ISE to "enable readback". However I cant find this option anywhere or anything referring to it on the Xilinx Support answers database. Any ideas? -- Cheers! MikeArticle: 56754
Hal, Cheap-shot. We take these things seriously. If a number is in the data sheet, then it has been reviewed as to how we can test for it. If we can not test it on the tester directly on 100 % of the parts, then we discuss how we can correlate it to another parameter that we can test directly. We then correlate the tester data with my bench data from the FPGA Lab. If we can not establish a correlation, then we have to go back and find another test that does correlate. If we just can't find a correlating test, then we have to either invent a new test, or do an AQL (separate test after the tester platform is done), or go back to IC Design and determine if there is sufficient margin in the design that we can safely ignore testing (ie "by design"). The proof and burden is on test to test everything, not on design to have huge margins so that we don't have to test (? bad philosophy for test, but good for yield). Further, if we test 1,000,000 parts, and a particular test always passes, why don't we just drop that test from the suite? It is common industry practice to drop tests that never fail, as what are they actually adding to the value, or the quality of the test (long time used by Western Electric...remember Demming?). If that test never fails, replace it with one that catches something, to improve the overall quality! So Peter is correct: if it is in the datasheet, then we must be able to have a test to support it, or a documented reason why not. Austin Hal Murray wrote: > > Also, IC manufacturers have this fixation that > >everything documented in the data sheet must be tested and guaranteed. > >Laudable idea, but it acts as a hindrance to documenting uncritical and > >untested parameters... > > I've seen lots of data sheets with "typical" numbers. > > There is another great footnote I see reasonably often > called "Guaranteed by design". > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 56755
Dear Philip and Other's I didn't find any difference between the constraints that work and the ones that don't. 1)( As suggested by you I reassigned some of the constraints that are working to the signals that are not working). I did this an I am getting the same error this means that the signal is not getting amy contraints value. The signal name is correct. 2) (As suggested by you, for the signal that are beign assigned correctly, change the pin number to one of the ones that isn't working). I tried this and it's work. It means that the pin number is correct and I have already checked this with the documentation provided by the manufacturer. The PCF file entry of the contraint that I am supplying using UCF file is given below. It has the constraint which I have entered in the UCF file. E.g: COMP "SR_DATA_IO<6>" LOCATE = SITE "P109" LEVEL 1; What you guys think whether this a problem of *.ngo file. As this file is being used by the NGDBUILD. Thnaking you in advance Rgds KhanArticle: 56756
Viral Parikh wrote: > Hi, > > I have some doubts in using External memory controller(EMC) for Off > chip memory in Xilinx Embedded Development Kit (EDK). > > Q:1 -> Can I use Off chip memory as CODE MEMORY to store my Code? Yes, you can, but you should notice the use of the data-width matching. We used plb_emc version 1.10.b to read from external flash. Although the datasheet tells to switch data-width matching OFF, we needed to switch data-width matching ON. To be able to write to the flash, we needed to tweak the chipselect and write strobes dependent on the byte enables. > Q:2 -> If yes, than how to initialize this external RAM, used as CODE > MEMORY, with my C code using EDK ? Just write to the associated address range ;-) Of course, when writing to flash you need to code the special flash enable sequences in your c-program. > Q:3 -> I don't find any API in given emc.c file to write/read to/from > external memory using EMC. I am expecting some API in C, which will > control activities of MB on OPB bus. Just same as API given in gpio.c > file to write through GPIO.(XGpio_DiscreteWrite/read)... You don't need them. Reading/writing to the associated memory range on PLB/OPB does the job. Regards, Rienk --- Rienk van der Scheer FPGA engineer 3T BV, http://www.3t.nl/Article: 56757
"Christian Widtmann" <e0125145@student.tuwien.ac.at> wrote in message news:bcchea$le3$1@news.tuwien.ac.at... > I'm trying to develop a PS/2-host in VHDL, whose entity naturally includes > the two inout-ports data and clock. Whenever the line is floating, the host > and the testbench both set it to high impedance = Z. That complies with the > PS/2-specification, and the synthesis log says that the pins are correctly > translatet into tri-state-pins. > > The problem is, I'm shifting the clock-signal into a 8-bit-FIFO to cope > with noise and spikes and to ensure that it is a real falling edge on the > clock-signal, but as soon as I shift the Z of the floating bus into the > FIFO the whole circuit goes nuts. This only happens after systhesis in > pre-layout-simulation, before that everything works fine. (snip) Since real signals are either 0 or 1, with the possible exception of the signal on the tri-state bus itself, there are some problems that occur only in simulation. Usually, though, for a properly designed circuit they will "shift out" after a reasonably number of clock cycles. If they don't you should figure out why, and fix it. Consider for example that a signal could be X, unknown. But if that signal is XORed with itself, you and I know the result will be 0, but the simulation will be X. -- glenArticle: 56758
"Brendan Cullen" <bcullen@xilinx.com> wrote in message news:3EE9D3E4.C98F23BB@xilinx.com... > Hi Ulises, > > By "image" do you mean a design ? If so, there is no software tool for > calculating design-dependent quiescent power for Virtex-II Pro. XPower can > calculate design-dependent quiescent power for Virtex and Spartan-II families > only. If a typical design has half the signals low and half high, I would expect the quiescent power to be relatively uniform over such typical designs. How much variation in quiescent power is due to process tolerance? (Between different fab runs of the same chip?) I would hope small, but ask anyway. -- glenArticle: 56759
I don't know where you got the 1.2 W and 0.605 W from, and I do not know what you mean by "image". Anyhow: I assume that you have no strange dc loads on your outputs, and that the inputs are not left floating. There is always a certain static or idle current consumption. It used to be very low (this is CMOS), only milliamps, but has gone up dramatically with the newer submicron processes. The supply voltage was reduced substantially, but the transistor threshold voltage cannot be reduced proportionally. The result is that the off-transistors are not perfectly turned off, each conducting fractional microamps in the off state. With many millions of transistors on the chip, this current adds up. This idle current increases with temperature, but is always there, independent of the configuration, and independent of the static data content. (Consider it the metabolism of the chip) Once you run data through the FPGA, you also have dynamic charging and discharging of internal and also external capacitors, and the formula is: P = C times f times (Voltage squared). The voltage is Vcc, but C and f are specific to each internal node. Obviously, this dynamic power is proportional to the clock frequency. Calculating the effective C is far more complicated. Your total power is the sum of static and dynamic power. I have not divulged any secrets, and nothing here is Xilinx specific. Pentium, Virtex2Pro, Stratix and all other modern CMOS devices show the same behavior. Ultra-low static power consumption is not compatible with high-performance circuits using < 0.2 micron technology. We all have to learn to live with that. :-( Peter Alfke ================ "U. Hernandez" wrote: > > Hi, > > I am using a Virtex-II Pro (XC2VP30-FG676) and need to estimate the power > consumed by this chip for different stages: > > (Note that I don't have an eval board or the prototype board yet) > > 1) Normal operation, DONE with XPower (~1.2W, with blah, blah logic) > > 2) Blank Image, DONE (~605mW, the h*ll of a lot and is only what I've got in > there, the QUIESCENT POWER is massive) > > 3) When is not configured, how can I do this? > > I'd use a uP to fetch data from Flash and 'upload' different images to the > FPGA, I'd like to know what happens when is powered up but there is nothing > on it. > > Thanks in advance > > Ulises Hernandez > ECS Technology Ltd. > www.ecs-tech.comArticle: 56760
You are right, I was refering to the v2 PRO. Incorrectly. Ljubisa Bajic ATI Technologies --- My opinions do not represent those of my employer --- Martin Thompson <martin.j.thompson@trw.com> wrote in message news:<u3ciee5bz.fsf@trw.com>... > eternal_nan@yahoo.com (Ljubisa Bajic) writes: > > > Hi All, > > > > You are right, the signalling used in DVI is not exactly lvds, it is > > current mode, but, as Peter Alfke mentioned in the other thread on > > this subject, the v2 differential drivers are highly programmable and > > I think that with some tweeking they can be made to output a signal > > that is acceptable by an DVI receiver chip. As far as the data rate > > concerns Martin E. had, v2's SERDES is more than capable of handling > > the data rates that are neccessary for DVI links (upto 3Gbits/s as far > > as I know should be fine with a v2). > > Is that data rate not for the MGT blocks on V2*Pro*? 840Mbps is the > max for basic V2 AFAIK. Ditto the configurability of the differential > drivers I think also? > > Cheers, > MartinArticle: 56761
On 13 Jun 2003 07:58:12 -0700, kalimuddin@hotmail.com (Muhammad Khan) wrote: >Dear Philip and Other's >I didn't find any difference between the constraints that work and the >ones that don't. >1)( As suggested by you I reassigned some of the constraints that are >working to the signals that are not working). I did this an I am >getting the same error this means that the signal is not getting amy >contraints value. The signal name is correct. The name may be correct, but the logic may be trimmed, so it no longer exists in your design. >2) (As suggested by you, for the signal that are beign assigned >correctly, change the pin number to one of the ones that isn't >working). I tried this and it's work. It means that the pin number is >correct and I have already checked this with the documentation >provided by the manufacturer. So the constraints you are writing are ok. >The PCF file entry of the contraint that I am supplying using UCF file >is given below. It has the constraint which I have entered in the UCF >file. >E.g: >COMP "SR_DATA_IO<6>" LOCATE = SITE "P109" LEVEL 1; >What you guys think whether this a problem of *.ngo file. As this file >is being used by the NGDBUILD. >Thnaking you in advance >Rgds >Khan I am almost certain that the problem you are having means that there is something in your code that is making the upper bits of your bus different from the rest. (for example, they don't exist, or have been renamed) If the signal name does not make it to the top level of your design in the instantiation record, the software treats it as unconnected, and then trims the net (and all logic connected to it). Since the signal name is trimmed, the constraint has nothing to attach to. You might also want to try a trivial test case design. For example a 32 bit counter, with a signal name that matches the names you are having trouble with. See if your constraint file works with it (may have to change the file name). Philip Philip Freidin FliptronicsArticle: 56762
Hi, Im trying to program a Spartan 2E using the XILINX 4.2i software and iMPACT. When I tell iMPACT to program the device I get the following error: Device #1 selected PROGRESS_START - Starting Operation. Validating chain... Boundary-scan chain validated successfully. ERROR:Bitstream:2 - The input bitstream file "C:\Xilinx\ISEexamples\intro\intro.msk" is not in the specified location. Please check the correct location of the file. If the .bit file was not created consult the "BitGen" Section in Chapter Twelve of the Development System Reference Guide for the appropriate command-line options to create a bitstream file or consult the "Implementation Options" Section of the Design Manager/Flow Engine Reference/User Guide for Configuration Template Settings. ERROR:iMPACT:123 - Mask file C:\Xilinx\ISEexamples\intro\intro.msk is invalid. PROGRESS_END - End Operation. Elapsed time = 2 sec. => Anyone got any ideas on what im doing wrong? In the XILINX Project Navigator I've generated the programming file without any errors. Thanks for any help,Article: 56763
Bram Stolk <b.stolk@chello.nl> wrote: > > I am looking for a compact (say 3x3") board that has both > RISC processor (preferably ARM or PPC) and a decent > FPGA chip. > Have you looked at the Intrinsyc uEngine products ?? Not exactly a bargin compared to the Cerfcube products though. http://www.intrinsyc.com/Merchant2/merchant.mv?Screen=CTGY&Store_Code=01&Category_Code=MICRO ADI Engineering's cheapest board looks nice (and much better value). It's a bit bigger than 3x3" though. http://www.adiengineering.com/ Please post a follow up if you do find something.Article: 56764
Hello, I would like to create a program to download the svf file to fpga, like gxsload from xess. Is there any library for that?any language Or any tip? Thank you in advance, Felipe NavesArticle: 56765
Hello, I just finished a course in VHDL. I should have probably got a kit earlier than using emulation tools all the way. I have decided to rectify that now. I am looking at this: http://www.nuhorizons.com/services/development/Xilinx/SpartanIIE/SpartanIIE Board.html I don't know what else I might need (expansion boards/cables). Please recommend me any better alternatives. Thanks a lot!!! -Sumeet (mailto:sumeet_p@yahoo.com) ps I am sorry if I didn't consult an FAQ for this group, please do point me to it.Article: 56766
Hi NG. I am using ISE5.2i and EDK 3.2 and tries to implement a MicroBlaze-design. The funny thing is that my design synthesizes fine, and I can even download it to my FPGA board (Virtex II) using the project navigator, the problem is that my written C-code does not get implented as well, so I have to download from the EDK software. When I do I get the error bellow. Anyone have an idea on what is wrong? As mentioned I can perfectly download a design to my board using the project navigator, but not with the EDK software, so I do not think it's my cable causing trouble :-( Command bash -c "cd /xygdrive/c/EDKproj1/; make -f system.make download; exit;" Started... ********************************************* Downloading Bitstream onto the target board ********************************************* impact -batch etc/download.cmd // *** BATCH CMD : setMode -bs // *** BATCH CMD : setCable -port lpt0 -baud 9600 Connecting to cable (Parallel Port - lpt1). Checking cable driver. Driver windrvr.sys version = 5.0.5.1. LPT base address = 0378h. Cable connection established. INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- INFO:iMPACT:1366 - Reading etc\xc18v04_vq44.bsd... INFO:iMPACT:1366 - Reading C:/Xilinx/xc18v00/data\xc18v04_vq44.bsd... INFO:iMPACT:501 - '1': Added Device XC18V04_VQ44 successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- INFO:iMPACT:1366 - Reading etc\xc18v04_vq44.bsd... ---------------------------------------------------------------------- // *** BATCH CMD : addDevice -position 1 -part etc/xc18v04_vq44.bsd // *** BATCH CMD : setAttribute -position 1 -attr configFileName -value etc/xc18v04_vq44.bsd INFO:iMPACT:1366 - Reading etc\xc18v04_vq44.bsd... INFO:iMPACT:1366 - Reading C:/Xilinx/xc18v00/data\xc18v04_vq44.bsd... INFO:iMPACT:501 - '1': Added Device XC18V04_VQ44 successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- INFO:iMPACT:1366 - Reading etc\xc18v04_vq44.bsd... '2': Loading file 'implementation/download.bit' ... done. INFO:iMPACT:1366 - Reading C:/Xilinx/virtex2/data\xc2v1000.bsd... INFO:iMPACT:501 - '2': Added Device xc2v1000 successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- // *** BATCH CMD : addDevice -position 2 -file implementation/download.bit // *** BATCH CMD : program -p 2 Validating chain... INFO:iMPACT:1209 - Testing for '0' at position 6.The Instruction capture of the device 1 does not match expected capture. INFO:iMPACT:1206 - Instruction Capture = '11111111110101' INFO:iMPACT:1207 - Expected Capture = '000XXX01XXXX01' ERROR:iMPACT:1210 - '1':Boundary-scan chain test failed at bit position '1'. A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. ---------------------------------------------------------------------- ---------------------------------------------------------------------- Done. Command bash -c "cd /xygdrive/c/EDKproj1/; make -f system.make init_bram; exit;" Started... make: Nothing to be done for `init_bram'. Done.Article: 56767
On Sat, 14 Jun 2003 06:43:45 +0000 (UTC), SP <nowhere@nowhere.com> wrote: >Hello, > >I just finished a course in VHDL. I should have probably got a kit >earlier than using emulation tools all the way. I have decided to >rectify that now. I am looking at this: >http://www.nuhorizons.com/services/development/Xilinx/SpartanIIE/SpartanIIE >Board.html > >I don't know what else I might need (expansion boards/cables). Please >recommend me any better alternatives. > >Thanks a lot!!! >-Sumeet (mailto:sumeet_p@yahoo.com) > >ps I am sorry if I didn't consult an FAQ for this group, please do point me >to it. Here you go: www.fpga-faq.com Also has a section on available boards. Philip =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 56768
hi, I like to know, Which adder architecture(like .. CLA,Ripple,CSM,BK-adder,ROM-method) is more suitable for targeting to Xilinx Virtex-2 FPGA for time/area/both ? Regards, Valli.Article: 56769
Hi, I have instantiated two Virtex II DCMs using the language templates in ISE4.1. When I try to compile the design, Synplify complains about not being able to map the type "Real", and quits. So I put a pair of --synopsis translate_off/on terms around the attribute declaration and it compiles fine, but I note in the report that it has used a divisor of 2, not 16 as I requested, but that's to be expected. If I use modelsim to simulate the original VHDL code, it works correctly, dividing by 16. But the post-map and post-p&r models divide by two. What am I doing wrong? Why does Synplify not understand the attributes? Thanks.Article: 56770
That board is made by digilentinc.com and you can get an add-on board from them also. All the cables were includes for the ones I bought. "SP" <nowhere@nowhere.com> wrote in message news:Xns939A11957CC08nowherenowherecom@216.109.160.14... > Hello, > > I just finished a course in VHDL. I should have probably got a kit > earlier than using emulation tools all the way. I have decided to > rectify that now. I am looking at this: > http://www.nuhorizons.com/services/development/Xilinx/SpartanIIE/SpartanIIE > Board.html > > I don't know what else I might need (expansion boards/cables). Please > recommend me any better alternatives. > > Thanks a lot!!! > -Sumeet (mailto:sumeet_p@yahoo.com) > > ps I am sorry if I didn't consult an FAQ for this group, please do point me > to it.Article: 56771
On 14 Jun 2003 04:12:31 -0700, sri_valli_design@hotmail.com (Valli) wrote: >hi, > >I like to know, Which adder architecture(like .. >CLA,Ripple,CSM,BK-adder,ROM-method) is more suitable for targeting to >Xilinx Virtex-2 FPGA for time/area/both ? >Valli. All Xilinx Virtex, Virtex-II, Virtex-II-P, Spartan, Spartan-II, and Spartan-III have built-in carry-chain logic, that implements very fast ripple carry. In VHDL or Verilog, just use "+" . The synthesis programs all know how to make use of the built-in structures, so you don't have to do anything specific to target this. Although the various other structures you mention can give better results than ripple-carry in other technologies (such as full custom silicon, or gate array), this is almost never the case for Xilinx FPGAs. Philip Freidin Philip Freidin FliptronicsArticle: 56772
Okay, think I worked it out. it seems that Synplify 7.1 doesn't support real attributes. Is there a workaround? Or must I use v.7.22 to be able to compile this? Thanks. On Sat, 14 Jun 2003, Suhaib Fahmy wrote: >Hi, > >I have instantiated two Virtex II DCMs using the language templates in >ISE4.1. When I try to compile the design, Synplify complains about not >being able to map the type "Real", and quits. So I put a pair of >--synopsis translate_off/on terms around the attribute declaration and >it compiles fine, but I note in the report that it has used a divisor of >2, not 16 as I requested, but that's to be expected. > >If I use modelsim to simulate the original VHDL code, it works >correctly, dividing by 16. But the post-map and post-p&r models divide >by two. > >What am I doing wrong? Why does Synplify not understand the attributes? > >Thanks. >Article: 56773
As long as you are upgrading I suggest that you go to 7.3 . You should also be able to use generics directly instead of generics and attributes. Suhaib Fahmy wrote: > Okay, think I worked it out. it seems that Synplify 7.1 doesn't support > real attributes. Is there a workaround? Or must I use v.7.22 to be able > to compile this? > > Thanks. > > > On Sat, 14 Jun 2003, Suhaib Fahmy wrote: > > >>Hi, >> >>I have instantiated two Virtex II DCMs using the language templates in >>ISE4.1. When I try to compile the design, Synplify complains about not >>being able to map the type "Real", and quits. So I put a pair of >>--synopsis translate_off/on terms around the attribute declaration and >>it compiles fine, but I note in the report that it has used a divisor of >>2, not 16 as I requested, but that's to be expected. >> >>If I use modelsim to simulate the original VHDL code, it works >>correctly, dividing by 16. But the post-map and post-p&r models divide >>by two. >> >>What am I doing wrong? Why does Synplify not understand the attributes? >> >>Thanks. >> >>Article: 56774
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