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"Martin Schoeberl" <martin.schoeberl@chello.at> schreef in bericht news:6GGIa.34485$RM6.474195@news.chello.at... > Since Leonardo is not longer available from Altera I'm trying to use Quartus > for synthesis. You are lucky here. We have a similar problem however our board used during the lab contains a MAX7000S device which is not (yet) supported by Quartus II. > problem down and now my qustion is: Is it a bug or sloopy written VHDL? > > The problem is setting output to tristate. See following VHDL code: I asumed > that it is ok when the databus (d) is set to 'Z' in state 'idl' and this > will not change when changing state to 'rd1'. This was ok with Leonardo. But > with Quartus I have to set d to 'Z' again in every state. What is the > correct VHDL code? Indeed if d is not set a new value in state rd1 it will remain its value. Therefore I would expect a latch in the design if not explicitly a value is set to d in every state. (A latch is needed to remember the value assigned to d in the previous state). However since I'm assume that you want the value of d be tri-state I would write <= "ZZZZZZZZ"; in such a state. (Maybe in your description Leonardo could optimize your design where the latch is not needed?) Egbert MolenkampArticle: 57001
This is the last frame write. It tells the configuration state machine that the last frame is being written get ready for startup. When they dropped this command from the Virtex 2 things got a little better. Steve > ***************ADDITONAL FAR WRITE.******** > Write the CRC check value into the CRC. > Write the LFRM command to the CMD register. > Write one dummy frame to the FDRI register. > Write the START command to the CMD register. > Write the CRC value into the CRC. > Clock the startup.Article: 57002
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3EF23D11.2572E620@yahoo.com... > The EP1C4 is a fairly small member of the Cyclone family, but they used > a staggered IO cell arrangement. Xilinx might consider doing an XC3S200 > like this with a higher IO count. I assume this could be done and still > keep the price much lower than the XC3S400. The Spartan-3 devices are already using the staggered pad configuration. It's Altera that was slow on the uptake - the EP1C4 will be available long after the first 4 members of the Cyclone family. I agree with you that low I/O to logic ratios don't work for many of us and that "buying up" just for the pin count is very annoying. I've done it with a few designs now. While there's little hope to squeeze more out of the Spartan-3 or the Cyclone family beyond what's announced, I'm looking forward to the NextGen products producing a more "optimum" available I/O to Logic ratio.Article: 57003
FAQ: Spartan 2 is Virtex 1 and Spartan 3 is Virtex 2 all of which support partial reconfiguration. Atmels chips are also partial. I'm not sure about Triscend. Any sram based FPGA should support partial. I'm sure the QuickSliver chips are. I would bet that Alteras do but they just won't tell. Steve "Moisés" <m_perez_gutierre@hotmail.com> wrote in message news:97f0ebf9.0306191408.5893a246@posting.google.com... > Does anybody knows what kind of devices actually support partial > reconfiguration. I know that the Xilinx Virtex do it and I'm not sure > if the Spartan3 will suppport it. > > Thanks in advance.Article: 57004
Frank Zampa wrote:
>
> I have eight bank of 16x1 dual port RAM. When i read the data (DPO)
> from the bidirectional bus(eight lines INOUT) the electrical signals
> are good, except when all the bits are at "1".
>
>
> For example, when i measure with the oscilloscope one line when i'm
> reading the signal is perfect
> ____
> __| \___
>
> when all the bits are at "1" the same signal is bad
> __
> __WWW \____
>
> If i turn off one of the others lines the signal return good.
>
> Whe i read data from other sources different from RAM i don't have
> this problem.
Try a better power supply and do walking 1 and walking 0
bit test to make sure it's wired up right.
-- Mike Treseler
Article: 57005
Hi Martin!
> The problem is setting output to tristate. See following VHDL code: I asumed
> that it is ok when the databus (d) is set to 'Z' in state 'idl' and this
> will not change when changing state to 'rd1'. This was ok with Leonardo. But
> with Quartus I have to set d to 'Z' again in every state. What is the
> correct VHDL code?
The better readable VHDL code for a flipflop-based state machine and a
tri-state output is the splitting of both:
-- state machine
process(reset,clk)
begin
if (reset='1') then
state <= idl;
elsif rising_edge(clk) then
case state is
when idl =>
if (mem_rd='1') then
a <= din(16 downto 0) & "00";
nram_cs <= '0';
ram_access <= '1';
i := ram_cnt;
nrd <= '0';
state <= rd1;
elsif (mem_wr='1') then
...
when rd1 =>
i := i-1;
if (i=0) then
state <= rd2;
mem_din(7 downto 0) <= d;
a(1 downto 0) <= "01";
i := ram_cnt;
end if;
when rd2 =>
-- and so on ..
end process;
-- tri-state output
process(state)
begin
if (state=idl OR state=rd1 OR ....)
a<=(others=>'Z')
d<=(others=>'Z');
else a<= ....
d<= ....
end if;
end process;
As you can see the tri-state output has to be combinational logic. I
could also write
a<=(others=>'Z') when (state=idl OR state=rd1 OR ....) else ....;
In your solution it is nessecary to set the value of the ouptuts in
every state, because the synthesis tool will recognize it as the same
like my solution: flipflops for the state machine, that decide whether
the output is 'Z' or not. There is no "tri-state-flipflop".
Ralf
Article: 57007Hello all, I am currently using Xilinx's Webpack ISE 5.2.3 to work on a dma_controller portion of a project. When I synthesize the project, the tool seems to take a long time synthesizing and optimizing the dma_controller code. The end result, is that the project takes 11 minutes to compile. I am trying to look for ways to reduce this compile time. This dma contoller involves two main state machines that perform handshakes with several smaller state machines in order to minimize repetitive states. The main state machines advance state on the positive edge of the clock, while the smaller state machines advance state on the clock's negative edge. The main state machines "call" the smaller state machines by setting an enable register and waiting in a state until the done register is set by the "called" sub machine. Is there a better way to subdivide state machines? Perhaps, calling tasks/functions or separating the state machines into separate .v files? Any help will be greatly appreciated! -AlbertArticle: 57008
The frequency division can be done by any FPGA, but in order to generate the exact frequencies, you either need to start at 24 MHz, or you make the divider more sophisticated, so that it divides by a sequence of smaller numbers. No problem whatsoever. For the FIFO, just pick an FPGA with a decent-size dual-port BlockRAM. XC2S15, the smallest Xilinx Spartan-II would be an excellent candidate. It has four 1k x 4 BlockRAMs, and you just use 2 in parallel. There are over 400 flip-flops with fast carry chains between them. Peter Alfke ============================ Moises Cambra wrote: > > We would like to generate multiple and different clock frequencies from a > single clock source. For example, from 8MHz obtain eight clock outputs of > arbitrary frequencies like 192KHz, 38400Hz, 9600Hz, etc. Basically, it could > be done with one counter/comparator for each output, with output toggle and > reset of the counter when it equals the value of the comparator. The values > of the comparison have to be loaded externally from a microcontroller to > change the frequencies from time to time. > > Apart from this, it would be nice if the same device could include a FIFO of > 1 or 2 Kbytes deep. > > Since it will be the first time we use programmable logic and we don't have > yet any development tool, my question is: what family/product would you > recommend for this application? Power consumption is important. If the FIFO > means to jump to a too big thing, we could stuck with the discrete FIFO... > > Thanks, > MoisesArticle: 57009
Paul Urbanus schrieb: > I have two old designs - from 1987 - that I wrote in ABEL (by Data I/O) > that fit into a PAL20L8 and a PAL20L10. I want to program some new parts > with these designs, but only have GAL20V8 and GAL22V10 parts available. > > According to a Lattice Semi data sheet, there parts are supposed to be > fuse compatible with all of the parts they replace. So, in theory I > should be able (pardon the pun) to use the PAL20L10 JEDEC file to > program the GAL22V10 and the PAL20L8 JEDEC file to program the GAL20L8. Do you have the Abel source or can you "redo" it ? > > Anyone have any experience in this matter who can say, "Yes, it will > work, or, no way in Hades this will work?" > > On a related note, does anyone know if the old DOS version of ABEL is in > the public domain? And if so, where I can download a new version. as far as i know it is not supported anymore since many years and therefore practically "quasi public" .. may be i am not juristicallly correct. have you looked at "LATTICE ISP LEVER STARTER" ? it may support your devices, about 22v10 i am pretty shure greetings, Bertram > ______________________________________________________________________ > Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com > <><><><><><><> The Worlds Uncensored News Source <><><><><><><><> > -- Bertram Geiger <bgeiger@aon.at> HTL-Bulme Graz, AustriaArticle: 57010
Hi Ralf, > In your solution it is nessecary to set the value of the ouptuts in > every state, because the synthesis tool will recognize it as the same > like my solution: flipflops for the state machine, that decide whether > the output is 'Z' or not. There is no "tri-state-flipflop". But a flip flop for the output enable could get synthesized from the VHDL code without an asignement in every state. I'm still not sure if the code was 'wrong' or not. Martin -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/Article: 57011
Dear Frank:
I usually have this problem when I forget to hook the ground up between
two chips or two boards. This is very reminiscent of a missing ground where
the reason it works is the line which is at '0' is providing a *virtual*
ground.
Just a guess on my part, but this sure looks familiar.
Charles
"Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message
news:3EF34441.1000004@flukenetworks.com...
>
>
> Frank Zampa wrote:
>
> >
> > I have eight bank of 16x1 dual port RAM. When i read the data (DPO)
> > from the bidirectional bus(eight lines INOUT) the electrical signals
> > are good, except when all the bits are at "1".
> >
> >
> > For example, when i measure with the oscilloscope one line when i'm
> > reading the signal is perfect
> > ____
> > __| \___
> >
> > when all the bits are at "1" the same signal is bad
> > __
> > __WWW \____
> >
> > If i turn off one of the others lines the signal return good.
> >
> > Whe i read data from other sources different from RAM i don't have
> > this problem.
>
>
> Try a better power supply and do walking 1 and walking 0
> bit test to make sure it's wired up right.
>
> -- Mike Treseler
>
Article: 57012Followup to: <3EF32F73.10C2E05E@yahoo.com> By author: rickman <spamgoeshere4@yahoo.com> In newsgroup: comp.arch.fpga > > > > This is the ISA side. We're using the PCI side. > > Then we are talking about two different animals. I belive PCI muxes > addr and data on the same 32 pins, so that saves a lot. But that would > be PC/104+, not PC/104. > Right. I was stating PC-104+ in every single message. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 57013
Albert Tsai wrote:
> I am currently using Xilinx's Webpack ISE 5.2.3 to work on a
> dma_controller portion of a project. When I synthesize the project,
> the tool seems to take a long time synthesizing and optimizing the
> dma_controller code. The end result, is that the project takes 11
> minutes to compile. I am trying to look for ways to reduce this
> compile time.
>
> This dma contoller involves two main state machines that perform
> handshakes with several smaller state machines in order to minimize
> repetitive states. The main state machines advance state on the
> positive edge of the clock, while the smaller state machines advance
> state on the clock's negative edge.
Webpack probably wouldn't have to think
so hard, if everything happened on
the rising edge of the clock.
-- Mike Treseler
Article: 57014The answer to your first question is no, the 20L8 and 20L10 are not fuse compatible with the 22V10 or the 20V8 so you will have to refit the design. The good news is that Lattice's tools read in ABEL directly as they bought it from Data I/O several years ago. You should be able to read in the designs and as long as you don't have your pins locked down, refit them into the newer devices. Paul Urbanus <urbpublic@hotmail.com> wrote in message news:<3EF31484.8060904@hotmail.com>... > I have two old designs - from 1987 - that I wrote in ABEL (by Data I/O) > that fit into a PAL20L8 and a PAL20L10. I want to program some new parts > with these designs, but only have GAL20V8 and GAL22V10 parts available. > > According to a Lattice Semi data sheet, there parts are supposed to be > fuse compatible with all of the parts they replace. So, in theory I > should be able (pardon the pun) to use the PAL20L10 JEDEC file to > program the GAL22V10 and the PAL20L8 JEDEC file to program the GAL20L8. > > Anyone have any experience in this matter who can say, "Yes, it will > work, or, no way in Hades this will work?" > > On a related note, does anyone know if the old DOS version of ABEL is in > the public domain? And if so, where I can download a new version. > > Of course, I could always recode the PALS in VHDL using the Cypress Warp > software, which used to support the 22V10, at least. > > Thanx > > > ______________________________________________________________________ > Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com > <><><><><><><> The Worlds Uncensored News Source <><><><><><><><>Article: 57015
Hi, Im getting the following error in the XILINX Project Navigator: ERROR:MapLib:93 - Illegal LOC on symbol "w_clk" (pad signal=w_clk) or BUFGP symbol "w_clk_BUFGP" (output signal=w_clk_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site. How can I assign w_clk to a general purpose I/O pin, rather than one of the clock inputs? Thanks for any help,Article: 57016
I've designed a board to use the PQ240-packaged EP1C12 when it is available. Since it isn't yet, I'd like to put an EP1C6 in there in the mean time. Unforutnately, the pinouts don't match exactly. The EP1C12 has fewer IOs and more power lines. If I make the "new" IOs on the EP1C6 (which were power pins on the EP1C12) into inputs, will everything be safe? Is there anything else I need to account for? Thanks MattArticle: 57017
Hello all I am in the process of configuring an FPGA using the Parallel port of a PC. My board also has a socket for a xilinx parallel programming cable(Parallel cable IV). This works fine and configures the device for me. What I am trying to do now is get my own software to configure the FPGA through a standard parallel cable. The device is a spartan XL XCS05XL. SO far I've used details from xilinx app note on "Configuring FPGAs over a processor bus." Well my software is not configuring the device. One thing that seems odd is that I don't seem to be able to drive the DIN pin low. I can get it down to about 1V but no lower. I thought it might be the pin I was using from the control port of the parallel port but I started using a pin from the data port with no benefit. On this device the DIN and DOUT pins are the same. I suppose if I got a schematic of the Parallel IV cable I would see what I was doing wrong. Any suggestions? Thanks in advance for all assistance. DenisArticle: 57018
"H. Peter Anvin" wrote: > > Followup to: <3EF32F73.10C2E05E@yahoo.com> > By author: rickman <spamgoeshere4@yahoo.com> > In newsgroup: comp.arch.fpga > > > > > > This is the ISA side. We're using the PCI side. > > > > Then we are talking about two different animals. I belive PCI muxes > > addr and data on the same 32 pins, so that saves a lot. But that would > > be PC/104+, not PC/104. > > > > Right. I was stating PC-104+ in every single message. I see now that you mentioned in the middle of a message that you were not using the ISA signals. I missed that. I can see that it could be a better way to handle the PCI interface. But it still depends on where the IO count pushes your part selection. If you can accommodate the extra IOs on the large FPGA then this can be a better way to do it. If you need to go to a larger chip, it can be very pricey compared to adding a smaller FPGA. I am curious, do the switch parts you chose meet all the PCI bus requirements when used with a low voltage FPGA? I know the IO specs on PCI are very particular on rise time and waveform specs. Typically it requires that the IO on a chip be spec'd for the application. Were you able to confirm that this combination meets the spec? And what FPGA are you using? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57019
John_H wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3EF23D11.2572E620@yahoo.com... > > The EP1C4 is a fairly small member of the Cyclone family, but they used > > a staggered IO cell arrangement. Xilinx might consider doing an XC3S200 > > like this with a higher IO count. I assume this could be done and still > > keep the price much lower than the XC3S400. > > The Spartan-3 devices are already using the staggered pad configuration. > It's Altera that was slow on the uptake - the EP1C4 will be available long > after the first 4 members of the Cyclone family. I'm not sure what you mean by "slow on the uptake". The EP1C4 is a newer version of the chip which has a higher IO to LE ratio compared to their standard mix. Once they released info on the Cyclone line they got feedback asking about a higher IO count on a lower end chip. Seems to me they turned the crank pretty quick on this part and are very confident on the development schedule. > I agree with you that low I/O to logic ratios don't work for many of us and > that "buying up" just for the pin count is very annoying. I've done it with > a few designs now. > > While there's little hope to squeeze more out of the Spartan-3 or the > Cyclone family beyond what's announced, I'm looking forward to the NextGen > products producing a more "optimum" available I/O to Logic ratio. That won't happen unless they start changing the way they do IO. I have read about a few companies that have a method of putting the IO pad on top of the logic. This will pretty much eliminate the perimeter length issue in determining how many IOs a chip can have. So far none of the PLD makers have adopted this method. I hope they catch on to this newer technology. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57020
Hi fellows, I want to ask about any way to use an FPGA (xilinx) board without a logical analyzer and still can see all the waves. Is there any software that can be used with a board that is connected to a simple PC? thanks -- Composed with Newz Crawler 1.4 http://www.newzcrawler.com/Article: 57021
Steve Casselman wrote: > > FAQ: > Spartan 2 is Virtex 1 and Spartan 3 is Virtex 2 all of which support partial > reconfiguration. Atmels chips are also partial. I'm not sure about Triscend. > Any sram based FPGA should support partial. I'm sure the QuickSliver chips > are. I would bet that Alteras do but they just won't tell. > > Steve > > "Moisés" <m_perez_gutierre@hotmail.com> wrote in message > news:97f0ebf9.0306191408.5893a246@posting.google.com... > > Does anybody knows what kind of devices actually support partial > > reconfiguration. I know that the Xilinx Virtex do it and I'm not sure > > if the Spartan3 will suppport it. > > > > Thanks in advance. There is a big difference to supporting "partial reconfiguration" in hardware and in software. Sure, the chip will let you download new data to part of the chip. But if the software has no means of generating a design that share the chip in a cooperative way, it can be exceedingly difficult to produce a design that can be partially downloaded. Our board uses the FPGA as an interface to daughterboards which contain IO. We have looked into this issue and unless we want to do a lot of programming ourselves, there is no solution from anyone. I rank this problem up there with the issues of using JTAG for boundary scan. This is not so much an issue with the FPGAs, but the CPUs and DSPs don't like to be debugged when anythign else is in the chain. Someone is just not paying attention to the customers. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57022
In article <3EF39237.ACC68E6D@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >> While there's little hope to squeeze more out of the Spartan-3 or the >> Cyclone family beyond what's announced, I'm looking forward to the NextGen >> products producing a more "optimum" available I/O to Logic ratio. > >That won't happen unless they start changing the way they do IO. I have >read about a few companies that have a method of putting the IO pad on >top of the logic. This will pretty much eliminate the perimeter length >issue in determining how many IOs a chip can have. So far none of the >PLD makers have adopted this method. I hope they catch on to this newer >technology. Area pads (C4 solder ball style) flip-chips have been fairly common in the microprocessor world for a while. However I think they are still a lot more costly than lead frame or FC-lead frame packaging, which is a big BIG deal on the cost-sensitive parts. What I'd like to see is two versions, one which uses C4 solderballs to mount to a very high pincount frame, and the other (which only populates 1/4 of the pads) as a chip-scale BGA which uses wafer-level packaging to lower the package cost and provide for a decent amount of I/Os in a small footprint. But that may be a fair bit away in the future. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 57023
Thomas <tom3@protectedfromreality.com> wrote in message news:<oprq2qzaummo2d8p@news3.news.adelphia.net>...
> I have also a similar thread in comp.arch.fpga;
>
> apparently my code works well when the inout signal is used in the fpga;
> only when I assign the signal to a pin the simulation starts to fail.
> I am using HDL bencher to generate the testscript and I wonder if it could
> be the reason: I set some values to be read with hdl bencher, and then it
> verifies every clock cycle the values are still there, but in the meantime,
> I might have switched the signal to output
>
> what do you think?
I never used HDL bencher. Not clear as to exactly what you are saying.
If I understand you correctly, the testbench checks for an expected
value at every clock, and drives the inout signal with a hard value
('1' or '0') even when that port is in the "out" mode, rather than the
"in" mode. Thus, the TB is not driving Zs. If that is the case,
the TB is definitely in error.
For the record, In TB design I generally use my own client/slave model
instead of a commercial product. That is described in my books.
I am now moving toward assertion-based verification (ABV), and really
liking PSL, property specification language, along with dynamic
simulation verification. I'll be exploring static, or formal
verification soon. ABV with PSL and simulation helps define design
intent, expected operation, and alerts of errors. PSL eases the
design of the TB because it puts more of the "verifier" design onto
PSL, instead of a user defined model.
Ben
>
> On 19 Jun 2003 18:38:16 GMT, VhdlCohen <vhdlcohen@aol.com> wrote:
>
> >> modelsim shows my BUS_Data signal as conflicts all through the
> >> simulation;
> > You seem to have an error in a driving value from one of your drivers.
> > The best way to debug this is to run the simulation until you get a
> > conflict,
> > and then type: drivers bus_data That will show you the source of each of
> > the drivers, and you can then get to
> > the root of it. What you have looks OK, but without a full understanding
> > of the design, it is
> > difficult for me to find the error. The "drivers" command would be the
> > first
> > thing I would try. ------------------------------------------------------
> >
> >
> > ----------------------
> > Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
> > http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following
> > textbooks: * Using PSL/SUGAR with Verilog and VHDL
> > Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
> > * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
> > 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1
> > * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-
> > 8474-1
> > * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-
> > 8115
> > --------------------------------------------------------------------------
> >
> >
> > ----
> >
> >
Article: 57024On 20 Jun 2003 14:53:16 -0700, matt@ettus.com (Matt Ettus) wrote: >I've designed a board to use the PQ240-packaged EP1C12 when it is >available. Since it isn't yet, I'd like to put an EP1C6 in there in >the mean time. Unforutnately, the pinouts don't match exactly. The >EP1C12 has fewer IOs and more power lines. If I make the "new" IOs on >the EP1C6 (which were power pins on the EP1C12) into inputs, will >everything be safe? Is there anything else I need to account for? > >Thanks >Matt www.arrow.com shows the 810 pieces of EP1C12Q240C8 available for immediate online ordering. in April/May I received an inventory list from arrow indicating all three speeds of this part in the Q240 were in stock so either the website didn't list them or folks have started buying them up Khim Bittle
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