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> but these are SIMD, not-GP, registers. As far as I know, its the same core of the Toshiba TX7901 micro processor, and it has 32 (of course, itīs a MIPS) 128 bit registers, although the two integer units are 64 bits wide. Only the SIMD intructions use all 128 bits (32bitx4, 16 bitX8 or 8bitx16 data types). There are no special porpouse SIMD registers. Luiz Carlos.Article: 57476
"black" <mini_monkey@163.net> wrote in message news:bdrkmo$vq2ne$1@ID-199450.news.dfncis.de... > The reason for using FPGA's dedicated > clock distribution resources is > that there is no clock skew in these resources,is that right? There is always *some* skew, but whatever it is, the FPGA manufacturer guarantees that if you use the dedicated clock network then you will never suffer from the skew-related race condition that we discussed. When designing ASICs and custom ICs, you achieve the same result by using specialised clock tree insertion software. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 57477
I am reposting after a memo from reader siting problems using the Xilinx link to post to this group. Sorry about any problems this may have caused. After the release of Alliance 3 support was no longer offered for the XC3xxx family. Worse, if you did not happen to have the original software that supported these devices, Xilinx would not sell you a copy. Even today we still have product that uses the 3xxx family. I am looking at upgrading our group to Allience 5.x and again see that Xilinx has dropped all support for Spartan. Other families were dropped as well. We would now need three copies of software running to support the Xilinx devices we use. Of course, not all the Xilinx tools like to be co-installed, so it's multiple computers or swap installs. Xilinx, what is your problem? Altera may drop parts, but their router continues to support all of their devices. Is your software so poorly written that it is so difficult to maintain parts that you need to drop them? I could understand if the parts were no longer available, or you at least sold older copies of your software.Article: 57478
"Triax" <malvric@starhub.net.sg> wrote in message news:3f0163ff@news.starhub.net.sg... > Hello, > I have written a program to run on the Celoxica RC100 board and compiled > it to edif file. When i use the Xilinx Design Manager to convert it to a bit > file, > it always fail during the mapping stage saying it cannot fit into the > device. > I have tried many optimzation method in the DK1 suite and nothing works. > Tried using its technology mapper (take very long to compiler) also cannot > work. > And it always exceed the maximum slices and 4 i/p look-up table (both exceed > by 50%). I have tried the -r option in the mapping and it still exceed. > > I'm using the following software, > Celoxica DK1 Design Suite 1.1 Service Pack 1, compiler version 3.1.2676 > Xilinx Design Manager Revlease version 3.3.08i, application version D.27 > > Thanks you > from Triax > > If you target EDIF, you can get a report on the area and timing of your design. You have to enable Generate Estimation Info on the Linker tab in your project settings. This should help you track down which parts of your design take most area, and concentrate on optimizing those. Of course you may find that your design cannot fit in the Spartan II on the RC100 board, in which case you will either have to simplify your design, or use a different board, regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 57479
benn686@hotmail.com (Ben Nguyen) wrote in message news:<e604be8.0306302332.78399fc7@posting.google.com>... > When is Quartus version 3 coming out? > Hi, My sources tells me late June worst case early August. (They are allready posting app notes on new features on Alteras homepage!) /Fredrik > > fredrik_he_lang@hotmail.com (Fredrik) wrote in message news:<77a94d51.0306300026.7c3b3c8@posting.google.com>... > > Hi Ben, > > It is possible at the moment to build a Nios for FLEX10KE family with > > the SOPC builder. But since you talking about 70kgate FLEX I am > > guessing you are looking at FLEX10K (5.0V) family. This family is not > > at the moment supported in Quartus hence not supported for Nios. But > > the new release of Quartus version 3 will have support for 5.0 familys > > such as flex10k and max7000s (way to go Altera) according to the > > Altera web page. So my guess is that there will be support for FLEX10K > > and Nios in the next release. There is no limites on the number of ram > > needed with Nios, as long as you have more than 2000LE's you should be > > able to build a decent Nios system in any non CPLD family from Altera. > > Cheers > > Fredrik > > benn686@hotmail.com (Ben Nguyen) wrote in message news:<e604be8.0306281332.23e027a8@posting.google.com>... > > > Since Altera only sells Stratix, Cyclon, and APEX kits for their Nios, > > > can Quartus II synthesize the Nios on a small (70k gates) FLEX device? > > > > > > Is this possible or does it require too many internal ram blocks/multipliers > > > that the Flex simply doesnt have? > > > > > > Thanks!Article: 57480
Hi Yu! > I'm looking for recent analytical papers talking about FPGA vs. DSP > (advantage comparison, etc). This is a comparison like apples and pears. You can compare a DSP-implementation of some problems with the realisation as hardware (FPGA) and so on... A comparison of a RISC / CISC - processor with a DSP would be o.k.. (In this case it would be a comparison of the different architectures.) RalfArticle: 57481
Hi tk, thanks for your reply. I had to get more familiar with the the buff-stuff. An ibufg is just a dedicated input buffer for connecting to the clock buffer BUFG or CLKDLL.The clock problem was solved with the insertion of a BUFG. Actually, my dwarfish design is routed on a Virtex-II device using the Xilinx xapp290 example bus-macro. Maybe the format of that macro (created with a former FPGA-Editor version) differs slightly from the format of the self-made macros? ChristianArticle: 57482
Luiz Carlos wrote: > > > >Again, I don't think you are reading what I am posting. In the XC3S400 > > >there are almost 7200 FFs and LUTs. So there are nearly 3600 LUTs > > >capable of being RAMs and SRs. How many do you really need??? That is > > >56,000 bits of distributed RAM, almost a quarter as much as the block > > >rams! Don't you need some LUTs to use as logic??? > > > > The wider address rams will require external muxing/control to > > implement with only 4 LUTs/CLB usable as ram rather than 8. > > That is my poit of view. I donīt care (not much) of having just half > of the LUTs confurable as memory (Iīve read what you wrote, Rick), but > I didnīt like loosing those dual ported bigger blocks (you didnīt read > carefully what I wrote). To have the same function I'll need a lot of > additional logic and/or a clock two times faster. So, my DSP designs > need a lot of more CLBs in Spartan3 than in Virtex2, and I'm not Ray. > > Luiz Carlos Oenning Martins > KHOMP Solutions You can feel how you wish about your designs, but even the loss of the 64 bit dual ports and the 128 bit single port rams is not signficant. To make a 64 bit dual port RAM requires 8 LUTs for ram (same as in VII) and one LUT for the read mux and possibly two more LUTs for the WEs. But if this is part of a larger ram block you are making half of the WEs would have been required anyway. So it is not a "large" amount of logic, just a bit more. If you are making really large blocks where the longer runs on the address and data can slow it down significantly, then you likely are better off with the block rams. Considering the much lower price of the XC3S parts, all this sounds to me like a benefit, not a liability. Think of it as paying for the LUTs that have RAM and getting the other LUTs for free :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 57483
Hi there I'm not very familar with HDL, but I have to realize a small project with Lattice CPLD. Up to now the most things are working fine, but now I need help: I'm searching for a device to implement (possibly written in ABEL) to decode signals from PC's seriell port, so I finaly get my eight data bits, under consideration of parity bit. I think, the need for this part is very common, but I can't find it. Can somebody help my with the code or can send a source for ABEL-code?? Greetings TimoArticle: 57484
Ralph,
Sorry for the delay in my response. I tried the code below with ISE
5.2i sp3 targeting a 9572:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity inits is
Port ( d : in std_logic;
c : in std_logic;
q : out std_logic);
end inits;
architecture inits_arch of inits is
signal q_temp : std_logic := '1';
begin
process (c) is begin
if c'event and c = '1' then
q_temp <= d;
end if;
end process;
q <= q_temp;
end inits_arch;
The register had the INIT value of '1' attached to it. I then tried the
below code with record types:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity inits is
Port ( d1 : in std_logic_vector (4 downto 0);
d2 : in std_logic_vector (4 downto 0);
c : in std_logic;
q1 : out std_logic_vector (4 downto 0);
q2 : out std_logic_vector (4 downto 0));
end inits;
architecture inits_arch of inits is
type v_reg_type is record
-- registers
IOLatch : std_logic_vector(4 downto 0);
IOLatch2 : std_logic_vector(4 downto 0);
end record;
signal d_temp : v_reg_type;
signal q_temp : v_reg_type := (IOLatch => "11111", IOLatch2 => "11111");
begin
process (c) is begin
if c'event and c = '1' then
q_temp <= d_temp;
end if;
end process;
d_temp.IOLatch <= d1;
d_temp.IOLatch2 <= d2;
q1 <= q_temp.IOLatch;
q2 <= q_temp.IOLatch2;
end inits_arch;
The registers did not get initialized in 5.2i sp3 or in our next version
of the software. I will file a bug report on this.
As for your version of webpack not working please try the latest
version. If the register is still not initializing as suspected (not
using record types that is) please contact the hotline.
thanks
Steve
Ralph Mason wrote:
>"Steven Elzinga" <steven.elzinga@xilinx.com> wrote in message
>news:3EFC59CE.8090103@xilinx.com...
>
>
>>Ralph,
>>
>>Another method (aside from passing an INIT) is to initialize the signal
>>that will be registered:
>>
>>library ieee;
>>ues ieee.std_logic_1164.all;
>>
>>entity ff is
>>port (d, c : in std_logic;
>> q : out std_logic);
>>end entity;
>>
>>architecture ff_arch of ff is
>>signal q_temp : std_logic := '0'; -- XST will pass the proper INIT
>>value based off of the signal initialization
>> -- This INIT value is the state to
>>which the register will power up
>> -- q_temp is the signal that will be
>>registered
>>begin
>>:
>>:
>>
>>
>>Steve
>>
>>
>>
>
>Hi Steve,
>
>With webpack 5.1 this doesn't seem to work at all. Doing this and then
>looking at the report file there is no change in the init states of the
>registers do not change at all.
>
>Taking the inferred net names from the synthesis report and using a
>constraints file worked fine though.
>
>Any ideas why your approach wouldn't work for me? Perhaps I am doing
>something wrong?
>
>Thanks
>Ralph
>
>
>
>
Article: 57485Thomas, Ngdbuild is warning that what it thinks is a clock (but is actually a reset) is not connected to clock pins of various components. When I have seen this warning it was usually as a result of having some non clock nets driven by a clock buffer, i.e. a bufg. Colm. Thomas wrote: > I get the following warning: > > WARNING:NgdBuild:477 - clock net 'resetlogic_local_reset' has non-clock > connections. These problematic connections include: pin clr on block > resetlogic_resettimer_3 with type FDCE, pin pre on block > resetlogic_resettimer_0 with type FDPE, pin pre on block > resetlogic_logicreset with type FDPE, pin pre on block > resetlogic_resettimer_1 with type FDPE, pin pre on block > resetlogic_cpureset > with type FDPE, pin pre on block resetlogic_resettimer0_1 with type > FDPE, pin > pre on block resetlogic_resettimer0_0 with type FDPE, pin pre on block > resetlogic_resettimer_2 with type FDPE, pin pre on block > resetlogic_resettimer_4 with type FDPE > > ... that signal is a reset signal that stays low for a few clocks then goes > high. What does this message mean? > the xilinx doc, is (once again | as usual | as expected ) useless at > describing what it is.Article: 57486
rickman wrote: > > > Except that I often am contacted by Altera directly rather than here in > public. I can understand why they would do that. I cannot understand that at all. If the question is ventilated in public, it should be answered in public. Unless the answer is very embarrassing... Peter Alfke, XilinxArticle: 57487
Does anyone know where I can find the xapp354_verilog or xapp354_VHDL files for NAND flash? I went to the Xilinx ftp site, and they were not listed there. Thanks.--MattArticle: 57488
Hi I am trying to use xilinx PLB TFT LCD core with EDK/XPS but the core is not even listed, it is in the cores directory (marked obsolete) ML300 TFT works well with xilinx demos, but there is no EDK example with TFT support, anybody succeeded to use EDK meaningfully for V2Pro/ML300 ? tnx AnttiArticle: 57489
Willste nen S3-50 haben? Die liegen hier in meiner Schublade... Darmstadt ist ja nicht so sehr "out in the wild" Gruss Peter ====================== Uwe Bonnes wrote: > > DK <dknews@ueidaq.com> wrote: > : Hi, All > > : for the new multichannel filter design I have a choice - > : Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???) > > : Xilinx part has a embedded MAC units. > > : I've used in a past Altera chips and they have a good tech support and free > : tools. > > : Does any one has experience with Xilinx support? And is it possible to > : obtain a free tools from Xilinx or they charge for the software? > > : Any other hidden issues? > > Don't expect the Spartan III out in the wild any soon... > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57490
I'm working on implementing a custom game boy advance cartrige with the following features: - 4-16MByte flash rom (bank switched to a 24 pin buss) - 32kbyte save ram (game state save, can be stored in flash rom if needed) - usb-to-pc link - in system reprogramability via usb - hardware assist for MP3/OGG decoding or similar lossy compression (target compression is 8bit, 2-8Kbit/sec, for 30min of audio in 2mbyte of rom) Space is a huge concern, my target board size is 1x2 inches. Plus my target cost in quantitys of 1,000 or more is $10-$15 total for the board and everything. Im looking at using the intell strata flash roms at ~$8 for a 4MByte chip in quantitys so that only leaves me ~$2-$7 for my remaining logic. To keep costs down as well as size Im looking on implementing the rest of the logic in an FPGA or CPLD. Currently Im looking at the Altera MAX 3000a series of chips. Is there enough power in the max chips to do what I want? What chips would you recomend? Should I just implement the controll logic in an ASIC and pick up an Atmel 8051 for the USB and MP3 decoder? thanks for your time, David TuckerArticle: 57491
Perhaps I did not explain well enough: Use the asynchronous reset the way you want to. Then generate a synchronous signal that lasts a little longer than the asynchronous reset, and use this synchronous reset signal to either drive Clock Enable inactive, or to force D Low. This overrides the trailing end of the asynchronous Resst, and lets the flip-flop "wake up" in a synchronous fashion, which is easy to simulate... Peter Alfke =================== Nial Stewart wrote: > > Peter Alfke <peter@xilinx.com> wrote in message > news:3F00A341.650BCCA4@xilinx.com... > > My approach would be to generate a synchronous CE (clock disable) signal > > and distribute it. Now I have a synchronous signal distribution problem > > that I can analyze the conventional way. If the prop delay is less than > > a clock period, there is no problem. Otherwise I can resort to > pipelining... > > That means, you are in charge and not at the mercy of some loosely > > specified asynchronous delay > > Peter, do you recommend using these synchronised resets with the asynch > reset > input of your flip-flops, or do they then become part of the > synchronous inputs? > > Nial. > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.ukArticle: 57492
Kris, The value E4E4 is the hex value in the LUT that is derived from a truth table: inputs | output 4 3 2 1 | out ------------- 0 0 0 0 | 0 0 0 0 1 | 0 0 0 1 0 | 1 0 0 1 1 | 0 0 1 0 0 | 0 0 1 0 1 | 1 0 1 1 0 | 1 0 1 1 1 | 1 : : The first 8 output bits that are listed -> 1 1 1 0 0 1 0 0 is a hex value of E4. Steve kris wrote: >Hi all, >If you look at the mapped netlist then the lut's are defined as >defparam NameOfLut.INIT=16'hE4E4; >does anybody know how the INIT defines the functionality of the LUT. In >other words >what does E4E4 mean? >Kris > > > >Article: 57493
Sorry, this was meant to be a personal reply, and it says that I have Spartan3-50s here in my drawer. They do exist ! (BTW, don't use your German dictionary, it starts with some colloquialisms...) Peter =============== Peter Alfke wrote: > > Willste nen S3-50 haben? Die liegen hier in meiner Schublade... > Darmstadt ist ja nicht so sehr "out in the wild" > Gruss > Peter > ====================== > Uwe Bonnes wrote: > > > > DK <dknews@ueidaq.com> wrote: > > : Hi, All > > > > : for the new multichannel filter design I have a choice - > > : Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???) > > > > : Xilinx part has a embedded MAC units. > > > > : I've used in a past Altera chips and they have a good tech support and free > > : tools. > > > > : Does any one has experience with Xilinx support? And is it possible to > > : obtain a free tools from Xilinx or they charge for the software? > > > > : Any other hidden issues? > > > > Don't expect the Spartan III out in the wild any soon... > > > > Bye > > -- > > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 57494
"tk" <tokwok@hotmail.com> wrote in message news:<bde307$j68$1@www.csis.hku.hk>... > Hi all, > > I have problem in configuring the xc2vp7 on the ML300 board. The > problem is described in the previous thread "ERROR:iMPACT:583". > > I doubt that I have omitted some settings on the ML300 board during > programming (or have done sth wrong in iMPACT). There is a button > called "FPGA PROG" on the ML300 board. I've searched through the > documentation but I couldn't find out what's it for. > > Does anyone have the experience on using ML300 that can share with me ? > > Thanks very much. > > tk there is not much I can share (yet) but: the impact/xps download to ML300 freezes some times, problem has been fixed by restarting rebooting, sometimes pressing the "fpga prog" button. the fpga prog button I guess simply forces the fpga to not-init state waiting for config, as sysace is not reset, it stays in non-configured state until you configure with impact. there are no settings on ML300 that could prevent the jtag re-config it should always work (but does not) in my case I had started v2pdk shells, debug server debugger, killed them and then tryied impact, and was freeting, not sure why. anttiArticle: 57495
"Peter Alfke" <peter@xilinx.com> wrote in message news:3F01ACDB.D6932AAE@xilinx.com... > Willste nen S3-50 haben? Die liegen hier in meiner Schublade... > Darmstadt ist ja nicht so sehr "out in the wild" > Gruss > Peter > ====================== > Uwe Bonnes wrote: > > > > DK <dknews@ueidaq.com> wrote: > > : Hi, All > > > > : for the new multichannel filter design I have a choice - > > : Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???) > > > > : Xilinx part has a embedded MAC units. > > > > : I've used in a past Altera chips and they have a good tech support and free > > : tools. > > > > : Does any one has experience with Xilinx support? And is it possible to > > : obtain a free tools from Xilinx or they charge for the software? > > > > : Any other hidden issues? > > > > Don't expect the Spartan III out in the wild any soon... > > > > Bye > > -- > > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Hab auch ein paar S3-50 in der Schublade... Weiss aber immer noch nicht ob die Blockrams und DLL's haben oder nicht ? Gruss MIKE for our english readers: I also have some spartan3-50 devices, but don't know if they have blockrams and dll's ? regards MIKEArticle: 57496
"Timo" <tispace@yahoo.de> wrote in message news:ae53bc9e.0307010645.3908cb1c@posting.google.com... > I'm not very familar with HDL, but I have to realize a small project > with Lattice CPLD. > Up to now the most things are working fine, but now I need help: > I'm searching for a device to implement (possibly written in ABEL) to > decode signals from PC's seriell port, so I finaly get my eight data > bits, under consideration of parity bit. I think, the need for this > part is very common, but I can't find it. What you need is a "UART receiver" and yes, they are very common. Typically you need a clock that runs at least 16x faster than the desired Baud rate. You can then detect the start bit and locate the middle of that bit position using a counter; then leave the same counter running, and use its value to determine when to sample the remaining 8 bits + optional parity bit + stop bit. Each data bit then must be shifted into a shift register, and as soon as you see a valid stop bit you must copy that shift register to a holding (buffer) register that the CPU or other "data user" can see. The whole thing uses quite a lot of flip-flops and you may find that it will consume a big part of your CPLD. Expect to use around 30 flip-flops (9-bit shifter, 8-bit buffer, 3 bits of status information, 4-bit shift counter, 4-bit oversampling counter, possibly a few bits of state logic). If you need flexibility (variable Baud rate, configurable parity etc) then the flop count will rise yet further. HTH -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 57497
"Jun" <free_y2003@yahoo.com> ha scritto nel messaggio news:vc32gvkddvihro1o7ukstsqu6ue6l9bhdv@4ax.com... > I am now designing a FPGA based video processing board for my own use. > The board has standard NTSC/PAL, HD and DVI input., a VirtexII FPGA, > 64 bit DDR-SDAM interface, DVI/RGB/YPbPr output, I2C and UART > communication port. Recently, I heard some interests from others I'd purchase one myself, should that contains also: - a strip for piggy back modules, with at least 8 bit + clock + 3 ctrl lines, to test different decoders, or different receivers. - an NTSC/PAL encoder - a Firewire port ? or maybe pushing up a bit the "piggy back" interface... - the HD input can scale down to SDI ? Keep us informed, seems really interesting.Article: 57498
lecroy wrote: >I am reposting after a memo from reader siting problems using the >Xilinx link to post to this group. Sorry about any problems this may >have caused. > >After the release of Alliance 3 support was no longer offered >for the XC3xxx family. Worse, if you did not happen to >have the original software that supported these >devices, Xilinx would not sell you a copy. Even today we >still have product that uses the 3xxx family. > If you're having trouble getting software for 3K devices, let me know. >I am looking at upgrading our group to Allience 5.x >and again see that Xilinx has dropped all support for >Spartan. Other families were dropped as well. We would >now need three copies of software running to >support the Xilinx devices we use. Of course, not all >the Xilinx tools like to be co-installed, so it's multiple >computers or swap installs. > >Xilinx, what is your problem? Altera may drop parts, but >their router continues to support all of their devices. >Is your software so poorly written that it is so difficult >to maintain parts that you need to drop them? > The issue is not the software, it's the testing. With thousands of device/package/speed grade combinations, plus the platforms and OSs, plus all the EDA interfaces we support, there are millions of possibilities that need to be tested. Since the Spartan software was high quality, and we didn't want to destabalize it with enhancements needed for newer architectures, we decided to freeze the Spartan software. This allows us to focus our testing efforts where they are needed most. Spartan software is available for free at: http://www.xilinx.com/ise_classics/index.html By the way, I don't expect us to be dropping any more architectures from our FPGA tools. Steve > I could understand >if the parts were no longer available, or you at least sold >older copies of your software. > >Article: 57499
On Tue, 01 Jul 2003 16:40:05 GMT, "Antonio Pasini" <pasini.a@tin.it> wrote: >"Jun" <free_y2003@yahoo.com> ha scritto nel messaggio >news:vc32gvkddvihro1o7ukstsqu6ue6l9bhdv@4ax.com... >> I am now designing a FPGA based video processing board for my own use. >> The board has standard NTSC/PAL, HD and DVI input., a VirtexII FPGA, >> 64 bit DDR-SDAM interface, DVI/RGB/YPbPr output, I2C and UART >> communication port. Recently, I heard some interests from others > >I'd purchase one myself, should that contains also: > >- a strip for piggy back modules, with at least 8 bit + clock + 3 ctrl >lines, to test different decoders, or different receivers. >- an NTSC/PAL encoder FPGA has a header connector capable of streaming in or out 24 bit video signal. What NTSC/PAL decoder do you like. I intend to use Micronas 323x. It seems slightly better than Philips decoder. Any comments? >- a Firewire port ? or maybe pushing up a bit the "piggy back" interface... No, it won't have a fieewire port. I don't want to make this board too too complicated and not many people are using it. >- the HD input can scale down to SDI ? > HD input is YPbPr with an 8-bit ADC. The board has a Faroudja FLI2300 on it. So you can implement your own scaling algorithm inside FPGA or use the Faroudja chip to do the scaling job. For the time being, I don't have SDI receiver and transmitter in my design. Maybe it is good idea too. Though they are excellent for broadcasting, probably will never enter consumer market. >Keep us informed, seems really interesting. > > Thank you for the feedback, Antonio. I will keep you posted.
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