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hai, I am new to the CPLD programming. I have to upgrade the CPLD(XCR3256XL) program using embedded controller. How commands like ISPEN, FERASE etc., will be called? Can anyone explain? Thanks in advance, ChiArticle: 63926
Looking at the mode selection M2 on the SII devices in Xilinx document DS-001_2, table 8, I wonder if the M2 for master mode is correct? It seems to match the rest of the data sheet, but I would have thought the the pullups would always follow the M2 pin and this is the only mode where it does not. On the SII, there is no mention of allowing for a weak pullup on the global clock lines. Interesting enough that using the 6.x tools and placing the following in the constraints: NET "p_pclock" LOC = "P88" | IOSTANDARD = LVTTL | PULLUP ; I get the following message from project manager during place and route: Annotating constraints to design from file "main.ucf" ... Attached a PULLUP primitive to pad net p_pclock If I look at the FPGA editor at pin 88 after place and route, there is no dialog box to allow for pullups, etc, like there are with a standard I/O. So, I would have to guess that in the actual device there was no pullup added. Can someone at Xilinx confirm this? ThanksArticle: 63927
If you are considering floorplanning- consider a physical synthesis tool such as Amplify or Precision Physical Synthesis. It lets you floorplan closer to the RTL- so it is easier to understand. Search the board for more info. Also- you should consider the backend tool that you are using. These backend tools are getting better all the time. For example, the latest version of Foundation (6.1 I believe) will do a far better job that the version 4 I used to use. So when looking back at posts- keep that in mind.Article: 63928
Has anyone used this embedded PowerPC in the Virtex2 Pros? We are working on a project where we will be pushing some functions into the processor on the FPGA. Basically- it will handle all the data path exceptions. I am interested to hear how people interfaced the data to the processor (DPRAM, DMA, registers, etc) and especially interested to hear how they (or whether they) tested everything. What sort of OS did you run? How hard was it to get everything to work together- to debug? How is the EDK toolset? Did you take formal training? We order a development board and will be banging on that soon. Thanks, WPArticle: 63929
hi, that sounds interesting since I've not seen such error before. Loadless is okay but sourceless and multiple drive will cause unexpected error, sometimes the software will gives up and post some silly message. Check your circuit and possibly break it into smaller macros blocks thst may help. good luck,Article: 63932
The BUSY signal has no programmable options. It is used during Slave Parallel configuration mode only. If the CCLK rate is under 50 MHz, it will stay Low during configuration and can be ignored. See the Spartan-II data sheet at http://www.xilinx.com/bvdocs/publications/ds001_2.pdf for details. "Amontec Team, Laurent Gauch" wrote: > Hi all, > > Is that possible to put the busy signal (when the FPGA is configuring) > in a float state. > > I coupled an ARM7 and a SPARTAN-II, and busy signal of the FPGA is > directly connected to a data_line of the ARM. > As we are doing FPGA configuration over ethernet, busy line corrupt the > ARM when it try to configure the FPGA. > > There are two solutions: > -- change the schemetic > -- to be able to put busy line in a float state as an other IO line when > FPGA is programming : > > Are there any option in ISE to do that? > > Laurent > www.amontec.com -- Marc Baker Xilinx Applications (408) 879-5375Article: 63933
I notice you're using Modelsim. One of my leading gripes with this program, the one that must have cost me the most time overall, is that it doesn't alert you (or maybe I just have the preferences set wrong somewhere) at compile time if it can't find an ENTITY, it just continues with a "compilation successful", and you have to double click on the this success message to learn that it actually failedto find any of the files it needs to actually do anything, and then your simulation gives X's all over the place. Of course, you're geting Z's, which is weird, but I figure it might be a similar problem. That, and I wanted to gripe ;). Sorry for hijacking your thread if this is an unrelated issue... Matt wrote: > Ryan, > I ran the vmap batch file and compxlib per the instructions on > page 5 of the getting started guide. The problem is still there. I > went through the tutorial design (except for the programming into > hardware) and the tutorial design gives me 'Z' output. Any idea why? > Thanks again. > > Matt > -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 63934
If I remember right this was a known issue way back where the number of signals on a sheet could not exceed 1024. The workaround was (as lnguyen) said to split the design over multiple sheets Basuki Endah Priyanto wrote: > Hi all, > I'd like to highlight a problem encountered while using the Xilinx foundation series 4.1i. I am unable to connect all the input ports to the respective output ports due the following comments shown: > Too many signals: Checking for sourceless, loadless nets and multiple drivers aborted. > I suspect that there is a limit to the number of bus terminal labels that we can give on a schematic. > The bus terminal labels are given to the inputs and outputs ports so that they need not to be physically connected with wires. These termianl labels are essential as it is impossible to physically connect the ports together with wires under the constraint of the space given in the schematic. > > Any idea how to solve the problem ??? > > Thanks. > > BuzzArticle: 63935
Hello! I want to build a FIFO for a special purpose: I've got a microcontroller that interfaces to a SDRAM via an SDRAM-interface. The microcontrollers data width is 16 bit while the SDRAM-interface needs 32 bit (if i write something to the sdram, in the first clock cycle, the interface needs the bank, row and column address (32 bit) and in the second clock cycle the data (only 16 bit, the upper 16bit are just don't care)). Now I need a FIFO that converts the 2x16 bit to one 32-bit word. Timing is not important, only the 2 words of 32 bit have to be sent one clock cycle after the other. (so i don't need a "doubling" of the clock rate, just a method to combine the two incoming words) could it work with a kind of shift register? Thank you for your help! SimoneArticle: 63936
> Well, that's totally different from what I thought it's working. Okay, I saw > that the xilkernel executable is created and also an bootloader executable. > Besides I have an application executable. If I understand everything, I have > to run the bootloader (which is done automatically, because it's beginning > at address 0) located in BRAM. With this bootloader I should download the > xilkernel executable and put it in memory. Because the process_table > parameter in the MSS file is specified, the kernel wants to start a process > (which is my application), so I have to download first the application to > 0xA0000000 and then the xilkernel to 0x400. Is that correct?! That is correct. > How to start the application if the process_table parameter is not > specified? Jump to application and do a process create here?! There are three ways to start an application that works with xilkernel 1) Put the start address of the app in the process_table in the MSS 2) Use process_create() from some application whose start address was in the process_table in the MSS 3) Use process_create() from some application started in one of the above two ways. > By the way, my bootloader exceeds the 0x400 bytes, thus I have to put the > xilkernel at a higher address by using a linkerscript. Can I put it also in > external memory? Yes. > And how to start up the xilkernel when downloaded into > external memory, just jump to the start address of it? Exactly. > Does the xilkernel > contain startup code for initializing data, stack etc.? (I guess the answer > is yes, because a disassembly of the .elf file shows me there is a > _crtinit). My application does also contain startup code for initializing > data, stack etc, doesn't it? How is this working? Are there different stacks > (one for xilkernel and one for application)? That is correct. The application and xilkernel have their own separate stacks and heaps. > My last question is about getting the xilkernel starting at external memory > (if possible): how to easilly change the common makefile (common for > bootloader and xilkernel) or linkerscript to let the bootloader start in > BRAM and the kernel start at external SDRAM?! Do you have any examples?! The bootloader and xilkernel use separate make files and linker scripts. For the bootloader, the makefile is in your top level project directory. For xilkernel the makefile is in <project-dir>/<mblaze>/libsrc/xilkernel_v1_00a/ So you can modify them independently. We do have some examples of xilkernel usage in the xilkernel_*/src/test/arch/* directories. However, none of these examples shows how to use a bootloader. The PowerPC examples have xilkernel and applications running out of different memories (BRAM + SRAM or BRAM + SDRAM or SDRAM alone) but linker scripts for PowerPC are different from MicroBlaze linker scripts and you would have to read the PowerPC+EDK documentation as well. We are working on more examples and documentation for xilkernel itself and you can expect to see them soon. Meanwhile, if you have more questions please feel free to ask. Best wishes, MohanArticle: 63937
> Indeed - and no different to a lot of embedded software. Some will be I aggree Martin. Embedded folks have to milk their processors for all they're worth also. I suppose there's so much similarity between hardware and embedded software, because they're just different ways of tackling the same problems. > in "vendor-specific" assembly, or even if in C, the low level stuff is > not trivially portable! Heh I bet. Each vendor has their own unique architecture and instruction set. Heck, there's a lot of differences between processor families from the same vendor. > I wonder if the difference is that in FPGA space there is a very > limited choice of vendors, so some people may think that it is > reasonableo t aim for vendor independance, whereas in the embedded That makes sense. The non-embedded world has two large players, the x86 and PowerPC. The FPGA world has two big players also. > processor space there are many more choices, so its clear you'll never > cover them all! Heh yeah, it's better to know that something is futile, so you don't waste your time. Regards, VinhArticle: 63938
> My explanation was probably a little unclear: I would like to set the > reset vector to point to a flash location and run the code directly > from the flash. In order to save some money and board space I wanted > to run a flash in 16-bit mode and use a 16-bit NIOS CPU and feed the > instruction stream directly from the flash. In other words I don't > want to boot out of the flash, I want to execute code from it > directly. > > I just can't see how you can do this on the NIOS Development Kit > Stratix Edition since it only has an eight bit datapath to the flash > (if we're talking about the same board). Take a look at page 6 of: > Hi Petter, Send me an email and I'll send you my design -- it is just that, the reset vector points to flash (8-bit flash at that). Once the FPGA is configured (.sof file download or configuration controller loads the bit stream), Nios boots with the reset vector pointing to flash (containing program memory). This memory is read and my program executes, entirely out of flash. The business of the flash being 8 bits wide and Nios (instruction master) being 16-bits wide is solved by something called "dynamic bus sizing". This is a feature of the Avalon bus which has been present in Nios since it was introduced a few years ago. The idea is that a bus master may request access to a 'narrow' slave -- the bus logic converts the single request for a 16-bit instruction fetch from Nios into two back-to-back 8-bit reads from the 8-bit bus to flash. The two reads are then concatenated into the 16-bit Nios instruction bus, and the read is declared valid (wait signal drops), allowing Nios to read 16 bits. This operation is transparent to the bus master, so a 32-bit Nios (or any other master) may do the same operation. There is even "reverse" dynamic bus sizing implemented for narrow masters accessing wide slaves, allowing (for example), a 16-bit master to use a 32-bit memory without throwing half of it away. This feature was originally implemented to allow users to save IO (or cost) in their external memory choice. > I do. I downloaded a flash model from AMD. I've also written my own > testbench which instantiate the design and the flash (so there's room > for errors here). The thing is since the *only* inputs to the design > are clk and reset I expected to see that it would at least output the > flash address on the bus shortly after reset. The next step would have > been to convert the srec file for the flash to commands to write the > flash before I release reset to the nios cpu (the flash model does not > have readmem to init the flash for simulation). > One suggestion here for debugging where the simulation problem is: Take a look at the Nios instruction master address, coming out of the CPU (before any of the bus logic) -- this should show you what Nios is asking for to get data into the program counter, and it should match your flash address. Also, one other suggestion I can give you would be to use the standard_32 design (with our 8-bit flash), and create the memory model for it in SOPC Builder, and then try the simulation booting from flash. Then, look at the top-level HDL file generated by SOPC Builder. Near the very end of the file is non-synthesizable HDL code that acts as a simulation test bench. Here you will see wiring from the top-level to the simple memory model that we create... I suggest this because it might assist in troubleshooting your test bench & flash memory model instantiation. > > BTW: > > 1) Is it possible to run the plugs library on a 16-bit nios cpu? > 2) Is it possible to use the plugs library without an uart? > see news:<m3brtht54l.fsf@scimul.dolphinics.no> > > Petter (1) I have not tried plugs in 16-bit mode but I am told it will work; there is a 16-bit Nios with Plugs example design included in the suite of examples for the older Nios Apex board. (2) Yes, but Plugs does use stdout via printf.. so some modifications to your software will be necessary unless you wish to modify the plugs source code. I presume that your system without a UART also lacks an OCI debug core (for printf communication), and therefore has no stdout. You could (as one way of doing this), #define printf to go to some subroutine which does nothing in excalibur.h Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 63939
Simone, when you call this a FIFO, it makes it sound complicated and creates fear of non-synchronous problems. But this does not seem to be the case here. I would just use the appropriate number of registers with the right input muzes and a tiny state machine that makes them do the right thing at the right time. You need to consider the required frequency or time response. Should be quite simple. Peter Alfke ================= Simone Winkler wrote: > > Hello! > > I want to build a FIFO for a special purpose: > I've got a microcontroller that interfaces to a SDRAM via an > SDRAM-interface. The microcontrollers data width is 16 bit while the > SDRAM-interface needs 32 bit (if i write something to the sdram, in the > first clock cycle, the interface needs the bank, row and column address (32 > bit) and in the second clock cycle the data (only 16 bit, the upper 16bit > are just don't care)). > Now I need a FIFO that converts the 2x16 bit to one 32-bit word. Timing is > not important, only the 2 words of 32 bit have to be sent one clock cycle > after the other. (so i don't need a "doubling" of the clock rate, just a > method to combine the two incoming words) could it work with a kind of shift > register? > > Thank you for your help! > > SimoneArticle: 63940
Hello! I meant that I need a FIFO + this special "feature" to convert the data to the right length. I thought that i could solve this problem by building a special FIFO. How could I solve this problem? Thanks, Simone "Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:3FD61B4E.B817D5BA@xilinx.com... : Simone, when you call this a FIFO, it makes it sound complicated and : creates fear of non-synchronous problems. But this does not seem to be : the case here. : I would just use the appropriate number of registers with the right : input muzes and a tiny state machine that makes them do the right thing : at the right time. You need to consider the required frequency or time response. : Should be quite simple. : : Peter Alfke : ================= : Simone Winkler wrote: : > : > Hello! : > : > I want to build a FIFO for a special purpose: : > I've got a microcontroller that interfaces to a SDRAM via an : > SDRAM-interface. The microcontrollers data width is 16 bit while the : > SDRAM-interface needs 32 bit (if i write something to the sdram, in the : > first clock cycle, the interface needs the bank, row and column address (32 : > bit) and in the second clock cycle the data (only 16 bit, the upper 16bit : > are just don't care)). : > Now I need a FIFO that converts the 2x16 bit to one 32-bit word. Timing is : > not important, only the 2 words of 32 bit have to be sent one clock cycle : > after the other. (so i don't need a "doubling" of the clock rate, just a : > method to combine the two incoming words) could it work with a kind of shift : > register? : > : > Thank you for your help! : > : > SimoneArticle: 63941
Simone, I was just commenting on the name FIFO, whichin some minds (including mine) paints a picture of significant depth and complexity. In your case, I assume you just need one or two or four 16-bit wide registers with the appropriate multiplexers. At slow speed, this is trivial. At 200 MHz, you have to be a little careful. If you want to discuss details, contact me per e-mail (even in German). Peter Alfke ========================= Simone Winkler wrote: > > Hello! > > I meant that I need a FIFO + this special "feature" to convert the data to > the right length. I thought that i could solve this problem by building a > special FIFO. > > How could I solve this problem? > > Thanks, Simone > > "Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag > news:3FD61B4E.B817D5BA@xilinx.com... > : Simone, when you call this a FIFO, it makes it sound complicated and > : creates fear of non-synchronous problems. But this does not seem to be > : the case here. > : I would just use the appropriate number of registers with the right > : input muzes and a tiny state machine that makes them do the right thing > : at the right time. You need to consider the required frequency or time > response. > : Should be quite simple. > : > : Peter Alfke > : ================= > : Simone Winkler wrote: > : > > : > Hello! > : > > : > I want to build a FIFO for a special purpose: > : > I've got a microcontroller that interfaces to a SDRAM via an > : > SDRAM-interface. The microcontrollers data width is 16 bit while the > : > SDRAM-interface needs 32 bit (if i write something to the sdram, in the > : > first clock cycle, the interface needs the bank, row and column address > (32 > : > bit) and in the second clock cycle the data (only 16 bit, the upper > 16bit > : > are just don't care)). > : > Now I need a FIFO that converts the 2x16 bit to one 32-bit word. Timing > is > : > not important, only the 2 words of 32 bit have to be sent one clock > cycle > : > after the other. (so i don't need a "doubling" of the clock rate, just a > : > method to combine the two incoming words) could it work with a kind of > shift > : > register? > : > > : > Thank you for your help! > : > > : > SimoneArticle: 63942
Been following the rollout of Application Specific Modular BLock (ASMBL) at Xilinx. Lots of gushing words, but what is it REALLY ? Thus far we can glean : Stripe layout, and areal bondpads Not quite 'Revolutionary': Areal bondpads are nice to have, and the Stripe layout has plus and minus columns : Plus: Faster local speeds Minus: Only to a certain ceiling Plus: Faster Place/Route Plus: Reduced routing cross points Plus: Faster device Testing, & possible redundancy mapping Plus: More consistant Place/Route migration Minus: Tendancy to wastage : New IP -> New Column CPLDs have been multiple-larger-block structured for years, and Clock drivers on FPGAs are already have larger fabric elements. But more fun comes from what the analysts think all this means : >"I believe we'll eventually see FPGAs that are fully application-specific," said Bryan Lewis, an analyst with Gartner Dataquest, San Jose. "But this is a nice compromise without losing the economics of having an architecture that can be used by multiple customers." Er, isn't a 'fully application-specific FPGA' actually an ASIC ? :) >"If Xilinx is doing a chip that is 90% perfect for the app, the price difference would have to be strong justification to make the leap into an ASIC," Snyder said. Might be that the more defined stripes make the move to Structured ASICs easier, and this 'MASK FPGA' segment would grow ? Perhaps ASMBL means 'A Surfeit of Marketing BaLoney' ? -jgArticle: 63943
They make it sound like it is a response to structured ASICs but it sounds a little like the QuickSliver stuff to me. QS is embedding custom blocks along with FPGA like blocks. Also the Structured ASICs are biting the dust but QS has hired 50% of all the top reconfigurable computing people I have a lot of faith in their abilities. Steve "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:EbrBb.12264$ws.1161156@news02.tsnz.net... > Been following the rollout of > Application Specific Modular BLock (ASMBL) at Xilinx. > Lots of gushing words, but what is it REALLY ? > > Thus far we can glean : Stripe layout, and areal bondpads > Not quite 'Revolutionary': Areal bondpads are nice to have, > and the Stripe layout has plus and minus columns : > > Plus: Faster local speeds > Minus: Only to a certain ceiling > Plus: Faster Place/Route > Plus: Reduced routing cross points > Plus: Faster device Testing, & possible redundancy mapping > Plus: More consistant Place/Route migration > Minus: Tendancy to wastage : New IP -> New Column > > CPLDs have been multiple-larger-block structured for years, > and Clock drivers on FPGAs are already have larger fabric > elements. > > But more fun comes from what the analysts think all this means : > > >"I believe we'll eventually see FPGAs that are fully application-specific," > said Bryan Lewis, an analyst with Gartner Dataquest, San Jose. "But this is > a nice compromise without losing the economics of having an architecture > that can be used by multiple customers." > > Er, isn't a 'fully application-specific FPGA' actually an ASIC ? :) > > >"If Xilinx is doing a chip that is 90% perfect for the app, the price > difference would have to be strong justification to make the leap into an > ASIC," Snyder said. > > Might be that the more defined stripes make the move to Structured ASICs > easier, and > this 'MASK FPGA' segment would grow ? > > Perhaps ASMBL means 'A Surfeit of Marketing BaLoney' ? > > -jg > > >Article: 63944
Jim, Now really, Jim, why so negative? Isn't Xilinx justified in rolling out a new architecture with some fanfare? Why is it that others are allowed to make outrageous and sometimes even false claims, and no one cares? Yet when we announce a truely revolutionary FPGA architecture, we get complaints? If we can architect a device to allow for any collection of "stripes" and have the mask, and the software ready immediately, isn't that worth shouting about? More and more we see market specific applications that require a more cost effective FPGA (eg software defined radio is a totally different mix of features than automotive entertainment center). Why not be able to target a general purpose device to a specific market segment at reduced cost and better margins? Might get more business that way, right? If Spartan 3 is already cost effective against many ASICs, might this not make us even a better cost/benefit solution? I do agree that the analysts do not have a clue, however. For example, we are being compared to structured ASICs and other "hard" solutions. Those are misleading and false. They are all dead-ends (just a re-spin of gate arrays with new clothing, or some other ASIC flow with window dressing liberally applied). As for the details that I am sure you want to hear, you have to wait until the next press release. Schedule: architectual release, then specific family details, then product announcement. Nothing new here. Been following the same formula for many years. Happy New Year! Austin Jim Granville wrote: > Been following the rollout of > Application Specific Modular BLock (ASMBL) at Xilinx. > Lots of gushing words, but what is it REALLY ? > > Thus far we can glean : Stripe layout, and areal bondpads > Not quite 'Revolutionary': Areal bondpads are nice to have, > and the Stripe layout has plus and minus columns : > > Plus: Faster local speeds > Minus: Only to a certain ceiling > Plus: Faster Place/Route > Plus: Reduced routing cross points > Plus: Faster device Testing, & possible redundancy mapping > Plus: More consistant Place/Route migration > Minus: Tendancy to wastage : New IP -> New Column > > CPLDs have been multiple-larger-block structured for years, > and Clock drivers on FPGAs are already have larger fabric > elements. > > But more fun comes from what the analysts think all this means : > > >>"I believe we'll eventually see FPGAs that are fully application-specific," > > said Bryan Lewis, an analyst with Gartner Dataquest, San Jose. "But this is > a nice compromise without losing the economics of having an architecture > that can be used by multiple customers." > > Er, isn't a 'fully application-specific FPGA' actually an ASIC ? :) > > >>"If Xilinx is doing a chip that is 90% perfect for the app, the price > > difference would have to be strong justification to make the leap into an > ASIC," Snyder said. > > Might be that the more defined stripes make the move to Structured ASICs > easier, and > this 'MASK FPGA' segment would grow ? > > Perhaps ASMBL means 'A Surfeit of Marketing BaLoney' ? > > -jg > > >Article: 63945
Every 4 CLBs, the horizontal tristate line has a pip, delivering the partitioning you read about. Only one of the four horizontal lines has a pip at each CLB column giving a staggered partitioning. Those lines can also interface with the IOBs on the left and right side of the device. They aren't "real" tristates in that if you drive a 1 and a 0 into the same line, the chip doesn't complain with smoke and heat - it gives you the low logic level. FPGA Editor is in the 6.1 tools, but I understand it's not a WebPack item. (I could be mistaken on this) "Przemyslaw Wegrzyn" <czajnik@czajsoft.pl> wrote in message news:c1de0250.0312090321.6701edf8@posting.google.com... > Hi ! > > In the spartan datasheet I can read that: > > "Horizontal routing resources are provided for on-chip > 3-state busses. Four partitionable bus lines are > provided per CLB row" > > What does partitionable mean in this case ? Does this mean the > horizontal lines can be divided ? If so, where (how many) the division > points are there ? > > > Is FPGA Editor removed from ISE6.1i ? I've recently used 6.1i at my > university, and couldn't find it :(Article: 63946
Hi Manfred, > I would like to renew my question: Why do you restrict FIFO depths to > powers of two? I can't see the need for that. The dual-clock FIFO internally uses a Gray counter, which is fairly trivial to write for a power of two, plus the fact that counter rollover happens with a single-bit transition as well. The Gray counter greatly reduces the risk of the Other Side (the one in in the different clock domain) seeing inaccurate counter values: the count is either the same, or only one bit has changed. For a normal counter, due to variations in the delay path between the various counter bits, part of the logic in the other clock domain might see a number of counter bits still having the old value, and a number that has the new value, resulting in a nonsense value. When there's a large difference between reader and writer clock frequencies, there may be not a single bit transition, but at least the number of transitions is minimized over time. I haven't studied Gray counters deeply enough to see whether it's feasible, or even possible to write a Gray counter generator algorithm that can _efficiently_ do single-bit-transition counter rollover on an arbitrary (though pre-computed) value. If this is possible without going into long combinatorial chains (which would reduce operating frequency) it should definitely be feasible to remove this power-of-two restriction. For the single-clock version - hey, why not? Just my $.02 Ben TwijnstraArticle: 63947
Hi, there: I am reading AMBA specification. Does the Read/Write waveform for the APB indicate the bus speed is 1/3 of the pclk frequency? Now if I need to write a continuously in every clock cycle, may I keep the PWRITE, PSELx and PENABLE high for many cycles while keep changing address and data every clock cycle? OR, am I obliged to use AHB's burst moode? Thanks.Article: 63948
"Austin Lesea" wrote > Jim, > > Now really, Jim, why so negative? I did not think I was negative on the engineering aspects ? - I listed more pluses than minuses :) ? > Isn't Xilinx justified in rolling out a new architecture with some fanfare? Of course, but when the gush exceeds the hard data, expect some analysts to get it wrong.... > Why is it that others are allowed > to make outrageous and sometimes even false claims, and no one cares? > Yet when we announce a truely revolutionary FPGA architecture, we get > complaints? "truely revolutionary" is a bold claim. I can see good Engineering & Yield trade-offs in what's released so far, but that's some way short of "truely revolutionary". > > If we can architect a device to allow for any collection of "stripes" > and have the mask, and the software ready immediately, isn't that worth > shouting about? Can you clarify 'the mask' ? Does this mean this will become like a block-hard-copy (but still FPGA), where a large enough customer (/market?) can 'select the mix of stripes' and a new die results ? With real care, 'the mask' could even be effectively virtual by using stripe based exposures at the wafer level. Challenge there will be in the definition, to get devices to reach critical mass, and not go EOL as uptakes do not quite meet forecasts. > More and more we see market specific applications that require a more > cost effective FPGA (eg software defined radio is a totally different > mix of features than automotive entertainment center). Why not be able > to target a general purpose device to a specific market segment at > reduced cost and better margins? Might get more business that way, > right? If Spartan 3 is already cost effective against many ASICs, might > this not make us even a better cost/benefit solution? So is this not a merchant market device, but an 'ASIC cherry pick' vehicle ? -jgArticle: 63949
Peter Alfke wrote:
> I would just use the appropriate number of registers with the right
> input muxes and a tiny state machine that makes them do the right thing
> at the right time.
Well said.
Thinking only in terms "well know" logic blocks
can obscure the real requirements,
and the real fpga resources.
-- Mike Treseler
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