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Hi, I think it does. If in ISE Project Navigator you go to Edit -> Language Templates -> Verilog -> Component Instantiation, then you can see the way it is done (in any of the RAM instantiation samples). Please do correct me if I am making some mistake. Adarsh "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:2u8Ab.66158$PY.31048@newssvr25.news.prodigy.com... > Page 155, XST User guide: > > "XST does not support block RAM initialization in Verilog." > > Why not? > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > >Article: 63876
"Adarsh Kumar Jain" wrote: > Verilog -> Component Instantiation, then you can see the way it is done (in > any of the RAM instantiation samples). No, not instantiation for synthesis. Simulation. That's why the subject is "Block RAM simulation VII". Initializing for synthesis works very well. If you don't see what I quoted on page 155 of your XST User Guide check the document version. I have 4.0, issued on 06/06/03. It's what came with the latest ISE update. Also, don't use the message subject line as part of a reply, it destroys a thread. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 63877
> learned about this in the Verilog NG ... it was like talking to someone from > another planet. Heh heh :_D > I don't really use inference for these constructs, I instantiate explicitly. > Why would you speak Greek when you know you need to say something in French > and you can speak French? Maybe 'cause I'm old school ... You definately don't have to worry about the synthesis tools getting too creative. Inference can save you some typing, but spend some time with "generics" and "generate" and you can craft a piece of reusable code that can handle varying widths and depths. And though I've never tried it, doing RPMs might be easier with instantiation, since you have more control over the structure/naming of the components. I just use inference because of the "neato" factor when I was first learning VHDL. > I still have my auto-stripping electric wire-wrap gun. Heh I think I've only used it once, during an internship. Iy does a very nice and neat job though. I remember the experienced guys telling me war stories of having to wire up an entire board, only to find out they did something wrong under serval layers of other wiring.Article: 63878
> No, not instantiation for synthesis. Simulation. That's why the subject is > "Block RAM simulation VII". Initializing for synthesis works very well. Heh looks like I might have led Adarsh astray with my synthesis/simulation mix up. Oh how history repeats itself.Article: 63879
Hi, I have a chain of registers to delay a certain wide signal 5 clocks. Quartus infers altshifttaps from this, which is fine because it saves me LEs. Unfortunately the M512 where it places the inferred shift register causes a long delay to and from the rest of logic. I want to manually assign this inferred shift register to a specific M512 for timing purposes. My question is two-fold: 1/ I tried assigned the affected registers to an M512 using Assignment Editor. Quartus ends up telling me this is an invalid location. This leads me to my next question: 2/ Does quartus look at location assignments before inferring shift regs, DSP blocks, etc? If not, this would explain #1 because LEs can obviously not be assigned to TriMatrix memory. So is it possible to assign a location to something that I know will be inferred by Quartus to use a specialized resource? Or do I have to write my code to explicitely use the altshifttaps megafunction?Article: 63880
Is it possible to run nios code from flash memory directly (assuming I'm running at only 10MHz)? Or do I need a small bootstrap in local rom to jump to the flash address? Most existing designs I've seen have use an external ram and bootstrap by copying code from the flash to the ram prior to branching to the start address. I tried a quick simulation. The only inputs I have to the nios cpu is clock and reset. I don't see that it's trying to put the flash address out on the bus. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 63881
Hey Martin, sorry about the subject line. I am new to this newsgroup thing... i had an earlier version of XST. anyways, i see your point. if it is simulation you are talking about, do you mean functional simulation ? in that case how is XST connected to it ? and then is it really a verilog issue ? for simulation can't you just use the "initial" statement ? and for any post synthesis simulation, I think the example in language templates works. adarsh "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:tlBAb.66747$aJ6.11966@newssvr25.news.prodigy.com... > "Adarsh Kumar Jain" wrote: > > > Verilog -> Component Instantiation, then you can see the way it is done > (in > > any of the RAM instantiation samples). > > No, not instantiation for synthesis. Simulation. That's why the subject is > "Block RAM simulation VII". Initializing for synthesis works very well. > > If you don't see what I quoted on page 155 of your XST User Guide check the > document version. I have 4.0, issued on 06/06/03. It's what came with the > latest ISE update. > > > Also, don't use the message subject line as part of a reply, it destroys a > thread. > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > >Article: 63882
Hi cruzin,
At present it is not possible to assign a location to something that
will be inferred by Quartus to use a specialized resource. In this case the
code should be written to explicitly use the altshifttaps function, so that
you can assign a location assignment.
- Subroto Datta
Altera Corp.
"cruzin" <cruiser144@hotmail.com> wrote in message
news:775730eb.0312070911.715c659e@posting.google.com...
> Hi,
>
> I have a chain of registers to delay a certain wide signal 5 clocks.
> Quartus infers altshifttaps from this, which is fine because it saves
> me LEs.
>
> Unfortunately the M512 where it places the inferred shift register
> causes a long delay to and from the rest of logic. I want to manually
> assign this inferred shift register to a specific M512 for timing
> purposes.
>
> My question is two-fold:
>
> 1/ I tried assigned the affected registers to an M512 using Assignment
> Editor. Quartus ends up telling me this is an invalid location. This
> leads me to my next question:
>
> 2/ Does quartus look at location assignments before inferring shift
> regs, DSP blocks, etc? If not, this would explain #1 because LEs can
> obviously not be assigned to TriMatrix memory.
>
> So is it possible to assign a location to something that I know will
> be inferred by Quartus to use a specialized resource? Or do I have to
> write my code to explicitely use the altshifttaps megafunction?
Article: 63883Hi, I remember reading a few lines on this newsgroup about the fact that a DLL in a Virtex might not be able to handle a negligible skew between two outputs (clk0 and clk2X for instance) in some situations like a heavy loading difference between the two clock trees with maybe an important (but in the datasheet spec ?) jitter on the input clock. Ever since I read this I did not consider I could change from one clock domain to the other without special care. Has anyone something new concerning these potential cases ? If there is still a possibility does it apply only to Virtex or also to Virtex II ? The reason I ask is that the designs coming up are running faster and faster making it more difficult to consider changing clock domains with some extra precaution. Thanks, JFArticle: 63884
Silvano Bettinzana wrote:
> Dear friends,
>
> I'm a novice and playing with Xilinx ISE Webpack and ModelsimXE.
> I have a 'TOP' Verilog module in which I have instanced 2 module: 'A' and
> 'B';
> I have a testbench for 'TOP' and want to simulate with 'A' sinthesized and
> 'B' not synthesized ('B' is not synthesizable; it has for example '#...'
> statement).
> Is this possible ?
I believe so, unless this isn't implemented in WebPack...
> How ?
You can ask ISE to generate a VHDL/Verilog simulation model at most
stages of implementation, i.e. post-translate, post-map, post-p&r. All
you need to do is take the generated file and use it instead of your
original source code. I don't know for Verilog, but the VHDL model has
exactly the same entity declaration, except the GENERICs have been
hard-coded, so the same testbenches can be used in each sim with only
very minor modifications... The only annoyance I've had is that your
signal names tend to be flattened out, and I'm not aware of any signal
name equivalence file. Hope this helps,
--
Pierre-Olivier
-- to email me directly, remove all [N0SP4M] from my address --
Article: 63885The new version of Xilinx tools (6.1i and on) appear to be doing a more complete job on this analysis. The biggest problem earlier was the effect of input jitter on the DCM that couldn't be accounted for. Uneven loading on the clock nets was also an issue. Now the tools allow an INPUT_JITTER constraint to go along with your specified period and duty cycle. Also with the automated elimination of hold-time violations, it looks like the tools are filling in for the corner cases of design as long as we, the designers, give the tool the right info. I'm now happier making the transition between same-edge clock domains without special treatment though I know where to look first if my design starts to misbehave. "jean-francois hasson" <jfhasson@club-internet.fr> wrote in message news:3fd377da$0$6982$7a628cd7@news.club-internet.fr... > Hi, > > I remember reading a few lines on this newsgroup about the fact that a DLL > in a Virtex might not be able to handle a negligible skew between two > outputs (clk0 and clk2X for instance) in some situations like a heavy > loading difference between the two clock trees with maybe an important (but > in the datasheet spec ?) jitter on the input clock. Ever since I read this I > did not consider I could change from one clock domain to the other without > special care. Has anyone something new concerning these potential cases ? If > there is still a possibility does it apply only to Virtex or also to Virtex > II ? The reason I ask is that the designs coming up are running faster and > faster making it more difficult to consider changing clock domains with some > extra precaution. > Thanks, > > JF > >Article: 63886
Hi Manfred,
There is no real need to restrict it. There have been several requests
to relax this condition and we will get to it in a future release.
- Subroto Datta
Altera Corp.
"Manfred Mücke" <manfred.getmuecke@ridgmxof.thisat> wrote in message
news:oprzq27uthgdoir8@news.inode.at...
> Hi Subroto,
>
> I would like to renew my question: Why do you restrict FIFO depths to
> powers of two? I can't see the need for that.
>
> Regards, Manfred
>
Article: 63887"Adarsh Kumar Jain" wrote: > sorry about the subject line. I am new to this newsgroup thing... No problem. That's why I pointed it out. > do you mean functional simulation It's about simulating a Block RAM with data in it. Say you are using one as a lookup table. You want to run a simulation with the lookup table actually working, otherwise the results might be of little use. I'll look into some of the other options. I sort of let this one go as verification was done in actual hardware. Can't stop to do it right, gotta keep that productivity up! :-) -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 63888
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote: :I don't really use inference for these constructs, I instantiate explicitly. :Why would you speak Greek when you know you need to say something in French :and you can speak French? Maybe 'cause I'm old school ... I still have my :auto-stripping electric wire-wrap gun. Portability. An instantiated primitive locks you into that vendor's technology.Article: 63889
Hi, I am trying to use AVRCore project from opencores.com on ACEX1K100-3 FPGA. Timing summary tells me that maximum clock is 11.xxx MHz. Since my external clock is 40MHz, I inserted a divide by 4 counter before feeding it to the CPU clock. But Quartus still says that max. clock is 11.xxx MHz. How's that, shouldn't it be now 44.xxx MHz, assuming the input counter can count to 44MHz. I am not using the input clock for any other purpose than dividing by 4. Another related question. ACEX1K datasheet says that the -3 devices do not have PLL. But Quartus always reports 0 of 1 PLL used, even when I specifically select -3 device. Which one is right, datasheet or Quartus? Thanks in advance. Pratip MukherjeeArticle: 63890
"David R Brooks" wrote: > :I don't really use inference for these constructs, I instantiate explicitly. > :Why would you speak Greek when you know you need to say something in French > :and you can speak French? Maybe 'cause I'm old school ... I still have my > :auto-stripping electric wire-wrap gun. > > Portability. An instantiated primitive locks you into that vendor's > technology. This is an often quoted reason to do many things. In my humble opinion --and particularly with high performance designs-- I see nothing wrong with HDL that is vendor-specific. Actually, high performance designs almost mandate this approach. The idea of jumping from one vendor to another is, again, my opinion, a fallacy for but the most trivial pushbutton-process designs. I mean, just the cost of designing and spinning a new board (with all associated risks) is enough to preclude one from making this move. One could, I suppose, argue that you'd build an HDL library that could be reused across designs or projects, regardless of the device or vendor. Again, I have a feeling that this is a part of reality only for JBOFF (just a bunch of flip-flops) designs. The minute you start to take advantage of device/vendor specific resources all bets are off. If you have to write device-specific descriptions to shove inference in the right direction you might as well use explicit instantiation. One variation on that theme, of course, would be writing intelligent VHDL code that would allow you to tell the HDL what sort of a device the module in question will be synthesized for. The code would make the appropriate changes to fit the device. But, again, this is device-specific code, as it would have to contain that specific intelligence. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 63891
> In my humble opinion --and particularly with high performance designs-- I Yeah I agree with that, when it comes to high performance designs. In order to squeeze every bit of performance out of our FPGAs, we have to take advantage of specific architectural features. And since we're always on the cutting edge of performance, we have completely new hardware for each evolution of our product, so we rarely have code reuse (that's why I like the concept of Design Patterns which advocates architecture reuse instead of code reuse). If one really wanted to be vendor independent, you would keep your design generic, lose performance in the design itself, and gain your performance by buying expensive chips and using more of them, but commercial projects are usually too price conscious to do that. Also we're always pushing the limits, so we tend to buy the highest end chips anyways. We can't upgrade any further. But yeah, if you're not at the bleeding edge (or at least your particular piece of reusable code isn't high performance, like a CPU interface), and there's a high chance that your code would actually be reused, then inference can be handy. As with all things, it depends on your situation.Article: 63892
"Subroto Datta" <sdatta@altera.com> wrote in message news:<JYaAb.3672$2C5.2593@newssvr33.news.prodigy.com>... > http://www.altera.com/support/software/nativelink/quartus2/glossary/def_vht. > html > > - Subroto Datta > Altera Corp. > > > > > A VHDL Test Bench File is the same as a standard VHDL test bench file, saved > with a .vht extension. > Hi, yes I read about it in the handbook, but HOW can I save a .vhd file as a .vht file? When I write a testbench file I can only save it as .vhd ! ? Thank you.Article: 63893
Well, maybe I am doing it totally wrong. Let me explain how I set it up:
- I have a directory with mhs, mss files code etc (lets call it bootldr). This
is the directory for the bootloader. The bootloader should do nothing with xilkernel.
- The bootloader should run in BRAM.
- I have a seperate directory for my final application (lets call it appl)
it's at the same level as the bootldr directory. The directory has its own makefile
and code, but no mhs, mss file etc. because it's using the same architecture as the
bootloader (this is why the xilkernel library block is placed in the mss file of the
bootloader). The application will use the xilkernel facilities (threads, semaphores etc.).
- The application should run in SDRAM.
- The makefile for the application is like this:
CC=mb-gcc
AR=mb-ar
CFLAGS = -O2 -g
SRC = ../src
INC = ../include
OBJS = appl.o hwinit.o debug.o hal.o leds.o crc.o can_sja1k.o irq.o pci.o pecx.o threads.o \
can.o timer.o
TOPDIR = ../mblaze/code
SYSTEMDIR = ../bootldr/mblaze
INCLUDEDIR = $(SYSTEMDIR)/include
LIBDIR = $(SYSTEMDIR)/lib
INCLUDES = -I$(INCLUDEDIR) -I$(INC)
LIBS = -L$(LIBDIR) -L$(TOPDIR)
LIBRARIES = -lw
# Linker options for the elf file
LFLAGS = -xl-mode-xilkernel -Wl,-defsym -Wl,_TEXT_START_ADDR=0xA0000000
VPATH = $(SRC)
all:
@echo "Makefile to build application which runs on SDRAM"
@echo " - SDRAM base address: 0xA0000000"
@echo " - application is placed in SDRAM by bootloader"
@echo ""
@echo "Usage: make appl"
appl: $(OBJS) makefile $(INCLUDEDIR)/xparameters.h
$(CC) $(CFLAGS) -o appl.elf $(OBJS) $(LFLAGS) $(LIBS) $(LIBRARIES)
@echo "appl.elf created at location 0xA0000000"
%.o:%.c
$(CC) $(CFLAGS) -c $< -o $@ $(INCLUDES)
%.o:%.s
$(CC) $(CFLAGS) -c $< -o $@
clean:
rm -f $(OBJS) *.elf
$(INCLUDEDIR)/xparameters.h:
$(error Make sure you have built the libraries for the bootloader)
So, in my opinion, the application is linking the xilkernel stuff by use of the -L
option in the LIBS variable. The bootloader is not linking xilkernel stuff, because it
does not use anything from the kernel (no threads or something else) or am I wrong at
this point and is something linked automatically when using the xilkernel library in
the mss file? Could you tell me if I have to define the process_table parameter in the
mss file in the described situation or not at all?!
TIA,
Frank
"mohan" <mohan@xilinx.com> wrote in message news:3FD0CA73.D3F0E9E5@xilinx.com...
Just curious - where does xilkernel fit in? Bootloader -> loads app at 0xA0000000 -> transfers
control to it. And the app seems to be configured as a stand-alone executable (not linked to xilkernel).
Frank wrote:
So when the bootloader is started, the xilkernel automattically tries to start executing
the code at address 0xA0000000?! But in my case there is no application at startup! I first
have to download it and then I jump from the code in the bootloader to the address of the
application (0xA0000000). Thus, if I understand it correctly, I MUST remove the process_table
parameter of the mss file?! (The bootloader should do nothing with xilkernel stuff, only my application is using it).Frank
Article: 63894Hi, you might want to try to write a .vqm netlist "Settings/Compiler Settings/Synthesis/Save a node-level netlist into a persistent source file (Verilog Quartus Mapping File)" after synthesis and use this netlist as your source file for place & route. All elements in the .vqm netlist will be persistent and it will be possible to do floorplanning based on this netlist. You can find more information on this flow in AN161. - Wolfgang Loewer El Camino GmbH "Subroto Datta" <sdatta@altera.com> schrieb im Newsbeitrag news:g1KAb.39062$v%7.8625@newssvr31.news.prodigy.com... > Hi cruzin, > > At present it is not possible to assign a location to something that > will be inferred by Quartus to use a specialized resource. In this case the > code should be written to explicitly use the altshifttaps function, so that > you can assign a location assignment. > > - Subroto Datta > Altera Corp. > > "cruzin" <cruiser144@hotmail.com> wrote in message > news:775730eb.0312070911.715c659e@posting.google.com... > > Hi, > > > > I have a chain of registers to delay a certain wide signal 5 clocks. > > Quartus infers altshifttaps from this, which is fine because it saves > > me LEs. > > > > Unfortunately the M512 where it places the inferred shift register > > causes a long delay to and from the rest of logic. I want to manually > > assign this inferred shift register to a specific M512 for timing > > purposes. > > > > My question is two-fold: > > > > 1/ I tried assigned the affected registers to an M512 using Assignment > > Editor. Quartus ends up telling me this is an invalid location. This > > leads me to my next question: > > > > 2/ Does quartus look at location assignments before inferring shift > > regs, DSP blocks, etc? If not, this would explain #1 because LEs can > > obviously not be assigned to TriMatrix memory. > > > > So is it possible to assign a location to something that I know will > > be inferred by Quartus to use a specialized resource? Or do I have to > > write my code to explicitely use the altshifttaps megafunction? > >Article: 63895
hi all, I have a 2.048 Mbps HDB3 data stream, now i should recover the clock from this data stream. For this i am using 16.384 MHZ(8xbaud) clock. First i detect the edges of the 2.048 Mbps data stream using 16.384 MHz(8xbaud)synchronously .The edges detected are used to reset a 3-bit counter synchronously running at 16.384 Mbps.Now if i take the MSB of the counter it will be of frequency 2.048 Mhz with the rising edge of the recovered clock approximately at the center of the bit duration. My problem is that the recoverd clock's rising edge will not be at the center of the bit duration.I want the recovered clock's rising edge in the middle of the bit duration . Should i increase the high frequency clock to 16xBaud, OR is there any other solution. rgds, praveenArticle: 63896
> Is it possible to run nios code from flash memory directly (assuming > I'm running at only 10MHz)? Or do I need a small bootstrap in local > rom to jump to the flash address? > Most existing designs I've seen have use an external ram and bootstrap > by copying code from the flash to the ram prior to branching to the > start address. > I tried a quick simulation. The only inputs I have to the nios cpu is > clock and reset. I don't see that it's trying to put the flash address > out on the bus. > Petter Petter, when you generate the core I'm 95% sure one of the advanced cpu config options is the reset address. If you change this to your flash address it might work. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone PCI development/eval board www.nialstewartdevelopments.co.ukArticle: 63897
praveen <praveen@cg-coreel.com> wrote: >hi all, >I have a 2.048 Mbps HDB3 data stream, now i should recover the clock >from this data stream. For this i am using 16.384 MHZ(8xbaud) clock. >First i detect the edges of the 2.048 Mbps data stream using 16.384 >MHz(8xbaud)synchronously .The edges detected are used to reset a 3-bit >counter synchronously running at 16.384 Mbps.Now if i take the MSB of >the counter it will be of frequency 2.048 Mhz with the rising edge of >the recovered clock approximately at the center of the bit duration. >My problem is that the recoverd clock's rising edge will not be at the >center of the bit duration.I want the recovered clock's rising edge in >the middle of the bit duration . Should i increase the high frequency >clock to 16xBaud, >OR is there any other solution. If the counter is assumed to be positive flank triggered. And you compare the value of the counter to a preset value on the negative flank. You should be able to grab the bit anywhere within each datavalidity range. (Clock <= Counter equals Preset) Btw, why isn't the recovered clocks's rising edge at the center ..? Parasitic capatitance? /PeterArticle: 63898
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> writes: > > Is it possible to run nios code from flash memory directly (assuming > > I'm running at only 10MHz)? Or do I need a small bootstrap in local > > rom to jump to the flash address? > > Most existing designs I've seen have use an external ram and bootstrap > > by copying code from the flash to the ram prior to branching to the > > start address. > > I tried a quick simulation. The only inputs I have to the nios cpu is > > clock and reset. I don't see that it's trying to put the flash address > > out on the bus. > > Petter > > Petter, when you generate the core I'm 95% sure one of the advanced > cpu config options is the reset address. If you change this to your > flash address it might work. I *did* set the reset address to the flash base. The nios supplied flash ip has an 8-bit interface only. However, I was hoping to see that it would try to do a read at address 0 (the flash base address and reset location) to fetch the first instruction. My plan was to try to make a new ptf file for a 16-bit flash interface and run a 16-bit nios directly from this. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 63899
> I *did* set the reset address to the flash base. The nios supplied > flash ip has an 8-bit interface only. However, I was hoping to see > that it would try to do a read at address 0 (the flash base address > and reset location) to fetch the first instruction. My plan was to try > to make a new ptf file for a 16-bit flash interface and run a 16-bit > nios directly from this. > Petter That seems odd, I would have thought that the program counter would reset to whatever value you set it to, and that this is the first address it would try to access. Let us know what's happening if you suss this out. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone PCI development/eval board www.nialstewartdevelopments.co.uk
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