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Messages from 63825

Article: 63825
Subject: Re: Slightly unmatched UART frequencies
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Fri, 05 Dec 2003 14:59:51 +1100
Links: << >>  << T >>  << A >>
On 04 Dec 2003 19:16:35 -0800, Eric Smith
<eric-no-spam-for-me@brouhaha.com> wrote:

>"Joel Kolstad" <JKolstad71HatesSpam@Yahoo.Com> writes:
>> Unless your (slightly slower) transmitter also has the capability of
>> producing shortened start (or stop) bits,
>
>An async transmitter should NEVER produce shortened start or stop bits!

Some [well engineered] systems will not work in all cases unless they
are able to use shortened stop bits.

I refer you to ITU-T recommendations V.110 and V.14.  (You could argue
that they aren't 'async', but still...)

Regards,
Allan.

Article: 63826
Subject: Re: Slightly unmatched UART frequencies
From: "Joel Kolstad" <JKolstad71HatesSpam@Yahoo.Com>
Date: Thu, 4 Dec 2003 21:53:09 -0800
Links: << >>  << T >>  << A >>
Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote:
> "Joel Kolstad" <JKolstad71HatesSpam@Yahoo.Com> writes:
>> You bright up a good subject, and you're absolutely correct that if you
>> continuously send data from one serial port at 9600.01bps to a receiver
>> at 9600, sooner or later there must be a buffer overflow.
>
> No, that will work just fine.  When a real UART is set for one stop bit,
> it actually only needs just over 1/2 a stop bit (usually 9/16).

If you read further into the thread, you'll see that the 'problem' is that
while, sure, you can receive all the characters coming in at 9600.01 bps
correctly, if you're then only going to re-transmit them (a data buffer-type
device) at 9600 bps, sooner or later you run out of storage for all the
accumulating bits.  That's what my 'there's no way around this' comment
meant.  In the interim, people have suggested lots of clever techiques to
deal with mismatched frequencies.

>> Nothing wrong with 16x oversampling (it will definitely help -- a
>> little),
>
> It helps a lot, if you do it right.

I'll buy that I suppose -- I've done just fine with 1x or 3x sampling with
software-based UARTs, but the mere fact that they were software-based meant
that they were only at, e.g., 9600bps or less and they happened to be over
short distances.  I.e., the data signals were always 'nice and clean.'

> An async transmitter should NEVER produce shortened start or stop bits!

Perhaps you should tell that to all the guys out there who've designed UARTs
that do just that?  Keep reading the thread -- if data comes into a data
forwarder at 9600.01 bps, you have to 'effectively' re-transmit at
9600.01bps as well.  You can do that by using a slightly faster clocking
frequency and/or slightly shortening your data bits -- your choice.

---Joel Kolstad



Article: 63827
Subject: VHDL: Different direction buses
From: arkagaz@yahoo.com (arkaitz)
Date: 4 Dec 2003 23:08:27 -0800
Links: << >>  << T >>  << A >>
Hi all,

It might be an obvious question but I have a doubt when assigning two buses
that are defined with opposite direction.

Here you are an example;

architecture behavioral of buses is
  signal bus_a: std_logic_vector (0 to 7);
  signal bus_b: std_logic_vector (7 downto 0);
  ...
begin

  -- this doesn't work
  bus_b <= bus_a;

  -- but don't know why this doesn't work
  process (bus_a)
  begin
    for i in bus_a'range loop
      bus_b (i) <= bus_a (i)
    end loop;

  -- this works
  process (bus_a)
  begin
    for i in bus_a'range loop
      bus_b(i) <= bus_a (bus_a'left - i);
    end loop;
  end process;

Does anybody have any idea why the second example doesn't work?

Thanks in advance.

Arkaitz.

Article: 63828
Subject: Re: Design analyse methods
From: muthu_nano@yahoo.co.in (Muthu)
Date: 4 Dec 2003 23:08:33 -0800
Links: << >>  << T >>  << A >>
Hi,

As in SignalTab from Altera, is there any way of doing similar in XILINX FPGAs?

Regards,
Muthu

Article: 63829
Subject: XILINX FPGA: DCM locked Signal
From: muthu_nano@yahoo.co.in (Muthu)
Date: 4 Dec 2003 23:20:19 -0800
Links: << >>  << T >>  << A >>
Hi,

Is the locked signal of DCM, is synchronous / Asynchronous ?

Regards,
Muthu

Article: 63830
Subject: Re: Hold violation and PLL
From: muthu_nano@yahoo.co.in (Muthu)
Date: 4 Dec 2003 23:34:30 -0800
Links: << >>  << T >>  << A >>
Hi,

I think Quartus software, is for Altera FPGAs... I haven't used Altera
FPGAs.

But in general i can give some options.

1. Try to pack the First Flip Flop in to IOBs.. This option is
available in Xilinx. I don't know about Altera.
2. Make the data path pad property to SLOW
3. Adjust the phase shift of PLL.. ie., delay it to caputre data in
next clock cycle
4. Else put some additonal dealy in the data path


Regards,
Muthu

shardendu@verizon.net (a2zasics) wrote in message news:<1c97c9ba.0312032206.3000a8e7@posting.google.com>...
> Hi,
> I have a problem on quartus II 3.0 software. I am using enhanced PLL
> and a set of input registers with FAST INPUT REG = on constraint. Thus
> i get about 1 ns delay of pad to IOB flop on datapath. However delay
> of clock from PLL to IOB  flops is higher around 3 ns. Thus i get a
> hold violation of 2 ns. Anyone has any suggestions as to how i can
> eliminate this hold violation.
> 
> Shardendu

Article: 63831
Subject: Re: Ideal Development Machine Specifications
From: "Vinh Pham" <a@a.a>
Date: Fri, 05 Dec 2003 08:22:11 GMT
Links: << >>  << T >>  << A >>
> I'd rather have my Matrox dual head card with two big monitors,
> I recon it makes me a fair bit more productive.

Yeah the extra desktop space is rather nice.  Do you have LCD screens also
by chance?



Article: 63832
Subject: Re: process table for XMK
From: "Frank" <someone@work.com>
Date: Fri, 5 Dec 2003 09:48:20 +0100
Links: << >>  << T >>  << A >>
So when the bootloader is started, the xilkernel automattically tries to start executing the code at address 0xA0000000?! But in my case there is no application at startup! I first have to download it and then I jump from the code in the bootloader to the address of the application (0xA0000000). Thus, if I understand it correctly, I MUST remove the process_table parameter of the mss file?! (The bootloader should do nothing with xilkernel stuff, only my application is using it).

Frank
  "mohan" <mohan@xilinx.com> wrote in message news:3FCFACBF.E47332F4@xilinx.com...
  xilkernel maintains an internal table of ready/waiting/running processes and their priorities. 
  This table can be statically initialized by specifying a list of process start-addresses and priorities in the MSS (assign to the PROCESS_TABLE parameter). 
  On startup xilkernel starts running the highest priority process in this table. 
  In your example, the process table is initialized with a single element with priority 1 and start address 0xA0000000 so xilkernel will start executing the code at this address. 
  If you want two threads, this main application can start up the other other thread/process using the create_process() or create_thread() function, or you can write the other thread as a separate application with a different start address, and specify that on the PROCESS_TABLE list in the MSS file. 
  -- 
    Mohan 
    

  Frank wrote: 

    Hi, 
    Could anyone explain the meaning of the process_table parameter in the mss 
    file (when using the xilkernel). I have a bootloader with the following 
    stuff in the mss file: 

    BEGIN LIBRARY 
     PARAMETER LIBRARY_NAME = xilkernel 
     PARAMETER LIBRARY_VER = 1.00.a 
     PARAMETER MAX_PROCS = 1 
     PARAMETER PROCESS_TABLE = ((0xA0000000, 1)) 
     PARAMETER CONFIG_THREAD_SUPPORT = true 
     PARAMETER MAX_THREADS = 2 
     PARAMETER THREAD_STACK_SIZE = 0x100 
     PARAMETER CONFIG_SEMA = true 
     PARAMETER MAX_SEMA = 1 
    END 

    Besides that, I have an application (with his own makefile) which should be 
    run from address 0xA0000000, so in the makefile I use the linker option 

    LFLAGS = -xl-mode-xilkernel -Wl,-defsym -Wl,_TEXT_START_ADDR=0xA0000000 

    When I disassemble the .elf file of the application, it's all ok (addresses 
    starts from 0xA0000000). So what is the meaning of the address in the 
    process_table parameter in the mss file of the bootloader?? Does it make any 
    sense? Or do I not need the process stuff at all, but just use the thread 
    parameters (I only want an application which contains two threads)?! 

    Thanks, 
    Frank



Article: 63833
Subject: Re: Ideal Development Machine Specifications
From: "Eric BATUT" <grostuba@ifrance.com>
Date: Fri, 5 Dec 2003 01:42:43 -0800
Links: << >>  << T >>  << A >>
Thanks a lot to everyone for the various advices. 
For the techie lovers out there, the video car will be a NVidia Quadro 4 280 NVS
 with dual-screen output and DVI adapters, for the two Eizo 19" LCD screens. 

And yes, I'm drooling while I'm writing this... 

Once again, thanks a lot, and have a nice day... 

Eric 



Article: 63834
Subject: Re: Different direction buses
From: "Alan Fitch" <alan.fitch@doulos.com>
Date: Fri, 5 Dec 2003 09:48:12 -0000
Links: << >>  << T >>  << A >>
> Hi all,
>
> It might be an obvious question but I have a doubt when assigning
two buses
> that are defined with opposite direction.
>
> Here you are an example;
>
> architecture behavioral of buses is
>   signal bus_a: std_logic_vector (0 to 7);
>   signal bus_b: std_logic_vector (7 downto 0);
>   ...
> begin
>
>   -- this doesn't work
>   bus_b <= bus_a;
>


What do you meant "it doesn't work?". It works fine! In
VHDL vectors are assigned left to right, *regardless of how
they are declared*. So that code says

   bus_b(7) <= bus_a(0);
   bus_b(6) <= bus_a(1);
   bus_b(5) <= bus_a(2);
   bus_b(4) <= bus_a(3);
   bus_b(3) <= bus_a(4);
   bus_b(2) <= bus_a(5);
   bus_b(1) <= bus_a(6);
   bus_b(0) <= bus_a(7);

Which looks fine to me. That's how VHDL works...

>   -- but don't know why this doesn't work
>   process (bus_a)
>   begin
>     for i in bus_a'range loop
>       bus_b (i) <= bus_a (i)
>     end loop;

Again, what do you mean "it doesn't work"?

bus_a'range gives you  "0 to 7", so the loop results in

      bus_b(0) <= bus_a(0);
      bus_b(1) <= bus_a(1);
      ...
      bus_b(7) <= bus_a(7);

which again works fine. Of course it does something different
from your first example...

>
>   -- this works
>   process (bus_a)
>   begin
>     for i in bus_a'range loop
>       bus_b(i) <= bus_a (bus_a'left - i);
>     end loop;
>   end process;
>

This does
   bus_b(0) <= bus_a(0-0);
   bus_b(1) <= bus_b(0-1); -- error!

so should not run. It should give a "index out of range error".
You may only see that at run time however, not at compile time.

> Does anybody have any idea why the second example doesn't work?
>

I believe your first two examples "work", and the last example doesn't
because of the indexing error.

What exactly are you trying to achieve?

kind regards

Alan



-- 
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223                          mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573                           Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.


Article: 63835
Subject: Re: Ideal Development Machine Specifications
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Fri, 5 Dec 2003 11:26:32 -0000
Links: << >>  << T >>  << A >>

Vinh Pham <a@a.a> wrote in message
news:TeXzb.33$R9.22@twister.socal.rr.com...
> > I'd rather have my Matrox dual head card with two big monitors,
> > I recon it makes me a fair bit more productive.
>
> Yeah the extra desktop space is rather nice.  Do you have LCD screens also
> by chance?

Unfortunately not :-(

Although the price of a decent 17" screen's down to
just over 300, and the screen area is nearly as big
as my 21" monitor. The thinner surrounds would mean
there would be less breaking up the desktop too.

Matrox also do 4 monitor output graphics cards :-)


Nial.

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk



Article: 63836
Subject: Re: increase NIOS processor clock speed on APEX20K200E device
From: karlIGNORETHISPART@chello.nl (Karl)
Date: 5 Dec 2003 04:20:05 -0800
Links: << >>  << T >>  << A >>
fredrik_he_lang@hotmail.com (Fredrik) wrote in message news:<77a94d51.0312040505.76d6e2cf@posting.google.com>...
> jwing23@hotmail.com (J-Wing) wrote in message news:<d6e7734d.0312020835.42729684@posting.google.com>...
> > The NIOS processor runs on a 33.333MHz clock. How can I increase the
> > speed of the clock and what is the maximum speed which can be
> > achieved? Please advice.
> Hi,
> One way of achiving this would be to remove the Y1 clock source and
> put a faster one on to this.(You need to check the schematics for
> pinning). Second question you can always check in the timing analys
> for fmax of your design, if I rember correctly you should be able to
> get 50-70MHz depending on design. (You need to change target freqency
> in the SOPC builder also).
> Cheers
> Fredrik

Hi,

Did some playing around with the Nios V3.1 in the APEX 20K200E and
could get 74 MHz with a small 16 bit core, 2 KByte on-chip memory and
a UART. Any bigger system will have lower performance.

Karl.

Article: 63837
Subject: Re: XILINX FPGA: DCM locked Signal
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 05 Dec 2003 05:55:17 -0800
Links: << >>  << T >>  << A >>
Muthu,

It is generated on the rising edge of CLKIN -- synchronous.

Austin

Muthu wrote:
> Hi,
> 
> Is the locked signal of DCM, is synchronous / Asynchronous ?
> 
> Regards,
> Muthu


Article: 63838
Subject: Re: VHDL: Different direction buses
From: arkagaz@yahoo.com (arkaitz)
Date: 5 Dec 2003 06:00:05 -0800
Links: << >>  << T >>  << A >>
Upppsss,

I'm sorry. The second example is wrong,


arkagaz@yahoo.com (arkaitz) wrote in message news:<c1408b8c.0312042308.27180437@posting.google.com>...
> Hi all,
> 
> It might be an obvious question but I have a doubt when assigning two buses
> that are defined with opposite direction.
> 
> Here you are an example;
> 
> architecture behavioral of buses is
>   signal bus_a: std_logic_vector (0 to 7);
>   signal bus_b: std_logic_vector (7 downto 0);
>   ...
> begin
> 
>   -- this doesn't work
>   bus_b <= bus_a;
> 
>   -- but don't know why this doesn't work
>   process (bus_a)
>   begin
>     for i in bus_a'range loop
>       bus_b (i) <= bus_a (i)
>     end loop;
> 
>   -- this works
>   process (bus_a)
>   begin
>     for i in bus_a'range loop
>       bus_b(i) <= bus_a (bus_a'left - i);
        bus_b(i) <= bus_a (bus_a'right - i); -- better like this
>     end loop;
>   end process;
> 
> Does anybody have any idea why the second example doesn't work?
> 
> Thanks in advance.
> 
> Arkaitz.

Article: 63839
Subject: VHDL-Testbench-Simulation in QuartusII
From: ALuPin@web.de (ALuPin)
Date: 5 Dec 2003 06:19:33 -0800
Links: << >>  << T >>  << A >>
Hi @ all,

how can I simulate a testbench written in VHDL in QuartusII 3.0
software?

Do I have to save it as a .vhd file or what kind of file is needed
to simulate with Altera-Modelsim?

Under SETTINGS --> EDA TOOL SETTINGS --> SIMULATION I choose
ModelSim-Altera
Under SETTINGS --> EDA TOOL SETTINGS ---> SIMULATION 
--> ADVANCED
there can be chosen "Test Bench Mode". But when I want to select
the Test Bench File there are only .vht files?
How can I save a .vhd file as a .vht file?

Thank you very much

Kind regards
A.Lapa

Article: 63840
Subject: Dual-port and single-port BlockRAM instantiation
From: arkagaz@yahoo.com (arkaitz)
Date: 5 Dec 2003 06:23:17 -0800
Links: << >>  << T >>  << A >>
Hi all,

I am working with a 1 million gate Virtex II FPGA. I am instantiating
large amounts of Block RAMs in my design and even though I am using
Single-Port ones, I would like to know if there would be a trouble to
instantiate them as Dual-Port ones. I mean, would it need twice the Block RAMs
I am using now, or would it just configure them as Dual-Port?

Thanks,

Arkaitz.

Article: 63841
Subject: Re: Floorplanning techniques
From: muthu_nano@yahoo.co.in (Muthu)
Date: 5 Dec 2003 06:45:57 -0800
Links: << >>  << T >>  << A >>
Hi,

For FPGAs, the Vendor tools will do the the floor planning job in a
better way. You no need to spend time on that. All you need to know,
how to constraint the tool to make them to do what you want exactly.

like clock frequency, Input setup-hold, Output setup-hold and so on...
with this; tool will place the logics to acheive your timing
requiement.


Regards,
Muthu



richieb@rediffmail.com (richie singh) wrote in message news:<a0238c18.0312041811.56cc43d9@posting.google.com>...
> Hi, 
> I recently started working with FPGAs and am would like to learn about
> floorplanning techniques. Could someone point me to documents or
> design guides dealing with what issues should be kept in mind while
> floorplanning a complex design..
> Thanks to all who reply!!
> R.B.

Article: 63842
Subject: Re: Xilinx DDR output with tri-state....
From: johnp3+nospam@probo.com (John Providenza)
Date: 5 Dec 2003 07:39:04 -0800
Links: << >>  << T >>  << A >>
I found an answer, and here's the code to implement byte-wide
bi-directional DDR pins.  I believe part of the magic it took
to make this work was to
  a) keep hierarchy
  b) pass the tri-state enable signals as an 8 bit bus so that
     XST doesn't optimize them into a single signal.
  c) use 8 copies of the tri-state 'assign'


//                              DDR_TRI
// This module provides a BYTE wide, Bi-directional DDR pad interface
with
// tri-state flip-flop embedded in the IOB.
//
// NOTEs:
//      a) you need to bring in 8 copies of the tri-state control
signal so
//      that XST doesn't optimize the tri_q signals improperly
//      
//      b) you must use 8 of the 
//              assign foo[x] = enable[x] ? 1'bz : q[x];
//         if you try to use
//              assign foo = enable ? 8'bz : q;
//         the tri-state control flip-flop doesn't get packed into the
IOB
//
module ddr_tri(
    clk_out,
    clk_out_n,
    clk_in,
    clk_in_n,
    data_out_even,
    data_out_odd,
    data_in_even,
    data_in_odd,
    tri_ctl,
    dq
);
input           clk_out;
input           clk_out_n;
input           clk_in;
input           clk_in_n;
input   [7:0]   data_out_even;
input   [7:0]   data_out_odd;
output  [7:0]   data_in_even;
output  [7:0]   data_in_odd;
input   [7:0]   tri_ctl;
inout   [7:0]   dq;

reg     [7:0]   data_in_even;
reg     [7:0]   data_in_odd;
reg     [7:0]   tri_q;
wire    [7:0]   fddq;

//synthesis attribute IOB of tri_q is "TRUE"
always @(posedge clk_out_n)
    tri_q <= tri_ctl;
	 
FDDRRSE u0ddr_q (.C0(clk_out_n),.C1(clk_out),.R(1'b0),.S(1'b0),.CE(1'b1),.D0(data_out_even[0]),.D1(data_out_odd[0]),.Q(fddq[0]));
FDDRRSE u1ddr_q (.C0(clk_out_n),.C1(clk_out),.R(1'b0),.S(1'b0),.CE(1'b1),.D0(data_out_even[1]),.D1(data_out_odd[1]),.Q(fddq[1]));
FDDRRSE u2ddr_q (.C0(clk_out_n),.C1(clk_out),.R(1'b0),.S(1'b0),.CE(1'b1),.D0(data_out_even[2]),.D1(data_out_odd[2]),.Q(fddq[2]));
FDDRRSE u3ddr_q (.C0(clk_out_n),.C1(clk_out),.R(1'b0),.S(1'b0),.CE(1'b1),.D0(data_out_even[3]),.D1(data_out_odd[3]),.Q(fddq[3]));
FDDRRSE u4ddr_q (.C0(clk_out_n),.C1(clk_out),.R(1'b0),.S(1'b0),.CE(1'b1),.D0(data_out_even[4]),.D1(data_out_odd[4]),.Q(fddq[4]));
FDDRRSE u5ddr_q (.C0(clk_out_n),.C1(clk_out),.R(1'b0),.S(1'b0),.CE(1'b1),.D0(data_out_even[5]),.D1(data_out_odd[5]),.Q(fddq[5]));
FDDRRSE u6ddr_q (.C0(clk_out_n),.C1(clk_out),.R(1'b0),.S(1'b0),.CE(1'b1),.D0(data_out_even[6]),.D1(data_out_odd[6]),.Q(fddq[6]));
FDDRRSE u7ddr_q (.C0(clk_out_n),.C1(clk_out),.R(1'b0),.S(1'b0),.CE(1'b1),.D0(data_out_even[7]),.D1(data_out_odd[7]),.Q(fddq[7]));

assign `Td dq[0] = tri_q[0] ? 1'bz : fddq[0];
assign `Td dq[1] = tri_q[1] ? 1'bz : fddq[1];
assign `Td dq[2] = tri_q[2] ? 1'bz : fddq[2];
assign `Td dq[3] = tri_q[3] ? 1'bz : fddq[3];
assign `Td dq[4] = tri_q[4] ? 1'bz : fddq[4];
assign `Td dq[5] = tri_q[5] ? 1'bz : fddq[5];
assign `Td dq[6] = tri_q[6] ? 1'bz : fddq[6];
assign `Td dq[7] = tri_q[7] ? 1'bz : fddq[7];

//synthesis attribute IOB of data_in_even is "TRUE"
//synthesis attribute IOB of data_in_odd is "TRUE"
always @(posedge clk_in)
    data_in_even        <= dq;

always @(posedge clk_in_n)
    data_in_odd         <= dq;

endmodule



johnp3+nospam@probo.com (John Providenza) wrote in message news:<349ef8f4.0312040932.76fe722@posting.google.com>...
> I'm trying to create DDR SRAM data I/O pads and am having problems 
> "pushing" the tri-state enable flip-flop into the IOB. I get the 
> DDR in/out DATA flip-flops packed into the IOB correctly, but XST 5.2
> refuses to use the IOB's tri-state enable flip-flop.  This is
> targeted at a V2-Pro part.
> 
> I'm "hand" instantiating the output DATA ddr "flops", but, for
> a variety of reasons, I REALLY don't want to hand instantiate
> components to control the tri-state, I'd really like to infer them.
> 
> In this design the tri-state control signals are not really "ddr",
> they only need to change on posedge clock.
> 
> 
> Here's a snippet of my code:
> 
> // instantiate 72 DDR output cells
> FDDRRSE u0ddr_q (
>     .C0    (clk_outn),          .C1    (clk_out),
>     .R     (1'b0),              .S     (1'b0),          .CE    (1'b1),
>     .D0    (sr_dout[0]),        .D1    (sr_dout[72]),   .Q     (sr_q[0])
> );
> FDDRRSE u1ddr_q (
>     .C0    (clk_outn),          .C1    (clk_out),
>     .R     (1'b0),              .S     (1'b0),          .CE    (1'b1),
>     .D0    (sr_dout[1]),        .D1    (sr_dout[73]),   .Q     (sr_q[1])
> );
> FDDRRSE u2ddr_q (
>     .C0    (clk_outn),          .C1    (clk_out),
>     .R     (1'b0),              .S     (1'b0),          .CE    (1'b1),
>     .D0    (sr_dout[2]),        .D1    (sr_dout[74]),   .Q     (sr_q[2])
> );
> ......
> 
> // infer the tri-state output control
> // try to get the control bit 'pushed' into the IOB tri-state control f/f
> reg   sr_oe;
> // synthesis attribute IOB of sr_oe "TRUE"
> always @(posedge clk_outn)
>     sr_oe       <= bar;
> 
> assign sram_dq[71:0] = (sr_oe) ? 72'bz : sr_q[71:0];
> 
> a) I have tried a BUNCH of variations on this scheme with no luck.
>      1) force sr_oe to be a 72 bit vector
>      2) add KEEP attributes
>      3) remove the IOB attribute
>      4) change the tri-state assign statement to be 72 individual
>         statements, one for each bit.
>     
> b) I have set the synthesis options to use IOB flip-flops.
> 
> I suspect the Xilinx tools don't like the combination of instantiated
> DDR data output flops and inferred tri-state registers pushed into the
> IOB.
> 
> Any ideas?
> 
> John P

Article: 63843
Subject: Re: Dual-port and single-port BlockRAM instantiation
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 05 Dec 2003 08:54:03 -0800
Links: << >>  << T >>  << A >>
A dual-port BlockRAM has exactly the same data storage capacity as a
single-port RAM, 18Kbits in the Virtex-II case.
As a dual-port RAM it just has an additional access ( read or write)
port, nothing else.

Peter Alfke, Xilinx Applications
==================
arkaitz wrote:
> 
> Hi all,
> 
> I am working with a 1 million gate Virtex II FPGA. I am instantiating
> large amounts of Block RAMs in my design and even though I am using
> Single-Port ones, I would like to know if there would be a trouble to
> instantiate them as Dual-Port ones. I mean, would it need twice the Block RAMs
> I am using now, or would it just configure them as Dual-Port?
> 
> Thanks,
> 
> Arkaitz.

Article: 63844
Subject: Re: Dual-port and single-port BlockRAM instantiation
From: "John_H" <johnhandwork@mail.com>
Date: Fri, 05 Dec 2003 16:57:13 GMT
Links: << >>  << T >>  << A >>
Your tools may combine two single port memories into one dual-port if the
memory sizes are compatible.  By instantiating the dual-port, you no longer
have the option of the combination.  The tool flow you use may not take
advantage of this packing anyway, so the point might be moot.

Check what your BlockRAM usage is - see if the tools are already
implementing two single-port memories in a dual-port.  As long as the total
number of BlockRAMs you infer and instatiate fit within the available number
of BlockRAMs for the device, you're set.


"arkaitz" <arkagaz@yahoo.com> wrote in message
news:c1408b8c.0312050623.52b9b1fa@posting.google.com...
> Hi all,
>
> I am working with a 1 million gate Virtex II FPGA. I am instantiating
> large amounts of Block RAMs in my design and even though I am using
> Single-Port ones, I would like to know if there would be a trouble to
> instantiate them as Dual-Port ones. I mean, would it need twice the Block
RAMs
> I am using now, or would it just configure them as Dual-Port?
>
> Thanks,
>
> Arkaitz.



Article: 63845
Subject: Re: Synchronization between CPU-clock and FPGA clock.
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 05 Dec 2003 10:05:10 -0800
Links: << >>  << T >>  << A >>
One Day & A Knight wrote:
> Hi,
> 
> I want to know how to properly interface between the CPU clock and the FPGA
> clock.
> My board has separate clocks for CPU and FPGA.


Make a ready with a fpga register and synch it to cpu_clk.
Make an ack  bit with a cpu port and synch it to fpga_clk.

Why not run the fpga on the cpu clk?

  -- Mike Treseler


Article: 63846
Subject: Re: process table for XMK
From: mohan <mohan@xilinx.com>
Date: Fri, 05 Dec 2003 10:12:04 -0800
Links: << >>  << T >>  << A >>
Just curious - where does xilkernel fit in? Bootloader -> loads app at 0xA0000000 -> transfers 
control to it. And the app seems to be configured as a stand-alone executable (not linked to xilkernel). 
Frank wrote: 

So when the bootloader is started, the xilkernel automattically tries to start executing the 
code at address 0xA0000000?! But in my case there is no application at startup! I first have 
to download it and then I jump from the code in the bootloader to the address of the application 
(0xA0000000). Thus, if I understand it correctly, I MUST remove the process_table parameter of 
the mss file?! (The bootloader should do nothing with xilkernel stuff, only my application is 
using it).
Frank



Article: 63847
Subject: "PIPELINE MODEL" constant in EDK 6.1
From: arkagaz@yahoo.com (arkaitz)
Date: 5 Dec 2003 10:12:11 -0800
Links: << >>  << T >>  << A >>
Hi all,

Has someone tried to attach an user logic core to the OPB bus of
MicroBlaze
using EDK 6.1?

In this new version of EDK there is a new constant called PIPELINE
MODEL that you can find in the user core reference design.

Here you are the options that it gives you:

--USER-- change PIPELINE_MODEL constant below to desired pipeline
model for
--       user logic:
--          1 = include OPB-In pipeline registers
--          2 = include IP pipeline registers
--          3 = include OPB-In and IP pipeline registers
--          4 = include OPB-Out pipeline registers
--          5 = include OPB-In and OPB-Out pipeline registers
--          6 = include IP and OPB-Out pipeline registers
--          7 = include OPB-In, IP, and OPB-Out pipeline registers


Does anybody know where can I find some information related to this?

Thanks in advance, 

Arkaitz.

Article: 63848
Subject: Re: VHDL-Testbench-Simulation in QuartusII
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 05 Dec 2003 10:14:32 -0800
Links: << >>  << T >>  << A >>
ALuPin wrote:

> how can I simulate a testbench written in VHDL in QuartusII 3.0
> software?

Use modelsim.

related thread:

http://groups.google.com/groups?q=ranjith+oe_demo

-- Mike Treseler


Article: 63849
Subject: Re: Hold violation and PLL
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 05 Dec 2003 10:23:12 -0800
Links: << >>  << T >>  << A >>
a2zasics wrote:

> hold violation of 2 ns. Anyone has any suggestions as to how i can
> eliminate this hold violation.

What happens if you remove the constraint?

  -- Mike Treseler




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